[coreboot-gerrit] New patch to review for coreboot: skylake: ACPI: Remove SerialIO ACPI mode code
Patrick Georgi (pgeorgi@google.com)
gerrit at coreboot.org
Mon Sep 7 18:42:10 CET 2015
Patrick Georgi (pgeorgi at google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11536
-gerrit
commit 73c4a6dd93d45298cd436aa45bd2dfc1db4cfa26
Author: Duncan Laurie <dlaurie at chromium.org>
Date: Thu Aug 27 16:58:23 2015 -0700
skylake: ACPI: Remove SerialIO ACPI mode code
Skylake moves back to having SerialIO devices be enumerated
as PCI devices instead of putting them all in ACPI mode.
There is currently no code that populates the device_nvs
fields so all the ACPI code to support that is dead.
Additionally because it contains _PS0/_PS3 methods that
causes the kernel to not use the standard PCIe PME handlers
and results in confusing messages at boot about not being
able to transition to a non-D0 state from D3.
BUG=chrome-os-partner:44622
BRANCH=none
TEST=build and boot on glados and ensure I2C devices work
Change-Id: Id0112830211707ba3d67d4dda29dd93397b5b180
Signed-off-by: Patrick Georgi <pgeorgi at chromium.org>
Original-Commit-Id: f7dddad9c2269abd292346e35ebd0b4ca2efe72b
Original-Change-Id: Ie5e40b5d73cd3a4d19b78f0df4ca015dccb6f5f6
Original-Signed-off-by: Duncan Laurie <dlaurie at chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/295909
Original-Reviewed-by: Aaron Durbin <adurbin at chromium.org>
---
src/soc/intel/skylake/acpi/device_nvs.asl | 60 ----
src/soc/intel/skylake/acpi/globalnvs.asl | 3 -
src/soc/intel/skylake/acpi/serialio.asl | 552 +-----------------------------
src/soc/intel/skylake/include/soc/nvs.h | 5 +-
4 files changed, 20 insertions(+), 600 deletions(-)
diff --git a/src/soc/intel/skylake/acpi/device_nvs.asl b/src/soc/intel/skylake/acpi/device_nvs.asl
deleted file mode 100644
index e84d25a..0000000
--- a/src/soc/intel/skylake/acpi/device_nvs.asl
+++ /dev/null
@@ -1,60 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2014 Google Inc.
- * Copyright (C) 2015 Intel Corporation.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc.
- */
-
-/* Device Enabled in ACPI Mode */
-
-S0EN, 8, // I2C0 Enable
-S1EN, 8, // I2C1 Enable
-S2EN, 8, // I2C2 Enable
-S3EN, 8, // I2C3 Enable
-S4EN, 8, // I2C4 Enable
-S5EN, 8, // I2C5 Enable
-S6EN, 8, // SPI0 Enable
-S7EN, 8, // SPI1 Enable
-S8EN, 8, // UART0 Enable
-S9EN, 8, // UART1 Enable
-SAEN, 8, // UART2 Enable
-
-/* BAR 0 */
-S0B0, 32, // I2C0 BAR0
-S1B0, 32, // I2C1 BAR0
-S2B0, 32, // I2C2 BAR0
-S3B0, 32, // I2C3 BAR0
-S4B0, 32, // I2C4 BAR0
-S5B0, 32, // I2C5 BAR0
-S6B0, 32, // SPI0 BAR0
-S7B0, 32, // SPI1 BAR0
-S8B0, 32, // UART0 BAR0
-S9B0, 32, // UART1 BAR0
-SAB0, 32, // UART2 BAR0
-
-/* BAR 1 */
-S0B1, 32, // I2C0 BAR1
-S1B1, 32, // I2C1 BAR1
-S2B1, 32, // I2C2 BAR1
-S3B1, 32, // I2C3 BAR1
-S4B1, 32, // I2C4 BAR1
-S5B1, 32, // I2C5 BAR1
-S6B1, 32, // SPI0 BAR1
-S7B1, 32, // SPI1 BAR1
-S8B1, 32, // UART0 BAR1
-S9B1, 32, // UART1 BAR1
-SAB1, 32, // UART2 BAR1
-
diff --git a/src/soc/intel/skylake/acpi/globalnvs.asl b/src/soc/intel/skylake/acpi/globalnvs.asl
index b41fa42..0208198 100644
--- a/src/soc/intel/skylake/acpi/globalnvs.asl
+++ b/src/soc/intel/skylake/acpi/globalnvs.asl
@@ -69,9 +69,6 @@ Field (GNVS, ByteAcc, NoLock, Preserve)
Offset (0x100),
#include <vendorcode/google/chromeos/acpi/gnvs.asl>
- /* Device specific */
- Offset (0x1000),
- #include "device_nvs.asl"
}
/* Set flag to enable USB charging in S5 */
diff --git a/src/soc/intel/skylake/acpi/serialio.asl b/src/soc/intel/skylake/acpi/serialio.asl
index d3dca7f..da38891 100644
--- a/src/soc/intel/skylake/acpi/serialio.asl
+++ b/src/soc/intel/skylake/acpi/serialio.asl
@@ -1,7 +1,7 @@
/*
* This file is part of the coreboot project.
*
- * Copyright (C) 2014 Google Inc.
+ * Copyright (C) 2015 Google Inc.
* Copyright (C) 2015 Intel Corporation.
*
* This program is free software; you can redistribute it and/or modify
@@ -18,603 +18,89 @@
* Foundation, Inc.
*/
-// Intel Serial IO Devices in ACPI Mode
-
-/* Serial IO Device BAR0 and BAR1 is 4KB */
-#define SIO_BAR_LEN 0x1000
-
-/* Put SerialIO device in D0 state */
-/* Arg0 - BAR1 of device */
-/* Arg1 - Set if device is in ACPI mode */
-
-Method (LPD0, 2, Serialized)
-{
- /* PCI mode devices will be handled by OS PCI bus driver */
- If (LEqual (Arg1, 0)) {
- Return
- }
-
- OperationRegion (SPRT, SystemMemory, Add (Arg0, 0x84), 4)
- Field (SPRT, DWordAcc, NoLock, Preserve)
- {
- SPCS, 32
- }
-
- And (SPCS, 0xFFFFFFFC, SPCS)
- /* Read back after writing */
- Store (SPCS, Local0)
-}
-
-/* Put SerialIO device in D3 state */
-/* Arg0 - BAR1 of device */
-/* Arg1 - Set if device is in ACPI mode */
-
-Method (LPD3, 2, Serialized)
-{
- /* PCI mode devices will be handled by OS PCI bus driver */
- If (LEqual (Arg1, 0)) {
- Return
- }
- OperationRegion (SPRT, SystemMemory, Add (Arg0, 0x84), 4)
- Field (SPRT, DWordAcc, NoLock, Preserve)
- {
- SPCS, 32
- }
- Or (SPCS, 0x3, SPCS)
- Store (SPCS, Local0) // Read back after writing
-}
-
-/* Serial IO Resource Consumption for BAR1 */
-Device (SIOR)
-{
- Name (_HID, EISAID("PNP0C02"))
- Name (_UID, 5)
- Method(ADDB,3,Serialized) {
- Name (BUFF, ResourceTemplate()
- {
- Memory32Fixed (ReadWrite, 0x00000000, 0x1000, BUF)
- })
- CreateDWordField(BUFF,BUF._BAS,ADDR)
- CreateDWordField(BUFF,BUF._LEN,LENG)
- Store(ResourceTemplate(){}, Local0)
- //Return (RBUF)
- }
-}
+/* Intel Serial IO Devices */
Device (I2C0)
{
- /* Serial IO I2C0 Controller */
- Name (_HID,"INT3442")
- Name (_UID, 1)
Name (_ADR, 0x00150000)
+ Name (_DDN, "Serial IO I2C Controller 0")
+
Name (SSCN, Package () { 432, 507, 30 })
Name (FMCN, Package () { 72, 160, 30 })
-
- /* BAR0 is assigned during PCI enumeration and saved into NVS */
- Name (RBUF, ResourceTemplate ()
- {
- Memory32Fixed (ReadWrite, 0x00000000, 0x00000000, BAR0)
- Interrupt (ResourceConsumer, Level, ActiveLow, Shared, , , )
- { LPSS_I2C0_IRQ }
- })
-
- Method (_CRS, 0, NotSerialized)
- {
- /* Update BAR0 address and length if set in NVS */
- If (LNotEqual (\S0B0, Zero)) {
- CreateDwordField (^RBUF, ^BAR0._BAS, B0AD)
- CreateDwordField (^RBUF, ^BAR0._LEN, B0LN)
- Store (\S0B0, B0AD)
- Store (SIO_BAR_LEN, B0LN)
- }
- Return (RBUF)
- }
-
- Method (_STA, 0, NotSerialized)
- {
- If (LEqual (\S0EN, 0)) {
- Return (0x0)
- } Else {
- Return (0xF)
- }
- }
-
- Method (_PS0, 0, Serialized)
- {
- ^^LPD0 (\S0B1, \S0EN)
- }
-
- Method (_PS3, 0, Serialized)
- {
- ^^LPD3 (\S0B1, \S0EN)
- }
-
}
Device (I2C1)
{
- /* Serial IO I2C1 Controller */
- Name (_HID,"INT3443")
- Name (_UID, 1)
Name (_ADR, 0x00150001)
+ Name (_DDN, "Serial IO I2C Controller 1")
+
Name (SSCN, Package () { 528, 640, 30 })
Name (FMCN, Package () { 128, 160, 30 })
Name (FPCN, Package () { 48, 64, 30})
-
- /* BAR0 is assigned during PCI enumeration and saved into NVS */
- Name (RBUF, ResourceTemplate ()
- {
- Memory32Fixed (ReadWrite, 0x00000000, 0x00000000, BAR0)
- Interrupt (ResourceConsumer, Level, ActiveLow, Shared, , , )
- { LPSS_I2C1_IRQ }
- })
-
- Method (_CRS, 0, NotSerialized)
- {
- /* Update BAR0 address and length if set in NVS */
- If (LNotEqual (\S1B0, Zero)) {
- CreateDwordField (^RBUF, ^BAR0._BAS, B0AD)
- CreateDwordField (^RBUF, ^BAR0._LEN, B0LN)
- Store (\S1B0, B0AD)
- Store (SIO_BAR_LEN, B0LN)
- }
- Return (RBUF)
- }
-
- Method (_STA, 0, NotSerialized)
- {
- If (LEqual (\S1EN, 0)) {
- Return (0x0)
- } Else {
- Return (0xF)
- }
- }
-
- Method (_PS0, 0, Serialized)
- {
- ^^LPD0 (\S1B1, \S1EN)
- }
-
- Method (_PS3, 0, Serialized)
- {
- ^^LPD3 (\S1B1, \S1EN)
- }
}
-
Device (I2C2)
{
- /* Serial IO I2C1 Controller */
- Name (_HID,"INT3444")
- Name (_UID, 1)
Name (_ADR, 0x00150002)
+ Name (_DDN, "Serial IO I2C Controller 2")
+
Name (SSCN, Package () { 432, 507, 30 })
Name (FMCN, Package () { 72, 160, 30 })
-
- /* BAR0 is assigned during PCI enumeration and saved into NVS */
- Name (RBUF, ResourceTemplate ()
- {
- Memory32Fixed (ReadWrite, 0x00000000, 0x00000000, BAR0)
- Interrupt (ResourceConsumer, Level, ActiveLow, Shared, , , )
- { LPSS_I2C2_IRQ }
- })
-
- Method (_CRS, 0, NotSerialized)
- {
- /* Update BAR0 address and length if set in NVS */
- If (LNotEqual (\S2B0, Zero)) {
- CreateDwordField (^RBUF, ^BAR0._BAS, B0AD)
- CreateDwordField (^RBUF, ^BAR0._LEN, B0LN)
- Store (\S2B0, B0AD)
- Store (SIO_BAR_LEN, B0LN)
- }
-
- Return (RBUF)
- }
-
- Method (_STA, 0, NotSerialized)
- {
- If (LEqual (\S2EN, 0)) {
- Return (0x0)
- } Else {
- Return (0xF)
- }
- }
-
- Method (_PS0, 0, Serialized)
- {
- ^^LPD0 (\S2B1, \S2EN)
- }
-
- Method (_PS3, 0, Serialized)
- {
- ^^LPD3 (\S2B1, \S2EN)
- }
}
Device (I2C3)
{
- /* Serial IO I2C3 Controller */
- Name (_HID,"INT3445")
- Name (_UID, 1)
Name (_ADR, 0x00150003)
+ Name (_DDN, "Serial IO I2C Controller 3")
+
Name (SSCN, Package () { 432, 507, 30 })
Name (FMCN, Package () { 72, 160, 30 })
-
- /* BAR0 is assigned during PCI enumeration and saved into NVS */
- Name (RBUF, ResourceTemplate ()
- {
- Memory32Fixed (ReadWrite, 0x00000000, 0x00000000, BAR0)
- Interrupt (ResourceConsumer, Level, ActiveLow, Shared, , , )
- { LPSS_I2C3_IRQ }
- })
-
- Method (_CRS, 0, NotSerialized)
- {
- /* Update BAR0 address and length if set in NVS */
- If (LNotEqual (\S3B0, Zero)) {
- CreateDwordField (^RBUF, ^BAR0._BAS, B0AD)
- CreateDwordField (^RBUF, ^BAR0._LEN, B0LN)
- Store (\S3B0, B0AD)
- Store (SIO_BAR_LEN, B0LN)
- }
-
- Return (RBUF)
- }
-
- Method (_STA, 0, NotSerialized)
- {
- If (LEqual (\S3EN, 0)) {
- Return (0x0)
- } Else {
- Return (0xF)
- }
- }
-
- Method (_PS0, 0, Serialized)
- {
- ^^LPD0 (\S3B1, \S3EN)
- }
-
- Method (_PS3, 0, Serialized)
- {
- ^^LPD3 (\S3B1, \S3EN)
- }
-
}
Device (I2C4)
{
- /* Serial IO I2C4 Controller */
- Name (_HID,"INT3446")
- Name (_UID, 1)
Name (_ADR, 0x00190002)
+ Name (_DDN, "Serial IO I2C Controller 4")
+
Name (SSCN, Package () { 432, 507, 30 })
Name (FMCN, Package () { 72, 160, 30 })
-
- /* BAR0 is assigned during PCI enumeration and saved into NVS */
- Name (RBUF, ResourceTemplate ()
- {
- Memory32Fixed (ReadWrite, 0x00000000, 0x00000000, BAR0)
- Interrupt (ResourceConsumer, Level, ActiveLow, Shared, , , )
- { LPSS_I2C4_IRQ }
- })
-
- Method (_CRS, 0, NotSerialized)
- {
- /* Update BAR0 address and length if set in NVS*/
- If (LNotEqual (\S4B0, Zero)) {
- CreateDwordField (^RBUF, ^BAR0._BAS, B0AD)
- CreateDwordField (^RBUF, ^BAR0._LEN, B0LN)
- Store (\S4B0, B0AD)
- Store (SIO_BAR_LEN, B0LN)
- }
-
- Return (RBUF)
- }
-
- Method (_STA, 0, NotSerialized)
- {
- If (LEqual (\S4EN, 0)) {
- Return (0x0)
- } Else {
- Return (0xF)
- }
- }
-
- Method (_PS0, 0, Serialized)
- {
- ^^LPD0 (\S4B1, \S4EN)
- }
-
- Method (_PS3, 0, Serialized)
- {
- ^^LPD3 (\S4B1, \S4EN)
- }
}
Device (I2C5)
{
- /* Serial IO I2C1 Controller */
- Name (_HID,"INT3447")
- Name (_UID, 1)
Name (_ADR, 0x00190002)
+ Name (_DDN, "Serial IO I2C Controller 5")
+
Name (SSCN, Package () { 432, 507, 30 })
Name (FMCN, Package () { 72, 160, 30 })
-
- /* BAR0 is assigned during PCI enumeration and saved into NVS */
- Name (RBUF, ResourceTemplate ()
- {
- Memory32Fixed (ReadWrite, 0x00000000, 0x00000000, BAR0)
- Interrupt (ResourceConsumer, Level, ActiveLow, Shared, , , )
- { LPSS_I2C5_IRQ }
- })
-
- Method (_CRS, 0, NotSerialized)
- {
- /* Update BAR0 address and length if set in NVS */
- CreateDwordField (^RBUF, ^BAR0._BAS, B0AD)
- CreateDwordField (^RBUF, ^BAR0._LEN, B0LN)
- Store (0xFE02A000, B0AD)
- Store (SIO_BAR_LEN, B0LN)
-
- Return (RBUF)
- }
-
- Method (_STA, 0, NotSerialized)
- {
- If (LEqual (\S5EN, 0)) {
- Return (0x0)
- } Else {
- Return (0xF)
- }
- }
-
- Method (_PS0, 0, Serialized)
- {
- ^^LPD0 (\S5B1, \S5EN)
- }
-
- Method (_PS3, 0, Serialized)
- {
- ^^LPD3 (\S5B1, \S5EN)
- }
}
Device (SPI0)
{
- /* Serial IO PI0 Controller */
- Name (_HID,"INT3440")
- Name (_UID, 1)
Name (_ADR, 0x001E0002)
-
- /* BAR0 is assigned during PCI enumeration and saved into NVS */
- Name (RBUF, ResourceTemplate ()
- {
- Memory32Fixed (ReadWrite, 0x00000000, 0x00000000, BAR0)
- Interrupt (ResourceConsumer, Level, ActiveLow, Shared, , , )
- { LPSS_SPI0_IRQ }
- })
-
- Method (_CRS, 0, NotSerialized)
- {
- /* Update BAR0 address and length if set in NVS */
- If (LNotEqual (\S6B0, Zero)) {
- CreateDwordField (^RBUF, ^BAR0._BAS, B0AD)
- CreateDwordField (^RBUF, ^BAR0._LEN, B0LN)
- Store (\S6B0, B0AD)
- Store (SIO_BAR_LEN, B0LN)
- }
-
- Return (RBUF)
- }
-
- Method (_STA, 0, NotSerialized)
- {
- If (LEqual (\S6EN, 0)) {
- Return (0x0)
- } Else {
- Return (0xF)
- }
- }
- Method (_PS0, 0, Serialized)
- {
- ^^LPD0 (\S6B1, \S6EN)
- }
-
- Method (_PS3, 0, Serialized)
- {
- ^^LPD3 (\S6B1, \S6EN)
- }
+ Name (_DDN, "Serial IO SPI Controller 0")
}
Device (SPI1)
{
- /* Serial IO SPI1 Controller */
- Name (_HID,"INT3441")
- Name (_UID, 1)
Name (_ADR, 0x001E0003)
-
- /* BAR0 is assigned during PCI enumeration and saved into NVS */
- Name (RBUF, ResourceTemplate ()
- {
- Memory32Fixed (ReadWrite, 0x00000000, 0x00000000, BAR0)
- Interrupt (ResourceConsumer, Level, ActiveLow, Shared, , , )
- { LPSS_SPI1_IRQ }
- })
-
- Method (_CRS, 0, NotSerialized)
- {
- /* Update BAR0 address and length if set in NVS */
- If (LNotEqual (\S7B0, Zero)) {
- CreateDwordField (^RBUF, ^BAR0._BAS, B0AD)
- CreateDwordField (^RBUF, ^BAR0._LEN, B0LN)
- Store (\S7B0, B0AD)
- Store (SIO_BAR_LEN, B0LN)
- }
-
- Return (RBUF)
- }
- Method (_STA, 0, NotSerialized)
- {
- If (LEqual (\S7EN, 0)) {
- Return (0x0)
- } Else {
- Return (0xF)
- }
- }
-
- Method (_PS0, 0, Serialized)
- {
- ^^LPD0 (\S7B1, \S7EN)
- }
-
- Method (_PS3, 0, Serialized)
- {
- ^^LPD3 (\S7B1, \S7EN)
- }
+ Name (_DDN, "Serial IO SPI Controller 1")
}
Device (UAR0)
{
- /* Serial IO UART0 Controller */
- Name (_HID,"INT3448")
- Name (_UID, 1)
Name (_ADR, 0x001E0000)
-
- /* BAR0 is assigned during PCI enumeration and saved into NVS */
- Name (RBUF, ResourceTemplate ()
- {
- Memory32Fixed (ReadWrite, 0x00000000, 0x00000000, BAR0)
- Interrupt (ResourceConsumer, Level, ActiveLow, Shared, , , )
- { LPSS_UART0_IRQ }
- })
-
- Method (_CRS, 0, NotSerialized)
- {
- /* Update BAR0 address and length if set in NVS */
- If (LNotEqual (\S8B0, Zero)) {
- CreateDwordField (^RBUF, ^BAR0._BAS, B0AD)
- CreateDwordField (^RBUF, ^BAR0._LEN, B0LN)
- Store (\S8B0, B0AD)
- Store (SIO_BAR_LEN, B0LN)
- }
-
- Return (RBUF)
- }
-
- Method (_STA, 0, NotSerialized)
- {
- If (LEqual (\S8EN, 0)) {
- Return (0x0)
- } Else {
- Return (0xF)
- }
- }
-
- Method (_PS0, 0, Serialized)
- {
- ^^LPD0 (\S8B1, \S8EN)
- }
-
- Method (_PS3, 0, Serialized)
- {
- ^^LPD3 (\S8B1, \S8EN)
- }
+ Name (_DDN, "Serial IO UART Controller 0")
}
Device (UAR1)
{
- /* Serial IO UART1 Controller */
- Name (_HID,"INT3449")
- Name (_UID, 1)
Name (_ADR, 0x001E0001)
-
- /* BAR0 is assigned during PCI enumeration and saved into NVS */
- Name (RBUF, ResourceTemplate ()
- {
- Memory32Fixed (ReadWrite, 0x00000000, 0x00000000, BAR0)
- Interrupt (ResourceConsumer, Level, ActiveLow, Shared, , , )
- { LPSS_UART1_IRQ }
- })
-
- Method (_CRS, 0, NotSerialized)
- {
- // Update BAR0 address and length if set in NVS
- If (LNotEqual (\S9B0, Zero)) {
- CreateDwordField (^RBUF, ^BAR0._BAS, B0AD)
- CreateDwordField (^RBUF, ^BAR0._LEN, B0LN)
- Store (\S9B0, B0AD)
- Store (SIO_BAR_LEN, B0LN)
- }
-
- Return (RBUF)
- }
-
- Method (_STA, 0, NotSerialized)
- {
- If (LEqual (\S9EN, 0)) {
- Return (0x0)
- } Else {
- Return (0xF)
- }
- }
-
- Method (_PS0, 0, Serialized)
- {
- ^^LPD0 (\S9B1, \S9EN)
- }
-
- Method (_PS3, 0, Serialized)
- {
- ^^LPD3 (\S9B1, \S9EN)
- }
+ Name (_DDN, "Serial IO UART Controller 1")
}
Device (UAR2)
{
- /* Serial IO UART1 Controller */
- Name (_HID,"INT344A")
- Name (_UID, 1)
Name (_ADR, 0x00190000)
-
- /* BAR0 is assigned during PCI enumeration and saved into NVS */
- Name (RBUF, ResourceTemplate ()
- {
- Memory32Fixed (ReadWrite, 0x00000000, 0x00000000, BAR0)
- Interrupt (ResourceConsumer, Level, ActiveLow, Shared, , , )
- { LPSS_UART2_IRQ }
- })
-
- Method (_CRS, 0, NotSerialized)
- {
- /* Update BAR0 address and length if set in NVS */
- If (LNotEqual (\SAB0, Zero)) {
- CreateDwordField (^RBUF, ^BAR0._BAS, B0AD)
- CreateDwordField (^RBUF, ^BAR0._LEN, B0LN)
- Store (\SAB0, B0AD)
- Store (SIO_BAR_LEN, B0LN)
- }
-
- Return (RBUF)
- }
-
- Method (_STA, 0, NotSerialized)
- {
- If (LEqual (\SAEN, 0)) {
- Return (0x0)
- } Else {
- Return (0xF)
- }
- }
-
- Method (_PS0, 0, Serialized)
- {
- ^^LPD0 (\SAB1, \SAEN)
- }
-
- Method (_PS3, 0, Serialized)
- {
- ^^LPD3 (\SAB1, \SAEN)
- }
+ Name (_DDN, "Serial IO UART Controller 2")
}
diff --git a/src/soc/intel/skylake/include/soc/nvs.h b/src/soc/intel/skylake/include/soc/nvs.h
index 2d8129b..c9fcb4e 100644
--- a/src/soc/intel/skylake/include/soc/nvs.h
+++ b/src/soc/intel/skylake/include/soc/nvs.h
@@ -24,7 +24,6 @@
#include <rules.h>
#include <vendorcode/google/chromeos/gnvs.h>
-#include <soc/device_nvs.h>
typedef struct {
/* Miscellaneous */
@@ -61,12 +60,10 @@ typedef struct {
/* ChromeOS specific (0x100 - 0xfff) */
chromeos_acpi_t chromeos;
-
- /* Device specific (0x1000) */
- device_nvs_t dev;
} __attribute__((packed)) global_nvs_t;
void acpi_create_gnvs(global_nvs_t *gnvs);
+
#if ENV_SMM
/* Used in SMM to find the ACPI GNVS address */
global_nvs_t *smm_get_gnvs(void);
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