[coreboot-gerrit] New patch to review for coreboot: skylake: Apply USB2 and USB3 port enable/disable settings

[Patrick Georgi (pgeorgi@google.com)]

Patrick Georgi (pgeorgi at google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11547

-gerrit

commit 7a5a9e8da19b2e3f624dfe641355aadf51e12d1b
Author: Duncan Laurie <dlaurie at chromium.org>
Date:   Fri Aug 28 17:21:07 2015 -0700

    skylake: Apply USB2 and USB3 port enable/disable settings
    
    The USB port enable/disable settings were never getting applied to
    the UPD configuration and so were not getting used by FSP.
    
    BUG=chrome-os-partner:44662
    BRANCH=none
    TEST=build and boot on glados
    
    Change-Id: I13d4eb901215308de4b59083339832d29ce0049f
    Signed-off-by: Patrick Georgi <pgeorgi at chromium.org>
    Original-Commit-Id: 4fd83caa8087cc349fa933eafac98c2563f501a4
    Original-Change-Id: Ia5fa051782eeb837756a14aecb4aa626d25b2bdb
    Original-Signed-off-by: Duncan Laurie <dlaurie at chromium.org>
    Original-Reviewed-on: https://chromium-review.googlesource.com/296034
    Original-Commit-Ready: Aaron Durbin <adurbin at chromium.org>
    Original-Reviewed-by: Aaron Durbin <adurbin at chromium.org>
---
 src/soc/intel/skylake/chip.c | 20 +++++++++-----------
 1 file changed, 9 insertions(+), 11 deletions(-)

diff --git a/src/soc/intel/skylake/chip.c b/src/soc/intel/skylake/chip.c
index 8bd62b4..2c49883 100644
--- a/src/soc/intel/skylake/chip.c
+++ b/src/soc/intel/skylake/chip.c
@@ -26,6 +26,7 @@
 #include <fsp_util.h>
 #include <soc/pci_devs.h>
 #include <soc/ramstage.h>
+#include <string.h>
 
 static void pci_domain_set_resources(device_t dev)
 {
@@ -69,18 +70,15 @@ struct chip_operations soc_intel_skylake_ops = {
 /* UPD parameters to be initialized before SiliconInit */
 void soc_silicon_init_params(SILICON_INIT_UPD *params)
 {
-	const struct device *dev;
-	const struct soc_intel_skylake_config *config;
-	int i;
+	const struct device *dev = dev_find_slot(0, PCH_DEVFN_LPC);
+	const struct soc_intel_skylake_config *config = dev->chip_info;
 
-	/* Set the parameters for SiliconInit */
-	dev = dev_find_slot(0, PCI_DEVFN(PCH_DEV_SLOT_LPC, 0));
-	if (!dev || !dev->chip_info)
-		return;
-	config = dev->chip_info;
-
-	for (i = 0; i < PchSerialIoIndexMax; i++)
-		params->SerialIoDevMode[i] = config->SerialIoDevMode[i];
+	memcpy(params->SerialIoDevMode, config->SerialIoDevMode,
+	       sizeof(params->SerialIoDevMode));
+	memcpy(params->PortUsb20Enable, config->PortUsb20Enable,
+	       sizeof(params->PortUsb20Enable));
+	memcpy(params->PortUsb30Enable, config->PortUsb30Enable,
+	       sizeof(params->PortUsb30Enable));
 
 	params->SataSalpSupport = config->SataSalpSupport;
 	params->SataPortsEnable[0] = config->SataPortsEnable[0];