[coreboot-gerrit] New patch to review for coreboot: skylake: Clean up chip.h

[Patrick Georgi (pgeorgi@google.com)]

Patrick Georgi (pgeorgi at google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11563

-gerrit

commit c0cf178cc2f33a952cdb6dd1ef0b2c726a81045a
Author: Duncan Laurie <dlaurie at chromium.org>
Date:   Thu Sep 3 16:05:59 2015 -0700

    skylake: Clean up chip.h
    
    Remove config options that do not apply and are unused on skylake.
    
    BUG=chrome-os-partner:40635
    BRANCH=none
    TEST=emerge-glados coreboot
    
    Change-Id: Ic410f8e6b8ecc06d6f4fb1f229017df18c6045f3
    Signed-off-by: Patrick Georgi <pgeorgi at chromium.org>
    Original-Commit-Id: 3224b89e310909c2836ef2c669c6b2ee826b1b28
    Original-Change-Id: I2b4fe85f78480eac5635e78ce4e848f73967bd27
    Original-Signed-off-by: Duncan Laurie <dlaurie at chromium.org>
    Original-Reviewed-on: https://chromium-review.googlesource.com/297740
    Original-Reviewed-by: Aaron Durbin <adurbin at chromium.org>
---
 src/soc/intel/skylake/chip.h | 33 +++++++--------------------------
 1 file changed, 7 insertions(+), 26 deletions(-)

diff --git a/src/soc/intel/skylake/chip.h b/src/soc/intel/skylake/chip.h
index e962b37..9b43b7f 100644
--- a/src/soc/intel/skylake/chip.h
+++ b/src/soc/intel/skylake/chip.h
@@ -60,23 +60,6 @@ struct soc_intel_skylake_config {
 	uint32_t gen3_dec;
 	uint32_t gen4_dec;
 
-	/* Enable linear PCIe Root Port function numbers starting at zero */
-	uint8_t pcie_port_coalesce;
-
-	/* Force root port ASPM configuration with port bitmap */
-	uint8_t pcie_port_force_aspm;
-
-	/* Enable ADSP power gating features */
-	uint8_t adsp_d3_pg_enable;
-	uint8_t adsp_sram_pg_enable;
-
-	/*
-	 * Clock Disable Map:
-	 * [21:16] = CLKOUT_PCIE# 5-0
-	 *    [24] = CLKOUT_ITPXDP
-	 */
-	uint32_t icc_clock_disable;
-
 	/*
 	 * Digital Port Hotplug Enable:
 	 *  0x04 = Enabled, 2ms short pulse
@@ -100,15 +83,6 @@ struct soc_intel_skylake_config {
 	u32 gpu_cpu_backlight;
 	u32 gpu_pch_backlight;
 
-	/*
-	 * Graphics CD Clock Frequency
-	 * 0 = 337.5MHz
-	 * 1 = 450MHz
-	 * 2 = 540MHz
-	 * 3 = 675MHz
-	 */
-	int cdclk;
-
 	/* Enable S0iX support */
 	int s0ix_enable;
 
@@ -167,6 +141,13 @@ struct soc_intel_skylake_config {
 	/* Audio related */
 	u8 EnableAzalia;
 	u8 DspEnable;
+
+	/*
+	 * I/O Buffer Ownership:
+	 * 0: HD-A Link
+	 * 1 Shared, HD-A Link and I2S Port
+	 * 3: I2S Ports
+	 */
 	u8 IoBufferOwnership;
 
 	/* Trace Hub function */