[coreboot-gerrit] New patch to review for coreboot: rk3288: Allow board-specific APLL (CPU clock) settings
Patrick Georgi (pgeorgi@google.com)
gerrit at coreboot.org
Mon Sep 7 18:43:33 CET 2015
Patrick Georgi (pgeorgi at google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11582
-gerrit
commit 04e96cb3a282e5d7e013fa4deb6cc8f384dbed46
Author: David Hendricks <dhendrix at chromium.org>
Date: Wed Sep 2 18:10:14 2015 -0700
rk3288: Allow board-specific APLL (CPU clock) settings
This changes the API to rkclk_configure_cpu() such that we can pass
in the desired APLL frequency in each veyron board's bootblock.c.
Devices with a constrainted form facter (rialto and possibly mickey)
will use this to run firmware at a slower speed to mitigate risk
of thermal issues (due to the RK808, not the RK3288).
BUG=chrome-os-partner:42054
BRANCH=none
TEST=amstan says rialto is noticably cooler (and slower)
Change-Id: I28b332e1d484bd009599944cd9f5cf633ea468dd
Signed-off-by: Patrick Georgi <pgeorgi at chromium.org>
Original-Commit-Id: d10af5e18b4131a00f202272e405bd22eab4caeb
Original-Change-Id: I960cb6ff512c058e72032aa2cbadedde97510631
Original-Signed-off-by: David Hendricks <dhendrix at chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/297190
Original-Reviewed-by: Julius Werner <jwerner at chromium.org>
---
src/mainboard/google/veyron/bootblock.c | 2 +-
src/mainboard/google/veyron_brain/bootblock.c | 2 +-
src/mainboard/google/veyron_danger/bootblock.c | 2 +-
src/mainboard/google/veyron_mickey/bootblock.c | 2 +-
src/mainboard/google/veyron_rialto/bootblock.c | 2 +-
src/mainboard/google/veyron_romy/bootblock.c | 2 +-
src/soc/rockchip/rk3288/clock.c | 13 ++++++++++---
src/soc/rockchip/rk3288/include/soc/clock.h | 8 ++++++--
8 files changed, 22 insertions(+), 11 deletions(-)
diff --git a/src/mainboard/google/veyron/bootblock.c b/src/mainboard/google/veyron/bootblock.c
index ae74972..e4126a4 100644
--- a/src/mainboard/google/veyron/bootblock.c
+++ b/src/mainboard/google/veyron/bootblock.c
@@ -59,7 +59,7 @@ void bootblock_mainboard_init(void)
udelay(175);/* Must wait for voltage to stabilize,2mV/us */
rk808_configure_buck(1, 1400);
udelay(100);/* Must wait for voltage to stabilize,2mV/us */
- rkclk_configure_cpu();
+ rkclk_configure_cpu(APLL_1800_MHZ);
/* i2c1 for tpm */
write32(&rk3288_grf->iomux_i2c1, IOMUX_I2C1);
diff --git a/src/mainboard/google/veyron_brain/bootblock.c b/src/mainboard/google/veyron_brain/bootblock.c
index a4a756d..50d8ef1 100644
--- a/src/mainboard/google/veyron_brain/bootblock.c
+++ b/src/mainboard/google/veyron_brain/bootblock.c
@@ -61,7 +61,7 @@ void bootblock_mainboard_init(void)
udelay(175);/* Must wait for voltage to stabilize,2mV/us */
rk808_configure_buck(1, 1400);
udelay(100);/* Must wait for voltage to stabilize,2mV/us */
- rkclk_configure_cpu();
+ rkclk_configure_cpu(APLL_1800_MHZ);
/* i2c1 for tpm */
write32(&rk3288_grf->iomux_i2c1, IOMUX_I2C1);
diff --git a/src/mainboard/google/veyron_danger/bootblock.c b/src/mainboard/google/veyron_danger/bootblock.c
index a4a756d..50d8ef1 100644
--- a/src/mainboard/google/veyron_danger/bootblock.c
+++ b/src/mainboard/google/veyron_danger/bootblock.c
@@ -61,7 +61,7 @@ void bootblock_mainboard_init(void)
udelay(175);/* Must wait for voltage to stabilize,2mV/us */
rk808_configure_buck(1, 1400);
udelay(100);/* Must wait for voltage to stabilize,2mV/us */
- rkclk_configure_cpu();
+ rkclk_configure_cpu(APLL_1800_MHZ);
/* i2c1 for tpm */
write32(&rk3288_grf->iomux_i2c1, IOMUX_I2C1);
diff --git a/src/mainboard/google/veyron_mickey/bootblock.c b/src/mainboard/google/veyron_mickey/bootblock.c
index a4a756d..50d8ef1 100644
--- a/src/mainboard/google/veyron_mickey/bootblock.c
+++ b/src/mainboard/google/veyron_mickey/bootblock.c
@@ -61,7 +61,7 @@ void bootblock_mainboard_init(void)
udelay(175);/* Must wait for voltage to stabilize,2mV/us */
rk808_configure_buck(1, 1400);
udelay(100);/* Must wait for voltage to stabilize,2mV/us */
- rkclk_configure_cpu();
+ rkclk_configure_cpu(APLL_1800_MHZ);
/* i2c1 for tpm */
write32(&rk3288_grf->iomux_i2c1, IOMUX_I2C1);
diff --git a/src/mainboard/google/veyron_rialto/bootblock.c b/src/mainboard/google/veyron_rialto/bootblock.c
index 38ae277..a539c08 100644
--- a/src/mainboard/google/veyron_rialto/bootblock.c
+++ b/src/mainboard/google/veyron_rialto/bootblock.c
@@ -65,7 +65,7 @@ void bootblock_mainboard_init(void)
udelay(175);/* Must wait for voltage to stabilize,2mV/us */
rk808_configure_buck(1, 1400);
udelay(100);/* Must wait for voltage to stabilize,2mV/us */
- rkclk_configure_cpu();
+ rkclk_configure_cpu(APLL_1392_MHZ);
/* i2c1 for tpm */
write32(&rk3288_grf->iomux_i2c1, IOMUX_I2C1);
diff --git a/src/mainboard/google/veyron_romy/bootblock.c b/src/mainboard/google/veyron_romy/bootblock.c
index a4a756d..50d8ef1 100644
--- a/src/mainboard/google/veyron_romy/bootblock.c
+++ b/src/mainboard/google/veyron_romy/bootblock.c
@@ -61,7 +61,7 @@ void bootblock_mainboard_init(void)
udelay(175);/* Must wait for voltage to stabilize,2mV/us */
rk808_configure_buck(1, 1400);
udelay(100);/* Must wait for voltage to stabilize,2mV/us */
- rkclk_configure_cpu();
+ rkclk_configure_cpu(APLL_1800_MHZ);
/* i2c1 for tpm */
write32(&rk3288_grf->iomux_i2c1, IOMUX_I2C1);
diff --git a/src/soc/rockchip/rk3288/clock.c b/src/soc/rockchip/rk3288/clock.c
index e4d2e3e..31901e7 100644
--- a/src/soc/rockchip/rk3288/clock.c
+++ b/src/soc/rockchip/rk3288/clock.c
@@ -73,10 +73,17 @@ static struct rk3288_cru_reg * const cru_ptr = (void *)CRU_BASE;
"divisors on line " STRINGIFY(__LINE__));
/* Keep divisors as low as possible to reduce jitter and power usage. */
-static const struct pll_div apll_init_cfg = PLL_DIVISORS(APLL_HZ, 1, 1);
static const struct pll_div gpll_init_cfg = PLL_DIVISORS(GPLL_HZ, 2, 2);
static const struct pll_div cpll_init_cfg = PLL_DIVISORS(CPLL_HZ, 1, 2);
+/* See linux/drivers/clk/rockchip/clk-rk3288.c for more APLL combinations */
+static const struct pll_div apll_1800_cfg = PLL_DIVISORS(1800*MHz, 1, 1);
+static const struct pll_div apll_1392_cfg = PLL_DIVISORS(1392*MHz, 1, 1);
+static const struct pll_div *apll_cfgs[] = {
+ [APLL_1800_MHZ] = &apll_1800_cfg,
+ [APLL_1392_MHZ] = &apll_1392_cfg,
+};
+
/*******************PLL CON0 BITS***************************/
#define PLL_OD_MSK (0x0F)
@@ -314,13 +321,13 @@ void rkclk_init(void)
}
-void rkclk_configure_cpu(void)
+void rkclk_configure_cpu(enum apll_frequencies apll_freq)
{
/* pll enter slow-mode */
write32(&cru_ptr->cru_mode_con,
RK_CLRSETBITS(APLL_MODE_MSK, APLL_MODE_SLOW));
- rkclk_set_pll(&cru_ptr->cru_apll_con[0], &apll_init_cfg);
+ rkclk_set_pll(&cru_ptr->cru_apll_con[0], apll_cfgs[apll_freq]);
/* waiting for pll lock */
while (1) {
diff --git a/src/soc/rockchip/rk3288/include/soc/clock.h b/src/soc/rockchip/rk3288/include/soc/clock.h
index 08d9d45..3fccecb 100644
--- a/src/soc/rockchip/rk3288/include/soc/clock.h
+++ b/src/soc/rockchip/rk3288/include/soc/clock.h
@@ -24,11 +24,15 @@
#define OSC_HZ (24*MHz)
-#define APLL_HZ (1800*MHz)
#define GPLL_HZ (594*MHz)
#define CPLL_HZ (384*MHz)
#define NPLL_HZ (384*MHz)
+enum apll_frequencies {
+ APLL_1800_MHZ,
+ APLL_1392_MHZ,
+};
+
/* The SRAM is clocked off aclk_bus, so we want to max it out for boot speed. */
#define PD_BUS_ACLK_HZ (297000*KHz)
#define PD_BUS_HCLK_HZ (148500*KHz)
@@ -44,7 +48,7 @@ void rkclk_ddr_reset(u32 ch, u32 ctl, u32 phy);
void rkclk_ddr_phy_ctl_reset(u32 ch, u32 n);
void rkclk_configure_ddr(unsigned int hz);
void rkclk_configure_i2s(unsigned int hz);
-void rkclk_configure_cpu(void);
+void rkclk_configure_cpu(enum apll_frequencies apll_freq);
void rkclk_configure_crypto(unsigned int hz);
void rkclk_configure_tsadc(unsigned int hz);
void rkclk_configure_vop_aclk(u32 vop_id, u32 aclk_hz);
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