[coreboot-gerrit] New patch to review for coreboot: Skylake: update C state latency and power numbers

[Patrick Georgi (pgeorgi@google.com)]

Patrick Georgi (pgeorgi at google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11659

-gerrit

commit 38dcdb1a2b26967e44735c187c6b471e87a06c16
Author: robbie zhang <robbie.zhang at intel.com>
Date:   Fri Sep 11 14:25:15 2015 -0700

    Skylake: update C state latency and power numbers
    
    The values are taken from latest BWG as well fsp src.
    
    BRANCH=none
    BUG=chrome-os-partner:45208
    TEST=Built and boot on kunimitsu
    Signed-off-by: Robbie Zhang <robbie.zhang at intel.com>
    
    Change-Id: Ia6bd336a71b0313801b59990c78822fa0d789e36
    Signed-off-by: Patrick Georgi <pgeorgi at chromium.org>
    Original-Commit-Id: c955ab43245153d76932daa527f1b5ebea859164
    Original-Change-Id: I3f7307951753c2bbe6319f627a82a93359c4e61b
    Original-Reviewed-on: https://chromium-review.googlesource.com/299480
    Original-Commit-Ready: Wenkai Du <wenkai.du at intel.com>
    Original-Tested-by: Wenkai Du <wenkai.du at intel.com>
    Original-Reviewed-by: Aaron Durbin <adurbin at chromium.org>
---
 src/soc/intel/skylake/acpi.c            | 24 ++++++++++++------------
 src/soc/intel/skylake/include/soc/cpu.h | 21 +++++++++++++++------
 2 files changed, 27 insertions(+), 18 deletions(-)

diff --git a/src/soc/intel/skylake/acpi.c b/src/soc/intel/skylake/acpi.c
index f2ab534..471fd17 100644
--- a/src/soc/intel/skylake/acpi.c
+++ b/src/soc/intel/skylake/acpi.c
@@ -78,62 +78,62 @@ static acpi_cstate_t cstate_map[NUM_C_STATES] = {
 	[C_STATE_C0] = { },
 	[C_STATE_C1] = {
 		.latency = 0,
-		.power = 1000,
+		.power = C1_POWER,
 		.resource = MWAIT_RES(0, 0),
 	},
 	[C_STATE_C1E] = {
 		.latency = 0,
-		.power = 1000,
+		.power = C1_POWER,
 		.resource = MWAIT_RES(0, 1),
 	},
 	[C_STATE_C3] = {
 		.latency = C_STATE_LATENCY_FROM_LAT_REG(0),
-		.power = 500,
+		.power = C3_POWER,
 		.resource = MWAIT_RES(1, 0),
 	},
 	[C_STATE_C6_SHORT_LAT] = {
 		.latency = C_STATE_LATENCY_FROM_LAT_REG(1),
-		.power = 350,
+		.power = C6_POWER,
 		.resource = MWAIT_RES(2, 0),
 	},
 	[C_STATE_C6_LONG_LAT] = {
 		.latency = C_STATE_LATENCY_FROM_LAT_REG(2),
-		.power = 350,
+		.power = C6_POWER,
 		.resource = MWAIT_RES(2, 1),
 	},
 	[C_STATE_C7_SHORT_LAT] = {
 		.latency = C_STATE_LATENCY_FROM_LAT_REG(1),
-		.power = 200,
+		.power = C7_POWER,
 		.resource = MWAIT_RES(3, 0),
 	},
 	[C_STATE_C7_LONG_LAT] = {
 		.latency = C_STATE_LATENCY_FROM_LAT_REG(2),
-		.power = 200,
+		.power = C7_POWER,
 		.resource = MWAIT_RES(3, 1),
 	},
 	[C_STATE_C7S_SHORT_LAT] = {
 		.latency = C_STATE_LATENCY_FROM_LAT_REG(1),
-		.power = 200,
+		.power = C7_POWER,
 		.resource = MWAIT_RES(3, 2),
 	},
 	[C_STATE_C7S_LONG_LAT] = {
 		.latency = C_STATE_LATENCY_FROM_LAT_REG(2),
-		.power = 200,
+		.power = C7_POWER,
 		.resource = MWAIT_RES(3, 3),
 	},
 	[C_STATE_C8] = {
 		.latency = C_STATE_LATENCY_FROM_LAT_REG(3),
-		.power = 200,
+		.power = C8_POWER,
 		.resource = MWAIT_RES(4, 0),
 	},
 	[C_STATE_C9] = {
 		.latency = C_STATE_LATENCY_FROM_LAT_REG(4),
-		.power = 200,
+		.power = C9_POWER,
 		.resource = MWAIT_RES(5, 0),
 	},
 	[C_STATE_C10] = {
 		.latency = C_STATE_LATENCY_FROM_LAT_REG(5),
-		.power = 200,
+		.power = C10_POWER,
 		.resource = MWAIT_RES(6, 0),
 	},
 };
diff --git a/src/soc/intel/skylake/include/soc/cpu.h b/src/soc/intel/skylake/include/soc/cpu.h
index c62b308..8d5c2a0 100644
--- a/src/soc/intel/skylake/include/soc/cpu.h
+++ b/src/soc/intel/skylake/include/soc/cpu.h
@@ -35,12 +35,21 @@
 #define CPU_BCLK		100
 
 /* Latency times in units of 1024ns. */
-#define C_STATE_LATENCY_CONTROL_0_LIMIT 0x42
-#define C_STATE_LATENCY_CONTROL_1_LIMIT 0x73
-#define C_STATE_LATENCY_CONTROL_2_LIMIT 0x91
-#define C_STATE_LATENCY_CONTROL_3_LIMIT 0xe4
-#define C_STATE_LATENCY_CONTROL_4_LIMIT 0x145
-#define C_STATE_LATENCY_CONTROL_5_LIMIT 0x1ef
+#define C_STATE_LATENCY_CONTROL_0_LIMIT	0x4e
+#define C_STATE_LATENCY_CONTROL_1_LIMIT	0x76
+#define C_STATE_LATENCY_CONTROL_2_LIMIT	0x94
+#define C_STATE_LATENCY_CONTROL_3_LIMIT	0xfa
+#define C_STATE_LATENCY_CONTROL_4_LIMIT	0x14c
+#define C_STATE_LATENCY_CONTROL_5_LIMIT	0x3f2
+
+/* Power in units of mW */
+#define C1_POWER	0x3e8
+#define C3_POWER	0x1f4
+#define C6_POWER	0x15e
+#define C7_POWER	0xc8
+#define C8_POWER	0xc8
+#define C9_POWER	0xc8
+#define C10_POWER	0xc8
 
 #define C_STATE_LATENCY_MICRO_SECONDS(limit, base) \
 	(((1 << ((base)*5)) * (limit)) / 1000)