[coreboot-gerrit] Patch set updated for coreboot: southbridge/intel/bd82x6x: add option to not enable gpu audio codec

[Nicolas Reinecke (nr@das-labor.org)]

Nicolas Reinecke (nr at das-labor.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8303

-gerrit

commit 5e96c39a62a1da8ea38eaad296944d0378962158
Author: Nicolas Reinecke <nr at das-labor.org>
Date:   Sat Jul 4 22:44:19 2015 +0200

    southbridge/intel/bd82x6x: add option to not enable gpu audio codec
    
    Some Thinkpads like T420s or T520 with discrete GPU have only VGA
    and LVDS conntected to the IGP. For this devices is it usefull to
    have an option to not enable audio codec. The audio dev shows up in
    linux as hdmi codec but is complete useless.
    
    Change-Id: Iaa60b6d4c3c98ec9616ea0ef43913bbcf0d315da
    Signed-off-by: Nicolas Reinecke <nr at das-labor.org>
---
 src/mainboard/lenovo/t420s/devicetree.cb |  3 +++
 src/mainboard/lenovo/t520/devicetree.cb  |  3 +++
 src/southbridge/intel/bd82x6x/azalia.c   | 17 ++++++++++-------
 src/southbridge/intel/bd82x6x/chip.h     |  2 ++
 4 files changed, 18 insertions(+), 7 deletions(-)

diff --git a/src/mainboard/lenovo/t420s/devicetree.cb b/src/mainboard/lenovo/t420s/devicetree.cb
index cd70228..0da501f 100644
--- a/src/mainboard/lenovo/t420s/devicetree.cb
+++ b/src/mainboard/lenovo/t420s/devicetree.cb
@@ -60,6 +60,9 @@ chip northbridge/intel/sandybridge
 			# Set max SATA speed to 6.0 Gb/s
 			register "sata_interface_speed_support" = "0x3"
 
+			# not enable audio codec on digital video outups. (for discrete gpu models)
+			register "azalia_video_codec_skip_enable" = "1"
+
 			register "gen1_dec" = "0x7c1601"
 			register "gen2_dec" = "0x0c15e1"
 			register "gen4_dec" = "0x0c06a1"
diff --git a/src/mainboard/lenovo/t520/devicetree.cb b/src/mainboard/lenovo/t520/devicetree.cb
index ff9745e..3d22e39 100644
--- a/src/mainboard/lenovo/t520/devicetree.cb
+++ b/src/mainboard/lenovo/t520/devicetree.cb
@@ -57,6 +57,9 @@ chip northbridge/intel/sandybridge
 			# Set max SATA speed to 6.0 Gb/s
 			register "sata_interface_speed_support" = "0x3"
 
+			# not enable audio codec on digital video outups. (for discrete gpu models)
+			register "azalia_video_codec_skip_enable" = "1"
+
 			register "gen1_dec" = "0x7c1601"
 			register "gen2_dec" = "0x0c15e1"
 			register "gen4_dec" = "0x0c06a1"
diff --git a/src/southbridge/intel/bd82x6x/azalia.c b/src/southbridge/intel/bd82x6x/azalia.c
index 2dd8836..cb4a913 100644
--- a/src/southbridge/intel/bd82x6x/azalia.c
+++ b/src/southbridge/intel/bd82x6x/azalia.c
@@ -229,6 +229,7 @@ static void codecs_init(struct device *dev, u8 *base, u32 codec_mask)
 
 static void azalia_init(struct device *dev)
 {
+	struct southbridge_intel_bd82x6x_config *config = dev->chip_info;
 	u8 *base;
 	struct resource *res;
 	u32 codec_mask;
@@ -268,14 +269,16 @@ static void azalia_init(struct device *dev)
 	reg32 |= (1 << 31);
 	pci_write_config32(dev, 0x120, reg32);
 
-	// Enable HDMI codec:
-	reg32 = pci_read_config32(dev, 0xc4);
-	reg32 |= (1 << 1);
-	pci_write_config32(dev, 0xc4, reg32);
+	if (!(config->azalia_video_codec_skip_enable)) {
+		// Enable HDMI codec:
+		reg32 = pci_read_config32(dev, 0xc4);
+		reg32 |= (1 << 1);
+		pci_write_config32(dev, 0xc4, reg32);
 
-	reg8 = pci_read_config8(dev, 0x43);
-	reg8 |= (1 << 6);
-	pci_write_config8(dev, 0x43, reg8);
+		reg8 = pci_read_config8(dev, 0x43);
+		reg8 |= (1 << 6);
+		pci_write_config8(dev, 0x43, reg8);
+	}
 
 	/* Additional programming steps */
 	reg32 = pci_read_config32(dev, 0xc4);
diff --git a/src/southbridge/intel/bd82x6x/chip.h b/src/southbridge/intel/bd82x6x/chip.h
index 3fa9192..731bbf9 100644
--- a/src/southbridge/intel/bd82x6x/chip.h
+++ b/src/southbridge/intel/bd82x6x/chip.h
@@ -96,6 +96,8 @@ struct southbridge_intel_bd82x6x_config {
 	uint32_t superspeed_capable_ports;
 	/* Overcurrent Mapping for USB 3.0 Ports */
 	uint32_t xhci_overcurrent_mapping;
+	/* do not enable audio codec on digital video outputs */
+	uint8_t azalia_video_codec_skip_enable;
 };
 
 #endif				/* SOUTHBRIDGE_INTEL_BD82X6X_CHIP_H */