[coreboot-gerrit] New patch to review for coreboot: coreboot: move TS_END_ROMSTAGE to one spot
Aaron Durbin (adurbin@chromium.org)
gerrit at coreboot.org
Thu Sep 24 01:03:01 CET 2015
Aaron Durbin (adurbin at chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11700
-gerrit
commit f3d72499988331d669ba87ceafaea45c646b994e
Author: Aaron Durbin <adurbin at chromium.org>
Date: Wed Sep 23 19:54:12 2015 -0500
coreboot: move TS_END_ROMSTAGE to one spot
While the romstage code flow is not consistent across all
mainboards/chipsets there is only one way of running ramstage
from romstage -- run_ramstage(). Move the
timestamp_add_now(TS_END_ROMSTAGE) to be within run_ramstage().
BUG=chrome-os-partner:44827
BRANCH=None
TEST=Built and booted glados. TS_END_ROMSTAGE still present in
timestamp table.
Change-Id: I4b584e274ce2107e83ca6425491fdc71a138e82c
Signed-off-by: Aaron Durbin <adurbin at chromium.org>
---
src/cpu/intel/haswell/romstage.c | 1 -
src/lib/prog_loaders.c | 2 ++
src/mainboard/advansus/a785e-i/romstage.c | 2 --
src/mainboard/amd/bimini_fam10/romstage.c | 2 --
src/mainboard/amd/mahogany_fam10/romstage.c | 2 --
src/mainboard/amd/serengeti_cheetah_fam10/romstage.c | 2 --
src/mainboard/amd/tilapia_fam10/romstage.c | 2 --
src/mainboard/apple/macbook21/romstage.c | 3 ---
src/mainboard/asus/kfsn4-dre/romstage.c | 2 --
src/mainboard/asus/m4a78-em/romstage.c | 2 --
src/mainboard/asus/m4a785-m/romstage.c | 2 --
src/mainboard/asus/m5a88-v/romstage.c | 2 --
src/mainboard/avalue/eax-785e/romstage.c | 2 --
src/mainboard/gigabyte/ma785gm/romstage.c | 2 --
src/mainboard/gigabyte/ma785gmt/romstage.c | 2 --
src/mainboard/gigabyte/ma78gm/romstage.c | 2 --
src/mainboard/google/cosmos/romstage.c | 2 --
src/mainboard/google/daisy/romstage.c | 2 --
src/mainboard/google/link/romstage.c | 2 --
src/mainboard/google/parrot/romstage.c | 1 -
src/mainboard/google/peach_pit/romstage.c | 2 --
src/mainboard/google/stout/romstage.c | 1 -
src/mainboard/google/veyron/romstage.c | 2 --
src/mainboard/google/veyron_brain/romstage.c | 2 --
src/mainboard/google/veyron_danger/romstage.c | 2 --
src/mainboard/google/veyron_mickey/romstage.c | 2 --
src/mainboard/google/veyron_rialto/romstage.c | 2 --
src/mainboard/google/veyron_romy/romstage.c | 2 --
src/mainboard/hp/dl165_g6_fam10/romstage.c | 2 --
src/mainboard/iei/kino-780am2-fam10/romstage.c | 2 --
src/mainboard/intel/cougar_canyon2/romstage.c | 2 --
src/mainboard/intel/emeraldlake2/romstage.c | 1 -
src/mainboard/jetway/pa78vm5/romstage.c | 2 --
src/mainboard/kontron/ktqm77/romstage.c | 1 -
src/mainboard/lenovo/t60/romstage.c | 2 --
src/mainboard/lenovo/x201/romstage.c | 2 --
src/mainboard/lenovo/x60/romstage.c | 3 ---
src/mainboard/msi/ms9652_fam10/romstage.c | 2 --
src/mainboard/packardbell/ms2290/romstage.c | 2 --
src/mainboard/samsung/lumpy/romstage.c | 1 -
src/mainboard/samsung/stumpy/romstage.c | 1 -
src/mainboard/supermicro/h8dmr_fam10/romstage.c | 2 --
src/mainboard/supermicro/h8qme_fam10/romstage.c | 2 --
src/mainboard/supermicro/h8scm_fam10/romstage.c | 2 --
src/mainboard/tyan/s2912_fam10/romstage.c | 2 --
src/mainboard/via/epia-m850/romstage.c | 1 -
src/northbridge/intel/sandybridge/romstage_native.c | 1 -
src/soc/intel/baytrail/romstage/romstage.c | 2 --
src/soc/intel/broadwell/romstage/romstage.c | 2 --
src/soc/intel/common/romstage.c | 2 --
src/soc/intel/fsp_baytrail/romstage/romstage.c | 2 --
src/southbridge/intel/fsp_rangeley/romstage.c | 2 --
52 files changed, 2 insertions(+), 95 deletions(-)
diff --git a/src/cpu/intel/haswell/romstage.c b/src/cpu/intel/haswell/romstage.c
index 6adb8be..9c238ca 100644
--- a/src/cpu/intel/haswell/romstage.c
+++ b/src/cpu/intel/haswell/romstage.c
@@ -274,7 +274,6 @@ void romstage_common(const struct romstage_params *params)
if (CONFIG_LPC_TPM) {
init_tpm(wake_from_s3);
}
- timestamp_add_now(TS_END_ROMSTAGE);
}
static inline void prepare_for_resume(struct romstage_handoff *handoff)
diff --git a/src/lib/prog_loaders.c b/src/lib/prog_loaders.c
index 2f4a2c1..e53fca5 100644
--- a/src/lib/prog_loaders.c
+++ b/src/lib/prog_loaders.c
@@ -96,6 +96,8 @@ void run_ramstage(void)
struct prog ramstage =
PROG_INIT(ASSET_RAMSTAGE, CONFIG_CBFS_PREFIX "/ramstage");
+ timestamp_add_now(TS_END_ROMSTAGE);
+
/* Only x86 systems currently take the same firmware path on resume. */
if (IS_ENABLED(CONFIG_ARCH_X86) && IS_ENABLED(CONFIG_EARLY_CBMEM_INIT))
run_ramstage_from_resume(romstage_handoff_find_or_add(),
diff --git a/src/mainboard/advansus/a785e-i/romstage.c b/src/mainboard/advansus/a785e-i/romstage.c
index 2987db1..dfda22e 100644
--- a/src/mainboard/advansus/a785e-i/romstage.c
+++ b/src/mainboard/advansus/a785e-i/romstage.c
@@ -226,8 +226,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
rs780_before_pci_init();
- timestamp_add_now(TS_END_ROMSTAGE);
-
post_code(0x42);
post_cache_as_ram(); // BSP switch stack to ram, copy then execute LB.
post_code(0x43); // Should never see this post code.
diff --git a/src/mainboard/amd/bimini_fam10/romstage.c b/src/mainboard/amd/bimini_fam10/romstage.c
index 372074c..9e2e904 100644
--- a/src/mainboard/amd/bimini_fam10/romstage.c
+++ b/src/mainboard/amd/bimini_fam10/romstage.c
@@ -225,8 +225,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
rs780_before_pci_init();
sb800_before_pci_init();
- timestamp_add_now(TS_END_ROMSTAGE);
-
post_code(0x42);
post_cache_as_ram(); // BSP switch stack to ram, copy then execute LB.
post_code(0x43); // Should never see this post code.
diff --git a/src/mainboard/amd/mahogany_fam10/romstage.c b/src/mainboard/amd/mahogany_fam10/romstage.c
index 2836d67..c01ccf0 100644
--- a/src/mainboard/amd/mahogany_fam10/romstage.c
+++ b/src/mainboard/amd/mahogany_fam10/romstage.c
@@ -224,8 +224,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
rs780_before_pci_init();
sb7xx_51xx_before_pci_init();
- timestamp_add_now(TS_END_ROMSTAGE);
-
post_code(0x42);
post_cache_as_ram(); // BSP switch stack to ram, copy then execute LB.
post_code(0x43); // Should never see this post code.
diff --git a/src/mainboard/amd/serengeti_cheetah_fam10/romstage.c b/src/mainboard/amd/serengeti_cheetah_fam10/romstage.c
index 631534e..3d7c168 100644
--- a/src/mainboard/amd/serengeti_cheetah_fam10/romstage.c
+++ b/src/mainboard/amd/serengeti_cheetah_fam10/romstage.c
@@ -333,8 +333,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
// die("After MCT init before CAR disabled.");
- timestamp_add_now(TS_END_ROMSTAGE);
-
post_code(0x42);
post_cache_as_ram(); // BSP switch stack to ram, copy then execute LB.
post_code(0x43); // Should never see this post code.
diff --git a/src/mainboard/amd/tilapia_fam10/romstage.c b/src/mainboard/amd/tilapia_fam10/romstage.c
index 12c9244..924345d 100644
--- a/src/mainboard/amd/tilapia_fam10/romstage.c
+++ b/src/mainboard/amd/tilapia_fam10/romstage.c
@@ -224,8 +224,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
rs780_before_pci_init();
sb7xx_51xx_before_pci_init();
- timestamp_add_now(TS_END_ROMSTAGE);
-
post_code(0x42);
post_cache_as_ram(); // BSP switch stack to ram, copy then execute LB.
post_code(0x43); // Should never see this post code.
diff --git a/src/mainboard/apple/macbook21/romstage.c b/src/mainboard/apple/macbook21/romstage.c
index 526d518..3f252ab 100644
--- a/src/mainboard/apple/macbook21/romstage.c
+++ b/src/mainboard/apple/macbook21/romstage.c
@@ -344,7 +344,4 @@ void main(unsigned long bist)
/* Initialize the internal PCIe links before we go into stage2 */
i945_late_initialization(s3resume);
-
- timestamp_add_now(TS_END_ROMSTAGE);
-
}
diff --git a/src/mainboard/asus/kfsn4-dre/romstage.c b/src/mainboard/asus/kfsn4-dre/romstage.c
index cf36a72..b35473c 100644
--- a/src/mainboard/asus/kfsn4-dre/romstage.c
+++ b/src/mainboard/asus/kfsn4-dre/romstage.c
@@ -368,8 +368,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
/* Restore default SuperIO access */
outb(0xaa, port);
- timestamp_add_now(TS_END_ROMSTAGE);
-
post_cache_as_ram(); // BSP switch stack to ram, copy then execute LB.
post_code(0x43); // Should never see this post code.
}
diff --git a/src/mainboard/asus/m4a78-em/romstage.c b/src/mainboard/asus/m4a78-em/romstage.c
index 6e3f709..bcff9e4 100644
--- a/src/mainboard/asus/m4a78-em/romstage.c
+++ b/src/mainboard/asus/m4a78-em/romstage.c
@@ -226,8 +226,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
rs780_before_pci_init();
sb7xx_51xx_before_pci_init();
- timestamp_add_now(TS_END_ROMSTAGE);
-
post_code(0x42);
post_cache_as_ram(); // BSP switch stack to ram, copy then execute LB.
post_code(0x43); // Should never see this post code.
diff --git a/src/mainboard/asus/m4a785-m/romstage.c b/src/mainboard/asus/m4a785-m/romstage.c
index c3bb1ca..e49c9b9 100644
--- a/src/mainboard/asus/m4a785-m/romstage.c
+++ b/src/mainboard/asus/m4a785-m/romstage.c
@@ -226,8 +226,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
rs780_before_pci_init();
sb7xx_51xx_before_pci_init();
- timestamp_add_now(TS_END_ROMSTAGE);
-
post_code(0x42);
post_cache_as_ram(); // BSP switch stack to ram, copy then execute LB.
post_code(0x43); // Should never see this post code.
diff --git a/src/mainboard/asus/m5a88-v/romstage.c b/src/mainboard/asus/m5a88-v/romstage.c
index ca9d1b1..35e9e94 100644
--- a/src/mainboard/asus/m5a88-v/romstage.c
+++ b/src/mainboard/asus/m5a88-v/romstage.c
@@ -223,8 +223,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
rs780_before_pci_init();
- timestamp_add_now(TS_END_ROMSTAGE);
-
post_code(0x42);
post_cache_as_ram(); // BSP switch stack to ram, copy then execute LB.
post_code(0x43); // Should never see this post code.
diff --git a/src/mainboard/avalue/eax-785e/romstage.c b/src/mainboard/avalue/eax-785e/romstage.c
index 71b2d5f..bace1d0 100644
--- a/src/mainboard/avalue/eax-785e/romstage.c
+++ b/src/mainboard/avalue/eax-785e/romstage.c
@@ -227,8 +227,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
rs780_before_pci_init();
- timestamp_add_now(TS_END_ROMSTAGE);
-
post_code(0x42);
post_cache_as_ram(); // BSP switch stack to ram, copy then execute LB.
post_code(0x43); // Should never see this post code.
diff --git a/src/mainboard/gigabyte/ma785gm/romstage.c b/src/mainboard/gigabyte/ma785gm/romstage.c
index 06b8d60..8ac24f9 100644
--- a/src/mainboard/gigabyte/ma785gm/romstage.c
+++ b/src/mainboard/gigabyte/ma785gm/romstage.c
@@ -221,8 +221,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
rs780_before_pci_init();
sb7xx_51xx_before_pci_init();
- timestamp_add_now(TS_END_ROMSTAGE);
-
post_code(0x42);
post_cache_as_ram(); // BSP switch stack to ram, copy then execute LB.
post_code(0x43); // Should never see this post code.
diff --git a/src/mainboard/gigabyte/ma785gmt/romstage.c b/src/mainboard/gigabyte/ma785gmt/romstage.c
index c213d16..cd9b790 100644
--- a/src/mainboard/gigabyte/ma785gmt/romstage.c
+++ b/src/mainboard/gigabyte/ma785gmt/romstage.c
@@ -221,8 +221,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
rs780_before_pci_init();
sb7xx_51xx_before_pci_init();
- timestamp_add_now(TS_END_ROMSTAGE);
-
post_code(0x42);
post_cache_as_ram(); // BSP switch stack to ram, copy then execute LB.
post_code(0x43); // Should never see this post code.
diff --git a/src/mainboard/gigabyte/ma78gm/romstage.c b/src/mainboard/gigabyte/ma78gm/romstage.c
index 1cc2b11..6cb4227 100644
--- a/src/mainboard/gigabyte/ma78gm/romstage.c
+++ b/src/mainboard/gigabyte/ma78gm/romstage.c
@@ -224,8 +224,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
rs780_before_pci_init();
sb7xx_51xx_before_pci_init();
- timestamp_add_now(TS_END_ROMSTAGE);
-
post_code(0x42);
post_cache_as_ram(); // BSP switch stack to ram, copy then execute LB.
post_code(0x43); // Should never see this post code.
diff --git a/src/mainboard/google/cosmos/romstage.c b/src/mainboard/google/cosmos/romstage.c
index e10b3ac..0f07354 100644
--- a/src/mainboard/google/cosmos/romstage.c
+++ b/src/mainboard/google/cosmos/romstage.c
@@ -53,7 +53,5 @@ void main(void)
cbmem_initialize_empty();
- timestamp_add_now(TS_END_ROMSTAGE);
-
run_ramstage();
}
diff --git a/src/mainboard/google/daisy/romstage.c b/src/mainboard/google/daisy/romstage.c
index 6f3cb77..b559c85 100644
--- a/src/mainboard/google/daisy/romstage.c
+++ b/src/mainboard/google/daisy/romstage.c
@@ -179,7 +179,5 @@ void main(void)
cbmem_initialize_empty();
- timestamp_add_now(TS_END_ROMSTAGE);
-
run_ramstage();
}
diff --git a/src/mainboard/google/link/romstage.c b/src/mainboard/google/link/romstage.c
index e9b4a09..aa36bc5 100644
--- a/src/mainboard/google/link/romstage.c
+++ b/src/mainboard/google/link/romstage.c
@@ -247,6 +247,4 @@ void main(unsigned long bist)
if (CONFIG_LPC_TPM) {
init_tpm(boot_mode == 2);
}
-
- timestamp_add_now(TS_END_ROMSTAGE);
}
diff --git a/src/mainboard/google/parrot/romstage.c b/src/mainboard/google/parrot/romstage.c
index a947c48..582d9e0 100644
--- a/src/mainboard/google/parrot/romstage.c
+++ b/src/mainboard/google/parrot/romstage.c
@@ -198,5 +198,4 @@ void main(unsigned long bist)
if (CONFIG_LPC_TPM) {
init_tpm(boot_mode == 2);
}
- timestamp_add_now(TS_END_ROMSTAGE);
}
diff --git a/src/mainboard/google/peach_pit/romstage.c b/src/mainboard/google/peach_pit/romstage.c
index 635877b..d5fdfb1 100644
--- a/src/mainboard/google/peach_pit/romstage.c
+++ b/src/mainboard/google/peach_pit/romstage.c
@@ -278,7 +278,5 @@ void main(void)
simple_spi_test();
- timestamp_add_now(TS_END_ROMSTAGE);
-
run_ramstage();
}
diff --git a/src/mainboard/google/stout/romstage.c b/src/mainboard/google/stout/romstage.c
index 31b61e2..3d18f18 100644
--- a/src/mainboard/google/stout/romstage.c
+++ b/src/mainboard/google/stout/romstage.c
@@ -252,5 +252,4 @@ void main(unsigned long bist)
if (CONFIG_LPC_TPM) {
init_tpm(boot_mode == 2);
}
- timestamp_add_now(TS_END_ROMSTAGE);
}
diff --git a/src/mainboard/google/veyron/romstage.c b/src/mainboard/google/veyron/romstage.c
index 5ccbe3e..a8d8f7d 100644
--- a/src/mainboard/google/veyron/romstage.c
+++ b/src/mainboard/google/veyron/romstage.c
@@ -111,7 +111,5 @@ void main(void)
cbmem_initialize_empty();
- timestamp_add_now(TS_END_ROMSTAGE);
-
run_ramstage();
}
diff --git a/src/mainboard/google/veyron_brain/romstage.c b/src/mainboard/google/veyron_brain/romstage.c
index f243235..e946cc6 100644
--- a/src/mainboard/google/veyron_brain/romstage.c
+++ b/src/mainboard/google/veyron_brain/romstage.c
@@ -102,7 +102,5 @@ void main(void)
cbmem_initialize_empty();
- timestamp_add_now(TS_END_ROMSTAGE);
-
run_ramstage();
}
diff --git a/src/mainboard/google/veyron_danger/romstage.c b/src/mainboard/google/veyron_danger/romstage.c
index e9857b8..0c1bb31 100644
--- a/src/mainboard/google/veyron_danger/romstage.c
+++ b/src/mainboard/google/veyron_danger/romstage.c
@@ -106,7 +106,5 @@ void main(void)
cbmem_initialize_empty();
- timestamp_add_now(TS_END_ROMSTAGE);
-
run_ramstage();
}
diff --git a/src/mainboard/google/veyron_mickey/romstage.c b/src/mainboard/google/veyron_mickey/romstage.c
index f243235..e946cc6 100644
--- a/src/mainboard/google/veyron_mickey/romstage.c
+++ b/src/mainboard/google/veyron_mickey/romstage.c
@@ -102,7 +102,5 @@ void main(void)
cbmem_initialize_empty();
- timestamp_add_now(TS_END_ROMSTAGE);
-
run_ramstage();
}
diff --git a/src/mainboard/google/veyron_rialto/romstage.c b/src/mainboard/google/veyron_rialto/romstage.c
index 9cdacc3..e845a42 100644
--- a/src/mainboard/google/veyron_rialto/romstage.c
+++ b/src/mainboard/google/veyron_rialto/romstage.c
@@ -112,7 +112,5 @@ void main(void)
cbmem_initialize_empty();
- timestamp_add_now(TS_END_ROMSTAGE);
-
run_ramstage();
}
diff --git a/src/mainboard/google/veyron_romy/romstage.c b/src/mainboard/google/veyron_romy/romstage.c
index f243235..e946cc6 100644
--- a/src/mainboard/google/veyron_romy/romstage.c
+++ b/src/mainboard/google/veyron_romy/romstage.c
@@ -102,7 +102,5 @@ void main(void)
cbmem_initialize_empty();
- timestamp_add_now(TS_END_ROMSTAGE);
-
run_ramstage();
}
diff --git a/src/mainboard/hp/dl165_g6_fam10/romstage.c b/src/mainboard/hp/dl165_g6_fam10/romstage.c
index ff2ed10..62fd6cb 100644
--- a/src/mainboard/hp/dl165_g6_fam10/romstage.c
+++ b/src/mainboard/hp/dl165_g6_fam10/romstage.c
@@ -218,8 +218,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
bcm5785_early_setup();
- timestamp_add_now(TS_END_ROMSTAGE);
-
post_cache_as_ram();
}
diff --git a/src/mainboard/iei/kino-780am2-fam10/romstage.c b/src/mainboard/iei/kino-780am2-fam10/romstage.c
index f822922..6df828b 100644
--- a/src/mainboard/iei/kino-780am2-fam10/romstage.c
+++ b/src/mainboard/iei/kino-780am2-fam10/romstage.c
@@ -224,8 +224,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
rs780_before_pci_init();
sb7xx_51xx_before_pci_init();
- timestamp_add_now(TS_END_ROMSTAGE);
-
post_code(0x42);
post_cache_as_ram(); // BSP switch stack to ram, copy then execute LB.
post_code(0x43); // Should never see this post code.
diff --git a/src/mainboard/intel/cougar_canyon2/romstage.c b/src/mainboard/intel/cougar_canyon2/romstage.c
index 92d0518..45da7d1 100644
--- a/src/mainboard/intel/cougar_canyon2/romstage.c
+++ b/src/mainboard/intel/cougar_canyon2/romstage.c
@@ -306,8 +306,6 @@ void romstage_main_continue(EFI_STATUS status, VOID *HobListPtr) {
*(u32*)cbmem_hob_ptr = (u32)HobListPtr;
post_code(0x4f);
- timestamp_add_now(TS_END_ROMSTAGE);
-
/* Load the ramstage. */
copy_and_run();
while (1);
diff --git a/src/mainboard/intel/emeraldlake2/romstage.c b/src/mainboard/intel/emeraldlake2/romstage.c
index bcf498b..5bdbdc6 100644
--- a/src/mainboard/intel/emeraldlake2/romstage.c
+++ b/src/mainboard/intel/emeraldlake2/romstage.c
@@ -256,5 +256,4 @@ void main(unsigned long bist)
if (CONFIG_LPC_TPM) {
init_tpm(boot_mode == 2);
}
- timestamp_add_now(TS_END_ROMSTAGE);
}
diff --git a/src/mainboard/jetway/pa78vm5/romstage.c b/src/mainboard/jetway/pa78vm5/romstage.c
index 3559642..ac66ada 100644
--- a/src/mainboard/jetway/pa78vm5/romstage.c
+++ b/src/mainboard/jetway/pa78vm5/romstage.c
@@ -229,8 +229,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
rs780_before_pci_init();
sb7xx_51xx_before_pci_init();
- timestamp_add_now(TS_END_ROMSTAGE);
-
post_code(0x42);
post_cache_as_ram(); // BSP switch stack to ram, copy then execute LB.
post_code(0x43); // Should never see this post code.
diff --git a/src/mainboard/kontron/ktqm77/romstage.c b/src/mainboard/kontron/ktqm77/romstage.c
index 869e020..57f8542 100644
--- a/src/mainboard/kontron/ktqm77/romstage.c
+++ b/src/mainboard/kontron/ktqm77/romstage.c
@@ -243,5 +243,4 @@ void main(unsigned long bist)
northbridge_romstage_finalize(boot_mode==2);
post_code(0x3f);
- timestamp_add_now(TS_END_ROMSTAGE);
}
diff --git a/src/mainboard/lenovo/t60/romstage.c b/src/mainboard/lenovo/t60/romstage.c
index 280722f..16fa871 100644
--- a/src/mainboard/lenovo/t60/romstage.c
+++ b/src/mainboard/lenovo/t60/romstage.c
@@ -284,6 +284,4 @@ void main(unsigned long bist)
/* Initialize the internal PCIe links before we go into stage2 */
i945_late_initialization(s3resume);
-
- timestamp_add_now(TS_END_ROMSTAGE);
}
diff --git a/src/mainboard/lenovo/x201/romstage.c b/src/mainboard/lenovo/x201/romstage.c
index 1e335d3..4be1ead 100644
--- a/src/mainboard/lenovo/x201/romstage.c
+++ b/src/mainboard/lenovo/x201/romstage.c
@@ -310,6 +310,4 @@ void main(unsigned long bist)
#if CONFIG_LPC_TPM
init_tpm(s3resume);
#endif
-
- timestamp_add_now(TS_END_ROMSTAGE);
}
diff --git a/src/mainboard/lenovo/x60/romstage.c b/src/mainboard/lenovo/x60/romstage.c
index e9cd80d..7765812 100644
--- a/src/mainboard/lenovo/x60/romstage.c
+++ b/src/mainboard/lenovo/x60/romstage.c
@@ -284,7 +284,4 @@ void main(unsigned long bist)
/* Initialize the internal PCIe links before we go into stage2 */
i945_late_initialization(s3resume);
-
- timestamp_add_now(TS_END_ROMSTAGE);
-
}
diff --git a/src/mainboard/msi/ms9652_fam10/romstage.c b/src/mainboard/msi/ms9652_fam10/romstage.c
index ef35fc9..b8fca64 100644
--- a/src/mainboard/msi/ms9652_fam10/romstage.c
+++ b/src/mainboard/msi/ms9652_fam10/romstage.c
@@ -243,8 +243,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
amdmct_cbmem_store_info(sysinfo);
- timestamp_add_now(TS_END_ROMSTAGE);
-
post_cache_as_ram(); // BSP switch stack to ram, copy then execute LB.
post_code(0x43); // Should never see this post code.
}
diff --git a/src/mainboard/packardbell/ms2290/romstage.c b/src/mainboard/packardbell/ms2290/romstage.c
index 82bacfe..074b31c 100644
--- a/src/mainboard/packardbell/ms2290/romstage.c
+++ b/src/mainboard/packardbell/ms2290/romstage.c
@@ -297,6 +297,4 @@ void main(unsigned long bist)
quick_ram_check();
}
#endif
-
- timestamp_add_now(TS_END_ROMSTAGE);
}
diff --git a/src/mainboard/samsung/lumpy/romstage.c b/src/mainboard/samsung/lumpy/romstage.c
index 015ae08..f2d5f4c 100644
--- a/src/mainboard/samsung/lumpy/romstage.c
+++ b/src/mainboard/samsung/lumpy/romstage.c
@@ -274,5 +274,4 @@ void main(unsigned long bist)
if (CONFIG_LPC_TPM) {
init_tpm(boot_mode == 2);
}
- timestamp_add_now(TS_END_ROMSTAGE);
}
diff --git a/src/mainboard/samsung/stumpy/romstage.c b/src/mainboard/samsung/stumpy/romstage.c
index 161c8d1..7fa93b8 100644
--- a/src/mainboard/samsung/stumpy/romstage.c
+++ b/src/mainboard/samsung/stumpy/romstage.c
@@ -284,5 +284,4 @@ void main(unsigned long bist)
if (CONFIG_LPC_TPM) {
init_tpm(boot_mode == 2);
}
- timestamp_add_now(TS_END_ROMSTAGE);
}
diff --git a/src/mainboard/supermicro/h8dmr_fam10/romstage.c b/src/mainboard/supermicro/h8dmr_fam10/romstage.c
index 405ec2e..d94d917 100644
--- a/src/mainboard/supermicro/h8dmr_fam10/romstage.c
+++ b/src/mainboard/supermicro/h8dmr_fam10/romstage.c
@@ -240,8 +240,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
amdmct_cbmem_store_info(sysinfo);
- timestamp_add_now(TS_END_ROMSTAGE);
-
post_cache_as_ram(); // BSP switch stack to ram, copy + execute stage 2
post_code(0x42); // Should never see this post code.
}
diff --git a/src/mainboard/supermicro/h8qme_fam10/romstage.c b/src/mainboard/supermicro/h8qme_fam10/romstage.c
index f74decb..c79c2b1 100644
--- a/src/mainboard/supermicro/h8qme_fam10/romstage.c
+++ b/src/mainboard/supermicro/h8qme_fam10/romstage.c
@@ -304,8 +304,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
amdmct_cbmem_store_info(sysinfo);
- timestamp_add_now(TS_END_ROMSTAGE);
-
post_cache_as_ram(); /* BSP switch stack to ram, copy then execute CB. */
post_code(0x42); /* Should never see this post code. */
}
diff --git a/src/mainboard/supermicro/h8scm_fam10/romstage.c b/src/mainboard/supermicro/h8scm_fam10/romstage.c
index 1c9fc8d..b3174ae 100644
--- a/src/mainboard/supermicro/h8scm_fam10/romstage.c
+++ b/src/mainboard/supermicro/h8scm_fam10/romstage.c
@@ -239,8 +239,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
sr5650_before_pci_init();
sb7xx_51xx_before_pci_init();
- timestamp_add_now(TS_END_ROMSTAGE);
-
post_code(0x42);
post_cache_as_ram(); // BSP switch stack to ram, copy then execute LB.
post_code(0x43); // Should never see this post code.
diff --git a/src/mainboard/tyan/s2912_fam10/romstage.c b/src/mainboard/tyan/s2912_fam10/romstage.c
index 5f49a35..1049014 100644
--- a/src/mainboard/tyan/s2912_fam10/romstage.c
+++ b/src/mainboard/tyan/s2912_fam10/romstage.c
@@ -239,8 +239,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
amdmct_cbmem_store_info(sysinfo);
- timestamp_add_now(TS_END_ROMSTAGE);
-
post_cache_as_ram(); // BSP switch stack to ram, copy then execute LB.
post_code(0x43); // Should never see this post code.
}
diff --git a/src/mainboard/via/epia-m850/romstage.c b/src/mainboard/via/epia-m850/romstage.c
index 8912d13..b38cd71 100644
--- a/src/mainboard/via/epia-m850/romstage.c
+++ b/src/mainboard/via/epia-m850/romstage.c
@@ -96,7 +96,6 @@ void main(unsigned long bist)
#if CONFIG_EARLY_CBMEM_INIT
cbmem_recovery(0);
#endif
- timestamp_add_now(TS_END_ROMSTAGE);
/* FIXME: See if this is needed or take this out please */
/* Disable Memcard and SDIO */
pci_mod_config8(LPC, 0x51, 0, (1 << 7) | (1 << 4));
diff --git a/src/northbridge/intel/sandybridge/romstage_native.c b/src/northbridge/intel/sandybridge/romstage_native.c
index 45f671c..a18c480 100644
--- a/src/northbridge/intel/sandybridge/romstage_native.c
+++ b/src/northbridge/intel/sandybridge/romstage_native.c
@@ -135,5 +135,4 @@ void main(unsigned long bist)
#endif
post_code(0x3f);
- timestamp_add_now(TS_END_ROMSTAGE);
}
diff --git a/src/soc/intel/baytrail/romstage/romstage.c b/src/soc/intel/baytrail/romstage/romstage.c
index 1b93eb6..8df022b 100644
--- a/src/soc/intel/baytrail/romstage/romstage.c
+++ b/src/soc/intel/baytrail/romstage/romstage.c
@@ -250,8 +250,6 @@ void romstage_common(struct romstage_params *params)
void asmlinkage romstage_after_car(void)
{
- timestamp_add_now(TS_END_ROMSTAGE);
-
/* Load the ramstage. */
copy_and_run();
while (1);
diff --git a/src/soc/intel/broadwell/romstage/romstage.c b/src/soc/intel/broadwell/romstage/romstage.c
index 27fb0f2..bfda862 100644
--- a/src/soc/intel/broadwell/romstage/romstage.c
+++ b/src/soc/intel/broadwell/romstage/romstage.c
@@ -132,8 +132,6 @@ void romstage_common(struct romstage_params *params)
void asmlinkage romstage_after_car(void)
{
- timestamp_add_now(TS_END_ROMSTAGE);
-
/* Load the ramstage. */
copy_and_run();
while (1);
diff --git a/src/soc/intel/common/romstage.c b/src/soc/intel/common/romstage.c
index ee9c975..0d5e85f 100644
--- a/src/soc/intel/common/romstage.c
+++ b/src/soc/intel/common/romstage.c
@@ -207,8 +207,6 @@ asmlinkage void romstage_after_car(void *chipset_context)
soc_after_temp_ram_exit();
soc_display_mtrrs();
- timestamp_add_now(TS_END_ROMSTAGE);
-
/* Load the ramstage. */
copy_and_run();
die("ERROR - Failed to load ramstage!");
diff --git a/src/soc/intel/fsp_baytrail/romstage/romstage.c b/src/soc/intel/fsp_baytrail/romstage/romstage.c
index c40f163..b5384fa 100644
--- a/src/soc/intel/fsp_baytrail/romstage/romstage.c
+++ b/src/soc/intel/fsp_baytrail/romstage/romstage.c
@@ -267,8 +267,6 @@ void romstage_main_continue(EFI_STATUS status, void *hob_list_ptr) {
else
printk(BIOS_DEBUG, "Romstage handoff structure not added!\n");
- timestamp_add_now(TS_END_ROMSTAGE);
-
post_code(0x4f);
/* Load the ramstage. */
diff --git a/src/southbridge/intel/fsp_rangeley/romstage.c b/src/southbridge/intel/fsp_rangeley/romstage.c
index 3500dfd..bc58b48 100644
--- a/src/southbridge/intel/fsp_rangeley/romstage.c
+++ b/src/southbridge/intel/fsp_rangeley/romstage.c
@@ -130,8 +130,6 @@ void romstage_main_continue(EFI_STATUS status, void *hob_list_ptr) {
*(u32*)cbmem_hob_ptr = (u32)hob_list_ptr;
post_code(0x4e);
- timestamp_add_now(TS_END_ROMSTAGE);
-
post_code(0x4f);
/* Load the ramstage. */
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