[coreboot-gerrit] New patch to review for coreboot: AMD bettong: Add UART support.
Zheng Bao (zheng.bao@amd.com)
gerrit at coreboot.org
Wed Sep 30 04:25:50 CET 2015
Zheng Bao (zheng.bao at amd.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11749
-gerrit
commit f01d4f0de638dea2cd9c38e3a6f4da338e09db22
Author: zbao <fishbaozi at gmail.com>
Date: Fri Jul 17 14:33:16 2015 -0400
AMD bettong: Add UART support.
Change-Id: I4cec833cc2ff8069c82886837f7cbd4483ff11bb
Signed-off-by: Zheng Bao <zheng.bao at amd.com>
Signed-off-by: Zheng Bao <fishbaozi at gmail.com>
---
src/drivers/uart/uart8250mem.c | 12 ++++--
src/mainboard/amd/bettong/Kconfig | 12 ++++++
src/mainboard/amd/bettong/romstage.c | 26 ++++++++++++
src/southbridge/amd/pi/hudson/Makefile.inc | 5 +++
src/southbridge/amd/pi/hudson/acpi/uart.asl | 66 +++++++++++++++++++++++++++++
src/southbridge/amd/pi/hudson/uart.c | 30 +++++++++++++
6 files changed, 148 insertions(+), 3 deletions(-)
diff --git a/src/drivers/uart/uart8250mem.c b/src/drivers/uart/uart8250mem.c
index fb7327e..be291f3 100644
--- a/src/drivers/uart/uart8250mem.c
+++ b/src/drivers/uart/uart8250mem.c
@@ -36,6 +36,12 @@
#define SINGLE_CHAR_TIMEOUT (50 * 1000)
#define FIFO_TIMEOUT (16 * SINGLE_CHAR_TIMEOUT)
+static void my_delay(int delay)
+{
+ while (delay --)
+ outb(0xaa, 0x80);
+}
+
#if IS_ENABLED(CONFIG_DRIVERS_UART_8250MEM_32)
static uint8_t uart8250_read(void *base, uint8_t reg)
{
@@ -67,7 +73,7 @@ static void uart8250_mem_tx_byte(void *base, unsigned char data)
{
unsigned long int i = SINGLE_CHAR_TIMEOUT;
while(i-- && !uart8250_mem_can_tx_byte(base))
- udelay(1);
+ my_delay(1);
uart8250_write(base, UART8250_TBR, data);
}
@@ -75,7 +81,7 @@ static void uart8250_mem_tx_flush(void *base)
{
unsigned long int i = FIFO_TIMEOUT;
while(i-- && !(uart8250_read(base, UART8250_LSR) & UART8250_LSR_TEMT))
- udelay(1);
+ my_delay(1);
}
static int uart8250_mem_can_rx_byte(void *base)
@@ -87,7 +93,7 @@ static unsigned char uart8250_mem_rx_byte(void *base)
{
unsigned long int i = SINGLE_CHAR_TIMEOUT;
while(i-- && !uart8250_mem_can_rx_byte(base))
- udelay(1);
+ my_delay(1);
if (i)
return uart8250_read(base, UART8250_RBR);
else
diff --git a/src/mainboard/amd/bettong/Kconfig b/src/mainboard/amd/bettong/Kconfig
index 1f2d888..3fa4ee3 100644
--- a/src/mainboard/amd/bettong/Kconfig
+++ b/src/mainboard/amd/bettong/Kconfig
@@ -55,4 +55,16 @@ config HUDSON_LEGACY_FREE
bool
default y
+config DRIVERS_UART_8250MEM
+ bool
+ default y
+
+config DRIVERS_UART_8250MEM_32
+ bool
+ default y
+
+config DRIVERS_UART_8250IO
+ bool
+ default n
+
endif # BOARD_AMD_BETTONG
diff --git a/src/mainboard/amd/bettong/romstage.c b/src/mainboard/amd/bettong/romstage.c
index a8a2777..1bfa9a3 100644
--- a/src/mainboard/amd/bettong/romstage.c
+++ b/src/mainboard/amd/bettong/romstage.c
@@ -27,6 +27,10 @@
#include <northbridge/amd/pi/agesawrapper.h>
#include <northbridge/amd/pi/agesawrapper_call.h>
#include <southbridge/amd/pi/hudson/hudson.h>
+#include <delay.h>
+
+#define ACPI_MMIO_BASE ((void *)0xFED80000)
+#define AOAC_BASE 0x1E00
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
{
@@ -34,6 +38,10 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
#if CONFIG_HAVE_ACPI_RESUME
void *resume_backup_memory;
#endif
+#if CONFIG_DRIVERS_UART_8250MEM
+ u8 byte;
+ msr_t msr;
+#endif
amd_initmmio();
@@ -43,6 +51,24 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
post_code(0x30);
post_code(0x31);
+#if CONFIG_DRIVERS_UART_8250MEM
+ msr = rdmsr(0x1B);
+ msr.lo |= 1 << 11;
+ wrmsr(0x1B, msr);
+ byte = read8(ACPI_MMIO_BASE + AOAC_BASE + 0x56 + CONFIG_UART_FOR_CONSOLE * 2);
+ byte |= 1 << 3;
+ write8(ACPI_MMIO_BASE + AOAC_BASE + 0x56 + CONFIG_UART_FOR_CONSOLE * 2, byte);
+ byte = read8(ACPI_MMIO_BASE + AOAC_BASE + 0x62);
+ byte |= 1 << 3;
+ write8(ACPI_MMIO_BASE + AOAC_BASE + 0x62, byte);
+ write8(ACPI_MMIO_BASE + 0xD00 + 0x89, 0);
+ write8(ACPI_MMIO_BASE + 0xD00 + 0x8A, 0);
+ write8(ACPI_MMIO_BASE + 0xD00 + 0x8E, 0);
+ write8(ACPI_MMIO_BASE + 0xD00 + 0x8F, 0);
+
+ udelay(2000);
+ write8((void *)0xFEDC6000 + 0x2000 * CONFIG_UART_FOR_CONSOLE + 0x88, 0x01); //reset UART
+#endif
console_init();
}
diff --git a/src/southbridge/amd/pi/hudson/Makefile.inc b/src/southbridge/amd/pi/hudson/Makefile.inc
index 00d150f..138520e 100644
--- a/src/southbridge/amd/pi/hudson/Makefile.inc
+++ b/src/southbridge/amd/pi/hudson/Makefile.inc
@@ -50,6 +50,11 @@ romstage-y += imc.c
ramstage-y += imc.c
endif
+ifeq ($(CONFIG_DRIVERS_UART_8250MEM), y)
+romstage-y += uart.c
+ramstage-y += uart.c
+endif
+
smm-$(CONFIG_HAVE_SMI_HANDLER) += smihandler.c smi_util.c
ramstage-$(CONFIG_HAVE_SMI_HANDLER) += smi.c smi_util.c
diff --git a/src/southbridge/amd/pi/hudson/acpi/uart.asl b/src/southbridge/amd/pi/hudson/acpi/uart.asl
new file mode 100644
index 0000000..da7817b
--- /dev/null
+++ b/src/southbridge/amd/pi/hudson/acpi/uart.asl
@@ -0,0 +1,66 @@
+ Scope(\_SB.FUR0)
+ {
+ Device(UART)
+ {
+ Name(_HID, "UTK0001")
+ Name(_CID, "UARTTest")
+ Name(_UID, Zero)
+ Method(_CRS, 0, NotSerialized)
+ {
+ Name(RBUF, Buffer(0x22)
+ {
+ 0x8E, 0x1D, 0x00, 0x01, 0x00, 0x03, 0x02, 0x35,
+ 0x00, 0x01, 0x0A, 0x00, 0x00, 0xC2, 0x01, 0x00,
+ 0x20, 0x00, 0x20, 0x00, 0x00, 0xC0, 0x5C, 0x5F,
+ 0x53, 0x42, 0x2E, 0x46, 0x55, 0x52, 0x30, 0x00,
+ 0x79, 0x00
+ })
+ Return(RBUF)
+ }
+ Method(_STA, 0, NotSerialized)
+ {
+ If(LEqual(MWTT, Zero))
+ {
+ Return(0x0F)
+ }
+ Else
+ {
+ Return(Zero)
+ }
+ }
+ }
+ }
+/*
+ Scope(\_SB.FUR1)
+ {
+ Device(UART)
+ {
+ Name(_HID, "UTK0001")
+ Name(_CID, "UARTTest")
+ Name(_UID, One)
+ Method(_CRS, 0, NotSerialized)
+ {
+ Name(RBUF, Buffer(0x22)
+ {
+ 0x8E, 0x1D, 0x00, 0x01, 0x00, 0x03, 0x02, 0x35,
+ 0x00, 0x01, 0x0A, 0x00, 0x00, 0xC2, 0x01, 0x00,
+ 0x20, 0x00, 0x20, 0x00, 0x00, 0xC0, 0x5C, 0x5F,
+ 0x53, 0x42, 0x2E, 0x46, 0x55, 0x52, 0x31, 0x00,
+ 0x79, 0x00
+ })
+ Return(RBUF)
+ }
+ Method(_STA, 0, NotSerialized)
+ {
+ If(LEqual(MWTT, Zero))
+ {
+ Return(0x0F)
+ }
+ Else
+ {
+ Return(Zero)
+ }
+ }
+ }
+ }
+*/
diff --git a/src/southbridge/amd/pi/hudson/uart.c b/src/southbridge/amd/pi/hudson/uart.c
new file mode 100644
index 0000000..523ce73
--- /dev/null
+++ b/src/southbridge/amd/pi/hudson/uart.c
@@ -0,0 +1,30 @@
+
+
+#include <boot/coreboot_tables.h>
+#include <console/console.h> /* for __console definition */
+#include <console/uart.h>
+#include <drivers/uart/uart8250reg.h>
+
+#define ACPI_MMIO_BASE 0xFED80000
+#define AOAC_BASE 0x1E00
+uintptr_t uart_platform_base(int idx)
+{
+ return (uintptr_t)(0xFEDC6000 + 0x2000 * (idx & 1));
+}
+
+unsigned int uart_platform_refclk(void)
+{
+ return 48000000;
+}
+
+void uart_fill_lb(void *data)
+{
+ struct lb_serial serial;
+ serial.type = LB_SERIAL_TYPE_MEMORY_MAPPED;
+ serial.baseaddr = uart_platform_base(CONFIG_UART_FOR_CONSOLE);
+ serial.baud = default_baudrate();
+ serial.regwidth = 1;
+ lb_add_serial(&serial, data);
+
+ lb_add_console(LB_TAG_CONSOLE_SERIAL8250MEM, data);
+}
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