[coreboot-gerrit] Patch set updated for coreboot: drivers/intel/fsp2_0: Display FSP calls and status
Lee Leahy (leroy.p.leahy@intel.com)
gerrit at coreboot.org
Tue Aug 2 02:31:09 CEST 2016
Lee Leahy (leroy.p.leahy at intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15989
-gerrit
commit 3e67711723506f05640d63d1637c53d6ad4b0fd4
Author: Lee Leahy <leroy.p.leahy at intel.com>
Date: Sun Jul 24 18:21:13 2016 -0700
drivers/intel/fsp2_0: Display FSP calls and status
Disable the chatty FSP behavior for normal builds. Use a Kconfig value
to enable the display of the FSP call entry points, the call parameters
and the returned status for MemoryInit, SiliconInit and FspNotify. The
debug code is placed into drivers/intel/fsp2_0/debug.c.
TEST=Build and run on Galileo Gen2
Change-Id: Iacae66f72bc5b4ba1469f53fcce4669726234441
Signed-off-by: Lee Leahy <leroy.p.leahy at intel.com>
---
src/drivers/intel/fsp2_0/Kconfig | 7 +++
src/drivers/intel/fsp2_0/Makefile.inc | 2 +
src/drivers/intel/fsp2_0/debug.c | 79 ++++++++++++++++++++++++++++
src/drivers/intel/fsp2_0/hand_off_block.c | 5 --
src/drivers/intel/fsp2_0/include/fsp/debug.h | 31 +++++++++++
src/drivers/intel/fsp2_0/include/fsp/util.h | 18 +++++++
src/drivers/intel/fsp2_0/memory_init.c | 10 ++--
src/drivers/intel/fsp2_0/notify.c | 11 +---
src/drivers/intel/fsp2_0/silicon_init.c | 12 ++---
9 files changed, 148 insertions(+), 27 deletions(-)
diff --git a/src/drivers/intel/fsp2_0/Kconfig b/src/drivers/intel/fsp2_0/Kconfig
index 01ce75d..7f4bbee 100644
--- a/src/drivers/intel/fsp2_0/Kconfig
+++ b/src/drivers/intel/fsp2_0/Kconfig
@@ -27,6 +27,13 @@ config ADD_FSP_BINARIES
Add the FSP-M and FSP-S binaries to CBFS. Currently coreboot does not
use the FSP-T binary and it is not added.
+config DISPLAY_FSP_CALLS_AND_STATUS
+ bool "Display the FSP calls and status"
+ default n
+ help
+ Display the FSP call entry point and parameters prior to calling FSP
+ and display the status upon return from FSP.
+
config FSP_S_CBFS
string "Name of FSP-S in CBFS"
default "fsps.bin"
diff --git a/src/drivers/intel/fsp2_0/Makefile.inc b/src/drivers/intel/fsp2_0/Makefile.inc
index 4f36664..9ec5192 100644
--- a/src/drivers/intel/fsp2_0/Makefile.inc
+++ b/src/drivers/intel/fsp2_0/Makefile.inc
@@ -15,10 +15,12 @@
ifeq ($(CONFIG_PLATFORM_USES_FSP2_0),y)
+romstage-y += debug.c
romstage-y += hand_off_block.c
romstage-y += util.c
romstage-y += memory_init.c
+ramstage-y += debug.c
ramstage-y += graphics.c
ramstage-y += hand_off_block.c
ramstage-y += notify.c
diff --git a/src/drivers/intel/fsp2_0/debug.c b/src/drivers/intel/fsp2_0/debug.c
new file mode 100644
index 0000000..31fba20
--- /dev/null
+++ b/src/drivers/intel/fsp2_0/debug.c
@@ -0,0 +1,79 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2016 Intel Corp.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+#include <console/console.h>
+#include <fsp/util.h>
+
+/*-----------
+ * MemoryInit
+ *-----------
+ */
+void fsp_debug_before_memory_init(fsp_memory_init_fn memory_init,
+ const struct FSPM_UPD *fspm_old_upd,
+ const struct FSPM_UPD *fspm_new_upd, void **hob_list_ptr)
+{
+ /* Display the call entry point and paramters */
+ if (!IS_ENABLED(CONFIG_DISPLAY_FSP_CALLS_AND_STATUS))
+ return;
+ printk(BIOS_DEBUG, "Calling FspMemoryInit: 0x%p\n", memory_init);
+ printk(BIOS_SPEW, "\t0x%p: raminit_upd\n", fspm_new_upd);
+ printk(BIOS_SPEW, "\t0x%p: &hob_list_ptr\n", hob_list_ptr);
+}
+
+void fsp_debug_after_memory_init(enum fsp_status status,
+ const struct hob_header *hob_list_ptr)
+{
+ if (IS_ENABLED(CONFIG_DISPLAY_FSP_CALLS_AND_STATUS))
+ printk(BIOS_DEBUG, "FspMemoryInit returned 0x%08x\n", status);
+}
+
+/*-----------
+ * SiliconInit
+ *-----------
+ */
+void fsp_debug_before_silicon_init(fsp_silicon_init_fn silicon_init,
+ const struct FSPS_UPD *fsps_old_upd,
+ const struct FSPS_UPD *fsps_new_upd)
+{
+ /* Display the call to FSP SiliconInit */
+ if (!IS_ENABLED(CONFIG_DISPLAY_FSP_CALLS_AND_STATUS))
+ return;
+ printk(BIOS_SPEW, "Calling FspSiliconInit: 0x%p\n", silicon_init);
+ printk(BIOS_SPEW, "\t0x%p: upd\n", fsps_new_upd);
+}
+
+void fsp_debug_after_silicon_init(enum fsp_status status)
+{
+ if (IS_ENABLED(CONFIG_DISPLAY_FSP_CALLS_AND_STATUS))
+ printk(BIOS_SPEW, "FspSiliconInit returned 0x%08x\n", status);
+}
+
+/*-----------
+ * FspNotify
+ *-----------
+ */
+void fsp_before_debug_notify(fsp_notify_fn notify,
+ const struct fsp_notify_params *notify_params)
+{
+ /* Display the call to FSP SiliconInit */
+ if (!IS_ENABLED(CONFIG_DISPLAY_FSP_CALLS_AND_STATUS))
+ return;
+ printk(BIOS_SPEW, "0x%08x: notify_params->phase\n",
+ notify_params->phase);
+ printk(BIOS_SPEW, "Calling FspNotify: 0x%p\n", notify);
+ printk(BIOS_SPEW, "\t0x%p: notify_params\n", notify_params);
+}
+
+void fsp_debug_after_notify(enum fsp_status status)
+{
+ if (IS_ENABLED(CONFIG_DISPLAY_FSP_CALLS_AND_STATUS))
+ printk(BIOS_SPEW, "FspNotify returned 0x%08x\n", status);
+}
diff --git a/src/drivers/intel/fsp2_0/hand_off_block.c b/src/drivers/intel/fsp2_0/hand_off_block.c
index b7cb981..ce06a82 100644
--- a/src/drivers/intel/fsp2_0/hand_off_block.c
+++ b/src/drivers/intel/fsp2_0/hand_off_block.c
@@ -21,11 +21,6 @@
#define HOB_HEADER_LEN 8
-struct hob_header {
- uint16_t type;
- uint16_t length;
-} __attribute__((packed));
-
struct hob_resource {
uint8_t owner_guid[16];
uint32_t type;
diff --git a/src/drivers/intel/fsp2_0/include/fsp/debug.h b/src/drivers/intel/fsp2_0/include/fsp/debug.h
new file mode 100644
index 0000000..68f1ecb
--- /dev/null
+++ b/src/drivers/intel/fsp2_0/include/fsp/debug.h
@@ -0,0 +1,31 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2016 Intel Corp.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+#ifndef _FSP2_0_DEBUG_H_
+#define _FSP2_0_DEBUG_H_
+
+#include <fsp/util.h>
+
+/* FSP debug API */
+void fsp_debug_before_memory_init(fsp_memory_init_fn memory_init,
+ const struct FSPM_UPD *fspm_old_upd,
+ const struct FSPM_UPD *fspm_new_upd, void **hob_list_ptr);
+void fsp_debug_after_memory_init(enum fsp_status status,
+ const struct hob_header *hob_list_ptr);
+void fsp_debug_before_silicon_init(fsp_silicon_init_fn silicon_init,
+ const struct FSPS_UPD *fsps_old_upd,
+ const struct FSPS_UPD *fsps_new_upd);
+void fsp_debug_after_silicon_init(enum fsp_status status);
+void fsp_before_debug_notify(fsp_notify_fn notify,
+ const struct fsp_notify_params *notify_params);
+void fsp_debug_after_notify(enum fsp_status status);
+
+#endif /* _FSP2_0_DEBUG_H_ */
diff --git a/src/drivers/intel/fsp2_0/include/fsp/util.h b/src/drivers/intel/fsp2_0/include/fsp/util.h
index 01186f7..b16a6ec 100644
--- a/src/drivers/intel/fsp2_0/include/fsp/util.h
+++ b/src/drivers/intel/fsp2_0/include/fsp/util.h
@@ -15,10 +15,20 @@
#include <boot/coreboot_tables.h>
#include <commonlib/region.h>
+#include <arch/cpu.h>
#include <fsp/api.h>
#include <fsp/info_header.h>
#include <memrange.h>
+struct hob_header {
+ uint16_t type;
+ uint16_t length;
+} __attribute__((packed));
+
+struct fsp_notify_params {
+ enum fsp_notify_phase phase;
+};
+
/*
* Hand-off-block handling functions that depend on CBMEM, and thus can only
* be used after cbmem_initialize().
@@ -53,4 +63,12 @@ void fsp_handle_reset(enum fsp_status status);
/* SoC/chipset must provide this to handle platform-specific reset codes */
void chipset_handle_reset(enum fsp_status status);
+typedef asmlinkage enum fsp_status (*fsp_memory_init_fn)
+ (void *raminit_upd, void **hob_list);
+typedef asmlinkage enum fsp_status (*fsp_silicon_init_fn)
+ (void *silicon_upd);
+typedef asmlinkage enum fsp_status (*fsp_notify_fn)
+ (struct fsp_notify_params *);
+#include <fsp/debug.h>
+
#endif /* _FSP2_0_UTIL_H_ */
diff --git a/src/drivers/intel/fsp2_0/memory_init.c b/src/drivers/intel/fsp2_0/memory_init.c
index 8e3eb68..ada1c28 100644
--- a/src/drivers/intel/fsp2_0/memory_init.c
+++ b/src/drivers/intel/fsp2_0/memory_init.c
@@ -29,9 +29,6 @@
#include <timestamp.h>
#include <vboot/vboot_common.h>
-typedef asmlinkage enum fsp_status (*fsp_memory_init_fn)
- (void *raminit_upd, void **hob_list);
-
static void save_memory_training_data(bool s3wake, uint32_t fsp_version)
{
size_t mrc_data_size;
@@ -221,9 +218,8 @@ static enum fsp_status do_fsp_memory_init(struct fsp_header *hdr, bool s3wake,
/* Call FspMemoryInit */
fsp_raminit = (void *)(hdr->image_base + hdr->memory_init_entry_offset);
- printk(BIOS_DEBUG, "Calling FspMemoryInit: 0x%p\n", fsp_raminit);
- printk(BIOS_SPEW, "\t%p: raminit_upd\n", &fspm_upd);
- printk(BIOS_SPEW, "\t%p: hob_list ptr\n", &hob_list_ptr);
+ fsp_debug_before_memory_init(fsp_raminit, upd, &fspm_upd,
+ &hob_list_ptr);
post_code(POST_FSP_MEMORY_INIT);
timestamp_add_now(TS_FSP_MEMORY_INIT_START);
@@ -231,7 +227,7 @@ static enum fsp_status do_fsp_memory_init(struct fsp_header *hdr, bool s3wake,
post_code(POST_FSP_MEMORY_INIT);
timestamp_add_now(TS_FSP_MEMORY_INIT_END);
- printk(BIOS_DEBUG, "FspMemoryInit returned 0x%08x\n", status);
+ fsp_debug_after_memory_init(status, hob_list_ptr);
/* Handle any resets requested by FSPM. */
fsp_handle_reset(status);
diff --git a/src/drivers/intel/fsp2_0/notify.c b/src/drivers/intel/fsp2_0/notify.c
index 4e7e9c5..f848986 100644
--- a/src/drivers/intel/fsp2_0/notify.c
+++ b/src/drivers/intel/fsp2_0/notify.c
@@ -17,13 +17,6 @@
#include <string.h>
#include <timestamp.h>
-struct fsp_notify_params {
- enum fsp_notify_phase phase;
-};
-
-typedef asmlinkage enum fsp_status (*fsp_notify_fn)
- (struct fsp_notify_params *);
-
enum fsp_status fsp_notify(enum fsp_notify_phase phase)
{
enum fsp_status ret;
@@ -35,8 +28,7 @@ enum fsp_status fsp_notify(enum fsp_notify_phase phase)
fspnotify = (void*) (fsps_hdr.image_base +
fsps_hdr.notify_phase_entry_offset);
-
- printk(BIOS_DEBUG, "FspNotify %x\n", (uint32_t) phase);
+ fsp_before_debug_notify(fspnotify, ¬ify_params);
if (phase == AFTER_PCI_ENUM) {
timestamp_add_now(TS_FSP_BEFORE_ENUMERATE);
@@ -55,6 +47,7 @@ enum fsp_status fsp_notify(enum fsp_notify_phase phase)
timestamp_add_now(TS_FSP_AFTER_FINALIZE);
post_code(POST_FSP_NOTIFY_BEFORE_FINALIZE);
}
+ fsp_debug_after_notify(ret);
return ret;
}
diff --git a/src/drivers/intel/fsp2_0/silicon_init.c b/src/drivers/intel/fsp2_0/silicon_init.c
index c069ff1..af40b6d 100644
--- a/src/drivers/intel/fsp2_0/silicon_init.c
+++ b/src/drivers/intel/fsp2_0/silicon_init.c
@@ -23,9 +23,6 @@
struct fsp_header fsps_hdr;
-typedef asmlinkage enum fsp_status (*fsp_silicon_init_fn)
- (void *silicon_upd);
-
static enum fsp_status do_silicon_init(struct fsp_header *hdr)
{
struct FSPS_UPD upd, *supd;
@@ -44,15 +41,18 @@ static enum fsp_status do_silicon_init(struct fsp_header *hdr)
/* Give SoC/mainboard a chance to populate entries */
platform_fsp_silicon_init_params_cb(&upd);
- timestamp_add_now(TS_FSP_SILICON_INIT_START);
- post_code(POST_FSP_SILICON_INIT);
+ /* Call SiliconInit */
silicon_init = (void *) (hdr->image_base +
hdr->silicon_init_entry_offset);
+ fsp_debug_before_silicon_init(silicon_init, supd, &upd);
+
+ timestamp_add_now(TS_FSP_SILICON_INIT_START);
+ post_code(POST_FSP_SILICON_INIT);
status = silicon_init(&upd);
timestamp_add_now(TS_FSP_SILICON_INIT_END);
post_code(POST_FSP_SILICON_INIT);
- printk(BIOS_DEBUG, "FspSiliconInit returned 0x%08x\n", status);
+ fsp_debug_after_silicon_init(status);
/* Handle any resets requested by FSPS. */
fsp_handle_reset(status);
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