[coreboot-gerrit] Patch set updated for coreboot: drivers/intel/fsp2_0: Add UPD display support
Lee Leahy (leroy.p.leahy@intel.com)
gerrit at coreboot.org
Wed Aug 3 05:45:58 CEST 2016
Lee Leahy (leroy.p.leahy at intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15847
-gerrit
commit e882d9579716ce81bf596d24e6670b56818864c4
Author: Lee Leahy <leroy.p.leahy at intel.com>
Date: Thu Jul 21 09:48:49 2016 -0700
drivers/intel/fsp2_0: Add UPD display support
Add UPD display support:
* Add a Kconfig value to enable UPD value display
* Add a routine to display a UPD value
* Add a call before MemoryInit to display the UPD parameters
* Add a routine to display the architectural parameters for MemoryInit
* Add a weak routine to display the other UPD parameters for MemoryInit
* Add a call before SiliconInit to display the UPD parameters
* Add a weak routine to display the UPD parameters for SiliconInit
TEST=Build and run on Galileo Gen2.
Change-Id: I35fb8410c0bccf217b32af4b8bbe5ad6671f81f6
Signed-off-by: Lee Leahy <leroy.p.leahy at intel.com>
---
src/drivers/intel/fsp2_0/Kconfig | 7 +++
src/drivers/intel/fsp2_0/Makefile.inc | 2 +
src/drivers/intel/fsp2_0/debug.c | 8 +++
src/drivers/intel/fsp2_0/include/fsp/debug.h | 14 +++++
src/drivers/intel/fsp2_0/upd_display.c | 76 ++++++++++++++++++++++++++++
5 files changed, 107 insertions(+)
diff --git a/src/drivers/intel/fsp2_0/Kconfig b/src/drivers/intel/fsp2_0/Kconfig
index 7f4bbee..32dbb59 100644
--- a/src/drivers/intel/fsp2_0/Kconfig
+++ b/src/drivers/intel/fsp2_0/Kconfig
@@ -34,6 +34,13 @@ config DISPLAY_FSP_CALLS_AND_STATUS
Display the FSP call entry point and parameters prior to calling FSP
and display the status upon return from FSP.
+config DISPLAY_UPD_DATA
+ bool "Display UPD data"
+ default n
+ help
+ Display the user specified product data prior to memory
+ initialization.
+
config FSP_S_CBFS
string "Name of FSP-S in CBFS"
default "fsps.bin"
diff --git a/src/drivers/intel/fsp2_0/Makefile.inc b/src/drivers/intel/fsp2_0/Makefile.inc
index 9ec5192..cc496ee 100644
--- a/src/drivers/intel/fsp2_0/Makefile.inc
+++ b/src/drivers/intel/fsp2_0/Makefile.inc
@@ -17,6 +17,7 @@ ifeq ($(CONFIG_PLATFORM_USES_FSP2_0),y)
romstage-y += debug.c
romstage-y += hand_off_block.c
+romstage-$(CONFIG_DISPLAY_UPD_DATA) += upd_display.c
romstage-y += util.c
romstage-y += memory_init.c
@@ -25,6 +26,7 @@ ramstage-y += graphics.c
ramstage-y += hand_off_block.c
ramstage-y += notify.c
ramstage-y += silicon_init.c
+ramstage-$(CONFIG_DISPLAY_UPD_DATA) += upd_display.c
ramstage-y += util.c
CPPFLAGS_common += -I$(src)/drivers/intel/fsp2_0/include
diff --git a/src/drivers/intel/fsp2_0/debug.c b/src/drivers/intel/fsp2_0/debug.c
index 6998295..b34910b 100644
--- a/src/drivers/intel/fsp2_0/debug.c
+++ b/src/drivers/intel/fsp2_0/debug.c
@@ -25,6 +25,10 @@ void fsp_debug_before_memory_init(fsp_memory_init_fn memory_init,
if (IS_ENABLED(CONFIG_DISPLAY_MTRRS))
soc_display_mtrrs();
+ /* Display the UPD values */
+ if (IS_ENABLED(CONFIG_DISPLAY_UPD_DATA))
+ fspm_display_upd_values(fspm_old_upd, fspm_new_upd);
+
/* Display the call entry point and paramters */
if (!IS_ENABLED(CONFIG_DISPLAY_FSP_CALLS_AND_STATUS))
return;
@@ -56,6 +60,10 @@ void fsp_debug_before_silicon_init(fsp_silicon_init_fn silicon_init,
if (IS_ENABLED(CONFIG_DISPLAY_MTRRS))
soc_display_mtrrs();
+ /* Display the UPD values */
+ if (IS_ENABLED(CONFIG_DISPLAY_UPD_DATA))
+ soc_display_fsps_upd_params(fsps_old_upd, fsps_new_upd);
+
/* Display the call to FSP SiliconInit */
if (!IS_ENABLED(CONFIG_DISPLAY_FSP_CALLS_AND_STATUS))
return;
diff --git a/src/drivers/intel/fsp2_0/include/fsp/debug.h b/src/drivers/intel/fsp2_0/include/fsp/debug.h
index 68f1ecb..21e1754 100644
--- a/src/drivers/intel/fsp2_0/include/fsp/debug.h
+++ b/src/drivers/intel/fsp2_0/include/fsp/debug.h
@@ -27,5 +27,19 @@ void fsp_debug_after_silicon_init(enum fsp_status status);
void fsp_before_debug_notify(fsp_notify_fn notify,
const struct fsp_notify_params *notify_params);
void fsp_debug_after_notify(enum fsp_status status);
+void fspm_display_upd_values(const struct FSPM_UPD *old,
+ const struct FSPM_UPD *new);
+
+/* Callbacks for displaying UPD parameters - place in a separate file
+ * that is conditionally build with CONFIG_DISPLAY_UPD_DATA.
+ */
+void soc_display_fspm_upd_params(const struct FSPM_UPD *fspm_old_upd,
+ const struct FSPM_UPD *fspm_new_upd);
+void soc_display_fsps_upd_params(const struct FSPS_UPD *fsps_old_upd,
+ const struct FSPS_UPD *fsps_new_upd);
+
+/* FSP debug utility functions */
+void fsp_display_upd_value(const char *name, size_t size, uint64_t old,
+ uint64_t new);
#endif /* _FSP2_0_DEBUG_H_ */
diff --git a/src/drivers/intel/fsp2_0/upd_display.c b/src/drivers/intel/fsp2_0/upd_display.c
new file mode 100644
index 0000000..694a66e
--- /dev/null
+++ b/src/drivers/intel/fsp2_0/upd_display.c
@@ -0,0 +1,76 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2016 Intel Corp.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+#include <arch/cpu.h>
+#include <console/console.h>
+#include <fsp/util.h>
+#include <lib.h>
+
+void fsp_display_upd_value(const char *name, size_t size, uint64_t old,
+ uint64_t new)
+{
+ size *= 2;
+ if (old == new) {
+ printk(BIOS_SPEW, " 0x%0*llx: %s\n", size, new, name);
+ } else {
+ printk(BIOS_SPEW, " 0x%0*llx --> 0x%0*llx: %s\n", size, old,
+ size, new, name);
+ }
+}
+
+static void fspm_display_arch_params(const struct FSPM_ARCH_UPD *old,
+ const struct FSPM_ARCH_UPD *new)
+{
+ /* Display the architectural parameters for MemoryInit */
+ printk(BIOS_SPEW, "Architectural UPD values for MemoryInit at: 0x%p\n",
+ new);
+ fsp_display_upd_value("Revision", sizeof(old->Revision),
+ old->Revision, new->Revision);
+ fsp_display_upd_value("NvsBufferPtr", sizeof(old->NvsBufferPtr),
+ (uintptr_t)old->NvsBufferPtr,
+ (uintptr_t)new->NvsBufferPtr);
+ fsp_display_upd_value("StackBase", sizeof(old->StackBase),
+ (uintptr_t)old->StackBase,
+ (uintptr_t)new->StackBase);
+ fsp_display_upd_value("StackSize", sizeof(old->StackSize),
+ old->StackSize, new->StackSize);
+ fsp_display_upd_value("BootLoaderTolumSize",
+ sizeof(old->BootLoaderTolumSize),
+ old->BootLoaderTolumSize, new->BootLoaderTolumSize);
+ fsp_display_upd_value("BootMode", sizeof(old->BootMode),
+ old->BootMode, new->BootMode);
+}
+
+/* Display the UPD parameters for MemoryInit */
+__attribute__((weak)) void soc_display_fspm_upd_params(
+ const struct FSPM_UPD *fspm_old_upd,
+ const struct FSPM_UPD *fspm_new_upd)
+{
+ printk(BIOS_SPEW, "UPD values for MemoryInit:\n");
+ hexdump(fspm_new_upd, sizeof(*fspm_new_upd));
+}
+
+void fspm_display_upd_values(const struct FSPM_UPD *old,
+ const struct FSPM_UPD *new)
+{
+ /* Display the UPD data */
+ fspm_display_arch_params(&old->FspmArchUpd, &new->FspmArchUpd);
+ soc_display_fspm_upd_params(old, new);
+}
+
+/* Display the UPD parameters for SiliconInit */
+__attribute__((weak)) void soc_display_fsps_upd_params(
+ const struct FSPS_UPD *fsps_old_upd,
+ const struct FSPS_UPD *fsps_new_upd)
+{
+ printk(BIOS_SPEW, "UPD values for SiliconInit:\n");
+ hexdump(fsps_new_upd, sizeof(*fsps_new_upd));
+}
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