[coreboot-gerrit] Patch set updated for coreboot: skylake/devicetree: Add PIRQ Routing programming

[Barnali Sarkar (barnali.sarkar@intel.com)]

Barnali Sarkar (barnali.sarkar at intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16044

-gerrit

commit 1ccb5e872a407c6b5515fda47557bdd1febf3a39
Author: Barnali Sarkar <barnali.sarkar at intel.com>
Date:   Wed Aug 3 12:15:22 2016 +0530

    skylake/devicetree: Add PIRQ Routing programming
    
    Program PIRQ Routing with correct values, as done by FSP, and in
    'soc/intel/skylake/romstage/pch.c' file. If not done, these values get
    overridden by "0" during PxRC -> PIRQ programming in ramstage, in
    'soc/intel/skylake/lpc.c' files pch_pirq_init()function.
    
    BUG=none
    BRANCH=none
    TEST=Build and boot kunimitsu
    
    Change-Id: Ibeb9a64824a71c253e45d6a1c6088abd737cf046
    Signed-off-by: Barnali Sarkar <barnali.sarkar at intel.com>
---
 src/mainboard/google/chell/devicetree.cb    | 9 +++++++++
 src/mainboard/google/glados/devicetree.cb   | 9 +++++++++
 src/mainboard/google/lars/devicetree.cb     | 9 +++++++++
 src/mainboard/intel/kunimitsu/devicetree.cb | 9 +++++++++
 4 files changed, 36 insertions(+)

diff --git a/src/mainboard/google/chell/devicetree.cb b/src/mainboard/google/chell/devicetree.cb
index 3f40449..c0ab98f 100644
--- a/src/mainboard/google/chell/devicetree.cb
+++ b/src/mainboard/google/chell/devicetree.cb
@@ -56,6 +56,15 @@ chip soc/intel/skylake
 	register "PmConfigSlpAMinAssert" = "3"         # 2s
 	register "PmTimerDisabled" = "1"
 
+	register "pirqa_routing" = "0xb"
+	register "pirqb_routing" = "0xa"
+	register "pirqc_routing" = "0xb"
+	register "pirqd_routing" = "0xb"
+	register "pirqe_routing" = "0xb"
+	register "pirqf_routing" = "0xb"
+	register "pirqg_routing" = "0xb"
+	register "pirqh_routing" = "0xb"
+
 	# VR Settings Configuration for 5 Domains
 	#+----------------+-------+-------+-------------+-------------+-------+
 	#| Domain/Setting |  SA   |  IA   | Ring Sliced | GT Unsliced |  GT   |
diff --git a/src/mainboard/google/glados/devicetree.cb b/src/mainboard/google/glados/devicetree.cb
index c315cd9..c7baa05 100644
--- a/src/mainboard/google/glados/devicetree.cb
+++ b/src/mainboard/google/glados/devicetree.cb
@@ -56,6 +56,15 @@ chip soc/intel/skylake
 	register "PmConfigSlpAMinAssert" = "3"         # 2s
 	register "PmTimerDisabled" = "1"
 
+	register "pirqa_routing" = "0xb"
+	register "pirqb_routing" = "0xa"
+	register "pirqc_routing" = "0xb"
+	register "pirqd_routing" = "0xb"
+	register "pirqe_routing" = "0xb"
+	register "pirqf_routing" = "0xb"
+	register "pirqg_routing" = "0xb"
+	register "pirqh_routing" = "0xb"
+
 	# VR Settings Configuration for 5 Domains
 	#+----------------+-------+-------+-------------+-------------+-------+
 	#| Domain/Setting |  SA   |  IA   | Ring Sliced | GT Unsliced |  GT   |
diff --git a/src/mainboard/google/lars/devicetree.cb b/src/mainboard/google/lars/devicetree.cb
index e411ad4..80f7978 100644
--- a/src/mainboard/google/lars/devicetree.cb
+++ b/src/mainboard/google/lars/devicetree.cb
@@ -38,6 +38,15 @@ chip soc/intel/skylake
 	register "FspSkipMpInit" = "1"
 	register "PmTimerDisabled" = "1"
 
+	register "pirqa_routing" = "0xb"
+	register "pirqb_routing" = "0xa"
+	register "pirqc_routing" = "0xb"
+	register "pirqd_routing" = "0xb"
+	register "pirqe_routing" = "0xb"
+	register "pirqf_routing" = "0xb"
+	register "pirqg_routing" = "0xb"
+	register "pirqh_routing" = "0xb"
+
 	# Enabling SLP_S3#, SLP_S4#, SLP_SUS and SLP_A Stretch
 	# SLP_S3 Minimum Assertion Width. Values 0: 60us, 1: 1ms, 2: 50ms, 3: 2s
 	register "PmConfigSlpS3MinAssert" = "0x02"
diff --git a/src/mainboard/intel/kunimitsu/devicetree.cb b/src/mainboard/intel/kunimitsu/devicetree.cb
index 07efd54..9638a37 100644
--- a/src/mainboard/intel/kunimitsu/devicetree.cb
+++ b/src/mainboard/intel/kunimitsu/devicetree.cb
@@ -37,6 +37,15 @@ chip soc/intel/skylake
 	register "SaGv" = "3"
 	register "PmTimerDisabled" = "1"
 
+	register "pirqa_routing" = "0xb"
+	register "pirqb_routing" = "0xa"
+	register "pirqc_routing" = "0xb"
+	register "pirqd_routing" = "0xb"
+	register "pirqe_routing" = "0xb"
+	register "pirqf_routing" = "0xb"
+	register "pirqg_routing" = "0xb"
+	register "pirqh_routing" = "0xb"
+
 	# Enabling SLP_S3#, SLP_S4#, SLP_SUS and SLP_A Stretch
 	# SLP_S3 Minimum Assertion Width. Values 0: 60us, 1: 1ms, 2: 50ms, 3: 2s
 	register "PmConfigSlpS3MinAssert" = "0x02"