[coreboot-gerrit] New patch to review for coreboot: google/reef: Configure SDIO D1 to enable SCS Power Gating

[Jagadish Krishnamoorthy (jagadish.krishnamoorthy@intel.com)]

Jagadish Krishnamoorthy (jagadish.krishnamoorthy at intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16062

-gerrit

commit 1dfbbf4226c3debf436cad8a6b660270f84f7879
Author: Jagadish Krishnamoorthy <jagadish.krishnamoorthy at intel.com>
Date:   Thu Aug 4 10:17:22 2016 -0700

    google/reef: Configure SDIO D1 to enable SCS Power Gating
    
    SDIO D1 pin needs to be configured as Native mode to
    enable SCS Power Gating.
    
    BUG=chrome-os-partner:54251
    TEST=Verify SCS Power Gating
    
    Change-Id: Ic33b26443203217678e11d195eb965a7e628ad82
    Signed-off-by: Jagadish Krishnamoorthy <jagadish.krishnamoorthy at intel.com>
---
 src/mainboard/google/reef/gpio.h | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/src/mainboard/google/reef/gpio.h b/src/mainboard/google/reef/gpio.h
index 969b392..0b906ef 100644
--- a/src/mainboard/google/reef/gpio.h
+++ b/src/mainboard/google/reef/gpio.h
@@ -53,7 +53,8 @@ static const struct pad_config gpio_table[] = {
 	/* SDIO -- unused. */
 	PAD_CFG_GPI(GPIO_166, UP_20K, DEEP),	 /* SDIO_CLK */
 	PAD_CFG_GPI(GPIO_167, UP_20K, DEEP),	 /* SDIO_D0 */
-	PAD_CFG_GPI(GPIO_168, UP_20K, DEEP),	 /* SDIO_D1 */
+	/* Configure SDIO to enable power gating */
+	PAD_CFG_NF(GPIO_168, UP_20K, DEEP, NF1), /* SDIO_D1 */
 	PAD_CFG_GPI(GPIO_169, UP_20K, DEEP),	 /* SDIO_D2 */
 	PAD_CFG_GPI(GPIO_170, UP_20K, DEEP),	 /* SDIO_D3 */
 	PAD_CFG_GPI(GPIO_171, UP_20K, DEEP),	 /* SDIO_CMD */