[coreboot-gerrit] New patch to review for coreboot: soc/intel/apollolake: ASL methods for eMMC
Vaibhav Shankar (vaibhav.shankar@intel.com)
gerrit at coreboot.org
Tue Aug 16 21:45:55 CEST 2016
Vaibhav Shankar (vaibhav.shankar at intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16233
-gerrit
commit b3047f930b32d7de6a83a80e8687e4b8276c7dcf
Author: vaibhav <vaibhav.shankar at intel.com>
Date: Mon Aug 15 11:32:26 2016 -0700
soc/intel/apollolake: ASL methods for eMMC
PS0 and PS3 methods implemented to support eMMC power gate
in S0ix suspend and resume.
Signed-off-by: vaibhav <vaibhav.shankar at intel.com>
Change-Id: Ia974e9ed67ee520d16f6d6a60294bc62a120fd76
---
src/soc/intel/apollolake/acpi/scs.asl | 103 ++++++++++++++++++++++++++
src/soc/intel/apollolake/acpi/southbridge.asl | 4 +
2 files changed, 107 insertions(+)
diff --git a/src/soc/intel/apollolake/acpi/scs.asl b/src/soc/intel/apollolake/acpi/scs.asl
new file mode 100644
index 0000000..32bed29
--- /dev/null
+++ b/src/soc/intel/apollolake/acpi/scs.asl
@@ -0,0 +1,103 @@
+/**************************************************************************;
+;* *;
+;* Intel Confidential *;
+;* *;
+;* Intel Corporation - ACPI Reference Code for the Broxton *;
+;* Family of Customer Reference Boards. *;
+;* *;
+;* *;
+;* Copyright (c) 2012 - 2016 Intel Corporation. All rights reserved *;
+;* This software and associated documentation (if any) is furnished *;
+;* under a license and may only be used or copied in accordance *;
+;* with the terms of the license. Except as permitted by such *;
+;* license, no part of this software or documentation may be *;
+;* reproduced, stored in a retrieval system, or transmitted in any *;
+;* form or by any means without the express written consent of *;
+;* Intel Corporation. *;
+;* *;
+;* *;
+;**************************************************************************/
+/*++
+ This file contains an 'Intel Peripheral Driver' and is
+ licensed for Intel CPUs and chipsets under the terms of your
+ license agreement with Intel or your vendor. This file may
+ be modified by the user, subject to additional terms of the
+ license agreement
+--*/
+scope (\_SB.PCI0) {
+
+ OperationRegion (SBMM, SystemMemory, OR( OR (CONFIG_IOSF_BASE_ADDRESS,
+ ShiftLeft(0xD6, 16)), 0x0600), 0x18)
+ Field (SBMM, DWordAcc, NoLock, Preserve)
+ {
+ Offset (0x00),
+ GENR, 32,
+ Offset (0x08),
+ , 5,
+ GRR3, 1,
+ }
+
+ //
+ // SCC power gate control method, this method must be serialized as multiple
+ // device will control
+ //the GENR register
+ //
+ // Arguments: (2)
+ // Arg0: 0-AND 1-OR
+ // Arg1: Value
+ Method (SCPG, 2, Serialized)
+ {
+ Name (TMP, 0x0)
+ if (LEqual(Arg0, 0x1)) {
+ Store (\_SB.PCI0.GENR, TMP)
+ Or (TMP, Arg1, \_SB.PCI0.GENR)
+
+ } ElseIf(LEqual(Arg0, 0x0)) {
+ Store (\_SB.PCI0.GENR, TMP)
+ And (TMP, Arg1, \_SB.PCI0.GENR)
+ }
+ }
+
+ //
+ // eMMC
+ //
+ Device(SDHA) {
+ Name (_ADR, 0x001C0000)
+ Name (_DDN, "Intel(R) eMMC Controller - 80865ACC")
+ Name (_UID, 1)
+ //Method for port80 debug
+ OperationRegion (POST, SystemIO, 0x80, 1)
+ Field (POST, ByteAcc, Lock, Preserve)
+ {
+ DBG0, 8
+ }
+
+ Method (_PS0, 0, NotSerialized) // _PS0: Power State 0
+ {
+ // To enable port 80 debug
+ // Store(0xB1, DBG0)
+
+ // Clear clock gate
+ \_SB.PCI0.SCPG(0,0xFFFFFFBE) // Clear bit 6 and 0
+ Sleep (2) // Sleep 2 ms
+ // To enable port 80 debug
+ // Store(0xB2, DBG0)
+ }
+
+ Method (_PS3, 0, NotSerialized) // _PS3: Power State 3
+ {
+ //
+ // Enable power gate
+ // To enable port 80 debug
+ // Store(0xB3, DBG0)
+
+ // Restore clock gate
+ \_SB.PCI0.SCPG(1,0x00000041) // restore bit 6 and 0
+
+ // To enable port 80 debug
+ //Store(0xB4, DBG0)
+ }
+
+ } // Device(SDHA)
+
+}
diff --git a/src/soc/intel/apollolake/acpi/southbridge.asl b/src/soc/intel/apollolake/acpi/southbridge.asl
index 5b29abb..75b681c 100644
--- a/src/soc/intel/apollolake/acpi/southbridge.asl
+++ b/src/soc/intel/apollolake/acpi/southbridge.asl
@@ -31,5 +31,9 @@
/* LPC */
#include "lpc.asl"
+/* eMMC */
+#include "scs.asl"
+
+
/* PCI _OSC */
#include <soc/intel/common/acpi/pci_osc.asl>
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