[coreboot-gerrit] Patch set updated for coreboot: soc/intel/apollolake: Save DIMM info from SMBIOS memory HOB
Ravishankar Sarawadi (ravishankar.sarawadi@intel.com)
gerrit at coreboot.org
Wed Aug 17 23:06:58 CEST 2016
Ravishankar Sarawadi (ravishankar.sarawadi at intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16238
-gerrit
commit 9ee0c937c83b00cbf94dfd7fe0b9522b1ef8efb5
Author: Ravi Sarawadi <ravishankar.sarawadi at intel.com>
Date: Tue Aug 16 16:55:02 2016 -0700
soc/intel/apollolake: Save DIMM info from SMBIOS memory HOB
Read FSP produced memory HOB and use it to populate DIMM info.
DIMM 'part_num' info is stored statically based on memory/SKU id.
BUG = chrome-os-partner:55505
Test = 'dmidecode -t 17' and 'mosys -k memory spd print all'
Change-Id: I7fa4fe6f99d4b3d68aaf10245af8484f7051aa25
Signed-off-by: Ravi Sarawadi <ravishankar.sarawadi at intel.com>
---
src/drivers/intel/fsp2_0/hand_off_block.c | 14 ++-
src/drivers/intel/fsp2_0/include/fsp/util.h | 1 +
src/mainboard/google/reef/romstage.c | 111 +++++++++++++++++++++++-
src/soc/intel/apollolake/include/soc/meminit.h | 1 +
src/soc/intel/apollolake/include/soc/romstage.h | 1 +
src/soc/intel/apollolake/romstage.c | 8 ++
6 files changed, 131 insertions(+), 5 deletions(-)
diff --git a/src/drivers/intel/fsp2_0/hand_off_block.c b/src/drivers/intel/fsp2_0/hand_off_block.c
index 0dd4a52..17adf46 100644
--- a/src/drivers/intel/fsp2_0/hand_off_block.c
+++ b/src/drivers/intel/fsp2_0/hand_off_block.c
@@ -45,8 +45,13 @@ const uint8_t fsp_reserved_memory_guid[16] = {
};
const uint8_t fsp_nv_storage_guid[16] = {
- 0x02, 0xcf, 0x1a, 0x72, 0x77, 0x4d, 0x2a, 0x4c,
- 0xb3, 0xdc, 0x27, 0x0b, 0x7b, 0xa9, 0xe4, 0xb0
+ 0x02, 0xcf, 0x1a, 0x72, 0x77, 0x4d, 0x2a, 0x4c,
+ 0xb3, 0xdc, 0x27, 0x0b, 0x7b, 0xa9, 0xe4, 0xb0
+};
+
+const uint8_t smbios_memory_info_guid[16] = {
+ 0x8c, 0x10, 0xa1, 0x01, 0xee, 0x9d, 0x84, 0x49,
+ 0x88, 0xc3, 0xee, 0xe8, 0xc4, 0x9e, 0xfb, 0x89
};
/*
@@ -218,3 +223,8 @@ const void *fsp_find_nv_storage_data(size_t *size)
{
return fsp_find_extension_hob_by_guid(fsp_nv_storage_guid, size);
}
+
+const void *fsp_find_smbios_memory_info(size_t *size)
+{
+ return fsp_find_extension_hob_by_guid(smbios_memory_info_guid, size);
+}
diff --git a/src/drivers/intel/fsp2_0/include/fsp/util.h b/src/drivers/intel/fsp2_0/include/fsp/util.h
index ba465ea..269bb02 100644
--- a/src/drivers/intel/fsp2_0/include/fsp/util.h
+++ b/src/drivers/intel/fsp2_0/include/fsp/util.h
@@ -61,6 +61,7 @@ const void *fsp_get_hob_list(void);
void *fsp_get_hob_list_ptr(void);
const void *fsp_find_extension_hob_by_guid(const uint8_t *guid, size_t *size);
const void *fsp_find_nv_storage_data(size_t *size);
+const void *fsp_find_smbios_memory_info(size_t *size);
enum cb_err fsp_fill_lb_framebuffer(struct lb_framebuffer *framebuffer);
int fsp_find_range_hob(struct range_entry *re, const uint8_t guid[16]);
int fsp_find_reserved_memory(struct range_entry *re);
diff --git a/src/mainboard/google/reef/romstage.c b/src/mainboard/google/reef/romstage.c
index f9743b5..e9a2bfc 100644
--- a/src/mainboard/google/reef/romstage.c
+++ b/src/mainboard/google/reef/romstage.c
@@ -13,9 +13,16 @@
* GNU General Public License for more details.
*/
+#include <cbmem.h>
+#include <console/console.h>
+#include <fsp/util.h>
#include <gpio.h>
+#include <memory_info.h>
+#include <smbios.h>
+#include <soc/fsp/FspmUpd.h>
#include <soc/meminit.h>
#include <soc/romstage.h>
+#include <string.h>
#include "gpio.h"
static const struct lpddr4_swizzle_cfg board_swizzle = {
@@ -82,12 +89,14 @@ static const struct lpddr4_sku skus[] = {
.ch1_rank_density = LP4_8Gb_DENSITY,
.ch0_dual_rank = 1,
.ch1_dual_rank = 1,
+ .part_num = "K4F6E304HB-MGCJ",
},
/* K4F8E304HB-MGCJ - both logical channels */
[1] = {
.speed = LP4_SPEED_2400,
.ch0_rank_density = LP4_8Gb_DENSITY,
.ch1_rank_density = LP4_8Gb_DENSITY,
+ .part_num = "K4F8E304HB-MGCJ",
},
/*
* MT53B512M32D2NP-062WT:C - both logical channels. While the parts
@@ -100,18 +109,21 @@ static const struct lpddr4_sku skus[] = {
.ch1_rank_density = LP4_8Gb_DENSITY,
.ch0_dual_rank = 1,
.ch1_dual_rank = 1,
+ .part_num = "MT53B512M32D2NP",
},
/* MT53B256M32D1NP-062 WT:C - both logical channels */
[3] = {
.speed = LP4_SPEED_2400,
.ch0_rank_density = LP4_8Gb_DENSITY,
.ch1_rank_density = LP4_8Gb_DENSITY,
+ .part_num = "MT53B256M32D1NP",
},
/* K4F8E304HB-MGCH - both logical channels */
[PROTO_SKU] = {
.speed = LP4_SPEED_2400,
.ch0_rank_density = LP4_8Gb_DENSITY,
.ch1_rank_density = LP4_8Gb_DENSITY,
+ .part_num = "K4F8E304HB-MGCH",
},
};
@@ -121,9 +133,8 @@ static const struct lpddr4_cfg lp4cfg = {
.swizzle_config = &board_swizzle,
};
-void mainboard_memory_init_params(struct FSPM_UPD *memupd)
+static int get_mem_sku(void)
{
- int mem_sku;
gpio_t pads[] = {
[3] = MEM_CONFIG3, [2] = MEM_CONFIG2,
[1] = MEM_CONFIG1, [0] = MEM_CONFIG0,
@@ -133,7 +144,101 @@ void mainboard_memory_init_params(struct FSPM_UPD *memupd)
* Read memory SKU id with internal pullups enabled to handle
* proto boards with no SKU id pins.
*/
- mem_sku = gpio_pullup_base2_value(pads, ARRAY_SIZE(pads));
+ return gpio_pullup_base2_value(pads, ARRAY_SIZE(pads));
+}
+
+void mainboard_memory_init_params(struct FSPM_UPD *memupd)
+{
+ int mem_sku = get_mem_sku();
meminit_lpddr4_by_sku(&memupd->FspmConfig, &lp4cfg, mem_sku);
}
+
+void mainboard_save_dimm_info(void)
+{
+ int channel, dimm, dimm_max, index, mem_sku;
+ size_t hob_size;
+ struct DIMM_INFO *dimm_info;
+ struct memory_info *mem_info;
+ struct CHANNEL_INFO *channel_info;
+ struct FSP_SMBIOS_MEMORY_INFO *memory_info_hob;
+
+ mem_sku = get_mem_sku();
+ if (mem_sku >= lp4cfg.num_skus) {
+ printk(BIOS_ERR, "Too few LPDDR4 SKUs: 0x%zx/0x%zx\n",
+ mem_sku, lp4cfg.num_skus);
+ return;
+ }
+
+ memory_info_hob = (struct FSP_SMBIOS_MEMORY_INFO *)
+ fsp_find_smbios_memory_info(&hob_size);
+
+ /*
+ * Allocate CBMEM area for DIMM information used to populate SMBIOS
+ * table 17
+ */
+ mem_info = cbmem_add(CBMEM_ID_MEMINFO, sizeof(*mem_info));
+ printk(BIOS_DEBUG, "CBMEM entry for DIMM info: 0x%p\n", mem_info);
+ if (mem_info == NULL)
+ return;
+ memset(mem_info, 0, sizeof(*mem_info));
+
+ /* Describe the first N DIMMs in the system */
+ index = 0;
+ dimm_max = ARRAY_SIZE(mem_info->dimm);
+ for (channel = 0; channel < memory_info_hob->ChannelCount; channel++) {
+ if (index >= dimm_max)
+ break;
+ channel_info = &memory_info_hob->ChannelInfo[channel];
+ for (dimm = 0; dimm < channel_info->DimmCount; dimm++) {
+ if (index >= dimm_max)
+ break;
+ dimm_info = &channel_info->DimmInfo[dimm];
+
+ /* Populate the DIMM information */
+ if (dimm_info->SizeInMb) {
+ mem_info->dimm[index].dimm_size =
+ dimm_info->SizeInMb;
+ mem_info->dimm[index].ddr_type =
+ memory_info_hob->MemoryType;
+ mem_info->dimm[index].ddr_frequency =
+ memory_info_hob->MemoryFrequencyInMHz;
+ mem_info->dimm[index].channel_num =
+ channel_info->ChannelId;
+ mem_info->dimm[index].dimm_num =
+ dimm_info->DimmId;
+ memcpy(mem_info->dimm[index].module_part_number,
+ lp4cfg.skus[mem_sku].part_num,
+ sizeof(mem_info->dimm[index].module_part_number));
+
+ switch (memory_info_hob->DataWidth) {
+ case 8:
+ mem_info->dimm[index].bus_width = MEMORY_BUS_WIDTH_8;
+ break;
+
+ case 16:
+ mem_info->dimm[index].bus_width = MEMORY_BUS_WIDTH_16;
+ break;
+
+ case 32:
+ mem_info->dimm[index].bus_width = MEMORY_BUS_WIDTH_32;
+ break;
+
+ case 64:
+ mem_info->dimm[index].bus_width = MEMORY_BUS_WIDTH_64;
+ break;
+
+ case 128:
+ mem_info->dimm[index].bus_width = MEMORY_BUS_WIDTH_128;
+ break;
+
+ default:
+ printk(BIOS_ERR, "Incorrect DIMM Data Width");
+ }
+ index++;
+ }
+ }
+ }
+ mem_info->dimm_cnt = index;
+ printk(BIOS_DEBUG, "%d DIMMs found\n", mem_info->dimm_cnt);
+}
diff --git a/src/soc/intel/apollolake/include/soc/meminit.h b/src/soc/intel/apollolake/include/soc/meminit.h
index a7da1ac..037e7f4 100644
--- a/src/soc/intel/apollolake/include/soc/meminit.h
+++ b/src/soc/intel/apollolake/include/soc/meminit.h
@@ -101,6 +101,7 @@ struct lpddr4_sku {
int ch1_rank_density;
int ch0_dual_rank;
int ch1_dual_rank;
+ const char *part_num;
};
struct lpddr4_cfg {
diff --git a/src/soc/intel/apollolake/include/soc/romstage.h b/src/soc/intel/apollolake/include/soc/romstage.h
index e7ee335..5b76f65 100644
--- a/src/soc/intel/apollolake/include/soc/romstage.h
+++ b/src/soc/intel/apollolake/include/soc/romstage.h
@@ -22,5 +22,6 @@
#include <fsp/api.h>
void mainboard_memory_init_params(struct FSPM_UPD *mupd);
+void mainboard_save_dimm_info(void);
#endif /* _SOC_APOLLOLAKE_ROMSTAGE_H_ */
diff --git a/src/soc/intel/apollolake/romstage.c b/src/soc/intel/apollolake/romstage.c
index 8f17fdd..d631192 100644
--- a/src/soc/intel/apollolake/romstage.c
+++ b/src/soc/intel/apollolake/romstage.c
@@ -118,6 +118,8 @@ asmlinkage void car_stage_entry(void)
if (postcar_frame_init(&pcf, 1*KiB))
die("Unable to initialize postcar frame.\n");
+ mainboard_save_dimm_info();
+
/*
* We need to make sure ramstage will be run cached. At this point exact
* location of ramstage in cbmem is not known. Instruct postcar to cache
@@ -169,6 +171,12 @@ void mainboard_memory_init_params(struct FSPM_UPD *mupd)
printk(BIOS_DEBUG, "WEAK: %s/%s called\n", __FILE__, __func__);
}
+__attribute__ ((weak))
+void mainboard_save_dimm_info(void)
+{
+ printk(BIOS_DEBUG, "WEAK: %s/%s called\n", __FILE__, __func__);
+}
+
int get_sw_write_protect_state(void)
{
uint8_t status;
More information about the coreboot-gerrit
mailing list