[coreboot-gerrit] Patch merged into coreboot/master: skylake: Do FspTempRamInit only for FSP1.1 & tidy up PCH early init

[gerrit at coreboot.org]

the following patch was just integrated into master:
commit cf73c1317dd1ab62a96eb17ed6d9c8590fb4c514
Author: Rizwan Qureshi <rizwan.qureshi at intel.com>
Date:   Thu Aug 4 20:01:12 2016 +0530

    skylake: Do FspTempRamInit only for FSP1.1 & tidy up PCH early init
    
    Prepare Skylake for FSP2.0 support.
    
    We do not use FSP-T in FSP2.0 driver, hence guard the
    FspTempRamInit call under a switch.
    
    In addition to the current early PCH configuration
    program few more register, so all in all we do the following,
    * Program and enable ACPI Base.
    * Program and enable PWRM Base.
    * Program TCO Base.
    * Program Interrupt configuration registers.
    * Program LPC IO decode range.
    * Program SMBUS Base address and enable it.
    * Enable upper 128 bytes of CMOS.
    And split the above programming into into smaller functions.
    
    Also, as part of bootblock_pch_early_init we enable decoding
    for HPET range. This is needed for FspMemoryInit to store and
    retrieve a global data pointer.
    
    And also move P2SB related definitions to a new header file.
    
    TEST=Build and boot Kunimitsu
    
    Change-Id: Ia201e03b745836ebb43b8d7cfc77550105c71d16
    Signed-off-by: Rizwan Qureshi <rizwan.qureshi at intel.com>
    Signed-off-by: Barnali Sarkar <barnali.sarkar at intel.com>
    Reviewed-on: https://review.coreboot.org/16113
    Tested-by: build bot (Jenkins)
    Reviewed-by: Martin Roth <martinroth at google.com>


See https://review.coreboot.org/16113 for details.

-gerrit