[coreboot-gerrit] Patch set updated for coreboot: soc/intel/apollolake: Save DIMM info from SMBIOS memory HOB
Ravishankar Sarawadi (ravishankar.sarawadi@intel.com)
gerrit at coreboot.org
Thu Aug 18 22:28:21 CEST 2016
Ravishankar Sarawadi (ravishankar.sarawadi at intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16246
-gerrit
commit 8df062f0c63e8542353617110dbb24e69b4f53eb
Author: Ravi Sarawadi <ravishankar.sarawadi at intel.com>
Date: Wed Aug 17 23:44:56 2016 -0700
soc/intel/apollolake: Save DIMM info from SMBIOS memory HOB
Read FSP produced memory HOB and use it to populate DIMM info.
DIMM 'part_num' info is stored statically based on memory/SKU id.
CQ-DEPEND=CL:16245
BUG = chrome-os-partner:55505
TEST = 'dmidecode -t 17' and 'mosys -k memory spd print all'
Change-Id: Ifcbb3329fd4414bba90eb584e065b1cb7f120e73
Signed-off-by: Ravi Sarawadi <ravishankar.sarawadi at intel.com>
---
src/mainboard/google/reef/romstage.c | 23 ++++++-
src/soc/intel/apollolake/include/soc/meminit.h | 2 +
src/soc/intel/apollolake/include/soc/romstage.h | 1 +
src/soc/intel/apollolake/meminit.c | 88 ++++++++++++++++++++++++-
src/soc/intel/apollolake/romstage.c | 8 +++
5 files changed, 118 insertions(+), 4 deletions(-)
diff --git a/src/mainboard/google/reef/romstage.c b/src/mainboard/google/reef/romstage.c
index f9743b5..99eb69c 100644
--- a/src/mainboard/google/reef/romstage.c
+++ b/src/mainboard/google/reef/romstage.c
@@ -16,6 +16,7 @@
#include <gpio.h>
#include <soc/meminit.h>
#include <soc/romstage.h>
+
#include "gpio.h"
static const struct lpddr4_swizzle_cfg board_swizzle = {
@@ -82,12 +83,14 @@ static const struct lpddr4_sku skus[] = {
.ch1_rank_density = LP4_8Gb_DENSITY,
.ch0_dual_rank = 1,
.ch1_dual_rank = 1,
+ .part_num = "K4F6E304HB-MGCJ",
},
/* K4F8E304HB-MGCJ - both logical channels */
[1] = {
.speed = LP4_SPEED_2400,
.ch0_rank_density = LP4_8Gb_DENSITY,
.ch1_rank_density = LP4_8Gb_DENSITY,
+ .part_num = "K4F8E304HB-MGCJ",
},
/*
* MT53B512M32D2NP-062WT:C - both logical channels. While the parts
@@ -100,18 +103,21 @@ static const struct lpddr4_sku skus[] = {
.ch1_rank_density = LP4_8Gb_DENSITY,
.ch0_dual_rank = 1,
.ch1_dual_rank = 1,
+ .part_num = "MT53B512M32D2NP",
},
/* MT53B256M32D1NP-062 WT:C - both logical channels */
[3] = {
.speed = LP4_SPEED_2400,
.ch0_rank_density = LP4_8Gb_DENSITY,
.ch1_rank_density = LP4_8Gb_DENSITY,
+ .part_num = "MT53B256M32D1NP",
},
/* K4F8E304HB-MGCH - both logical channels */
[PROTO_SKU] = {
.speed = LP4_SPEED_2400,
.ch0_rank_density = LP4_8Gb_DENSITY,
.ch1_rank_density = LP4_8Gb_DENSITY,
+ .part_num = "K4F8E304HB-MGCH",
},
};
@@ -121,9 +127,8 @@ static const struct lpddr4_cfg lp4cfg = {
.swizzle_config = &board_swizzle,
};
-void mainboard_memory_init_params(struct FSPM_UPD *memupd)
+static int get_mem_sku(void)
{
- int mem_sku;
gpio_t pads[] = {
[3] = MEM_CONFIG3, [2] = MEM_CONFIG2,
[1] = MEM_CONFIG1, [0] = MEM_CONFIG0,
@@ -133,7 +138,19 @@ void mainboard_memory_init_params(struct FSPM_UPD *memupd)
* Read memory SKU id with internal pullups enabled to handle
* proto boards with no SKU id pins.
*/
- mem_sku = gpio_pullup_base2_value(pads, ARRAY_SIZE(pads));
+ return gpio_pullup_base2_value(pads, ARRAY_SIZE(pads));
+}
+
+void mainboard_memory_init_params(struct FSPM_UPD *memupd)
+{
+ int mem_sku = get_mem_sku();
meminit_lpddr4_by_sku(&memupd->FspmConfig, &lp4cfg, mem_sku);
}
+
+void mainboard_save_dimm_info(void)
+{
+ int mem_sku = get_mem_sku();
+
+ save_lpddr4_dimm_info(&lp4cfg, mem_sku);
+}
diff --git a/src/soc/intel/apollolake/include/soc/meminit.h b/src/soc/intel/apollolake/include/soc/meminit.h
index a7da1ac..c115c4a 100644
--- a/src/soc/intel/apollolake/include/soc/meminit.h
+++ b/src/soc/intel/apollolake/include/soc/meminit.h
@@ -101,6 +101,7 @@ struct lpddr4_sku {
int ch1_rank_density;
int ch0_dual_rank;
int ch1_dual_rank;
+ const char *part_num;
};
struct lpddr4_cfg {
@@ -115,5 +116,6 @@ struct lpddr4_cfg {
*/
void meminit_lpddr4_by_sku(struct FSP_M_CONFIG *cfg,
const struct lpddr4_cfg *lpcfg, size_t sku_id);
+void save_lpddr4_dimm_info(const struct lpddr4_cfg *lpcfg, size_t mem_sku);
#endif /* _SOC_APOLLOLAKE_MEMINIT_H_ */
diff --git a/src/soc/intel/apollolake/include/soc/romstage.h b/src/soc/intel/apollolake/include/soc/romstage.h
index e7ee335..5b76f65 100644
--- a/src/soc/intel/apollolake/include/soc/romstage.h
+++ b/src/soc/intel/apollolake/include/soc/romstage.h
@@ -22,5 +22,6 @@
#include <fsp/api.h>
void mainboard_memory_init_params(struct FSPM_UPD *mupd);
+void mainboard_save_dimm_info(void);
#endif /* _SOC_APOLLOLAKE_ROMSTAGE_H_ */
diff --git a/src/soc/intel/apollolake/meminit.c b/src/soc/intel/apollolake/meminit.c
index 92b84c8..03e9ac4 100644
--- a/src/soc/intel/apollolake/meminit.c
+++ b/src/soc/intel/apollolake/meminit.c
@@ -12,8 +12,11 @@
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
-
+#include <cbmem.h>
#include <console/console.h>
+#include <fsp/util.h>
+#include <memory_info.h>
+#include <smbios.h>
#include <soc/meminit.h>
#include <stddef.h> /* required for FspmUpd.h */
#include <soc/fsp/FspmUpd.h>
@@ -252,3 +255,86 @@ void meminit_lpddr4_by_sku(struct FSP_M_CONFIG *cfg,
lpcfg->swizzle_config);
}
}
+
+void save_lpddr4_dimm_info(const struct lpddr4_cfg *lp4cfg, size_t mem_sku)
+{
+ int channel, dimm, dimm_max, index;
+ size_t hob_size;
+ const struct DIMM_INFO *src_dimm;
+ struct dimm_info *dest_dimm;
+ struct memory_info *mem_info;
+ const struct CHANNEL_INFO *channel_info;
+ const struct FSP_SMBIOS_MEMORY_INFO *memory_info_hob;
+
+ if (mem_sku >= lp4cfg->num_skus) {
+ printk(BIOS_ERR, "Too few LPDDR4 SKUs: 0x%zx/0x%zx\n",
+ mem_sku, lp4cfg->num_skus);
+ return;
+ }
+
+ memory_info_hob = fsp_find_smbios_memory_info(&hob_size);
+
+ /*
+ * Allocate CBMEM area for DIMM information used to populate SMBIOS
+ * table 17
+ */
+ mem_info = cbmem_add(CBMEM_ID_MEMINFO, sizeof(*mem_info));
+ if (mem_info == NULL) {
+ printk(BIOS_ERR, "CBMEM entry for DIMM info missing\n");
+ return;
+ }
+ memset(mem_info, 0, sizeof(*mem_info));
+
+ /* Describe the first N DIMMs in the system */
+ index = 0;
+ dimm_max = ARRAY_SIZE(mem_info->dimm);
+ for (channel = 0; channel < memory_info_hob->ChannelCount; channel++) {
+ if (index >= dimm_max)
+ break;
+ channel_info = &memory_info_hob->ChannelInfo[channel];
+ for (dimm = 0; dimm < channel_info->DimmCount; dimm++) {
+ if (index >= dimm_max)
+ break;
+ src_dimm = &channel_info->DimmInfo[dimm];
+ dest_dimm = &mem_info->dimm[index];
+
+ if (!src_dimm->SizeInMb)
+ continue;
+
+ /* Populate the DIMM information */
+ dest_dimm->dimm_size = src_dimm->SizeInMb;
+ dest_dimm->ddr_type = memory_info_hob->MemoryType;
+ dest_dimm->ddr_frequency =
+ memory_info_hob->MemoryFrequencyInMHz;
+ dest_dimm->channel_num = channel_info->ChannelId;
+ dest_dimm->dimm_num = src_dimm->DimmId;
+ strncpy((char *)dest_dimm->module_part_number,
+ lp4cfg->skus[mem_sku].part_num,
+ sizeof(dest_dimm->module_part_number));
+
+ switch (memory_info_hob->DataWidth) {
+ case 8:
+ dest_dimm->bus_width = MEMORY_BUS_WIDTH_8;
+ break;
+ case 16:
+ dest_dimm->bus_width = MEMORY_BUS_WIDTH_16;
+ break;
+ case 32:
+ dest_dimm->bus_width = MEMORY_BUS_WIDTH_32;
+ break;
+ case 64:
+ dest_dimm->bus_width = MEMORY_BUS_WIDTH_64;
+ break;
+ case 128:
+ dest_dimm->bus_width = MEMORY_BUS_WIDTH_128;
+ break;
+ default:
+ printk(BIOS_ERR, "Incorrect DIMM Data Width");
+ }
+ index++;
+ }
+ }
+ mem_info->dimm_cnt = index;
+ printk(BIOS_DEBUG, "%d DIMMs found\n", mem_info->dimm_cnt);
+}
+
diff --git a/src/soc/intel/apollolake/romstage.c b/src/soc/intel/apollolake/romstage.c
index 8f17fdd..d631192 100644
--- a/src/soc/intel/apollolake/romstage.c
+++ b/src/soc/intel/apollolake/romstage.c
@@ -118,6 +118,8 @@ asmlinkage void car_stage_entry(void)
if (postcar_frame_init(&pcf, 1*KiB))
die("Unable to initialize postcar frame.\n");
+ mainboard_save_dimm_info();
+
/*
* We need to make sure ramstage will be run cached. At this point exact
* location of ramstage in cbmem is not known. Instruct postcar to cache
@@ -169,6 +171,12 @@ void mainboard_memory_init_params(struct FSPM_UPD *mupd)
printk(BIOS_DEBUG, "WEAK: %s/%s called\n", __FILE__, __func__);
}
+__attribute__ ((weak))
+void mainboard_save_dimm_info(void)
+{
+ printk(BIOS_DEBUG, "WEAK: %s/%s called\n", __FILE__, __func__);
+}
+
int get_sw_write_protect_state(void)
{
uint8_t status;
More information about the coreboot-gerrit
mailing list