[coreboot-gerrit] New patch to review for coreboot: src/southbridge: indent using tabs
HAOUAS Elyes (ehaouas@noos.fr)
gerrit at coreboot.org
Sun Aug 21 21:33:18 CEST 2016
HAOUAS Elyes (ehaouas at noos.fr) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16291
-gerrit
commit 3aa2ce029223851f1ff6eee73920a238285e003b
Author: Elyes HAOUAS <ehaouas at noos.fr>
Date: Sun Aug 21 19:14:31 2016 +0200
src/southbridge: indent using tabs
Change-Id: Icfc35b73bacb60b1f21e71e70ad4418ec3e644f6
Signed-off-by: Elyes HAOUAS <ehaouas at noos.fr>
---
src/southbridge/amd/amd8111/early_ctrl.c | 40 ++---
src/southbridge/amd/amd8111/ide.c | 4 +-
src/southbridge/amd/amd8111/reset.c | 20 +--
src/southbridge/amd/amd8131/bridge.c | 54 +++---
src/southbridge/amd/amd8132/bridge.c | 150 ++++++++--------
src/southbridge/amd/amd8151/agp3.c | 2 +-
src/southbridge/amd/cimx/sb800/Amd.h | 2 +-
src/southbridge/amd/cimx/sb800/early.c | 4 +-
src/southbridge/amd/cimx/sb800/late.c | 54 +++---
src/southbridge/amd/cimx/sb800/smbus.c | 8 +-
src/southbridge/amd/cimx/sb900/Amd.h | 2 +-
src/southbridge/amd/cimx/sb900/cfg.c | 4 +-
src/southbridge/amd/cimx/sb900/late.c | 98 +++++-----
src/southbridge/amd/cimx/sb900/smbus.c | 8 +-
src/southbridge/amd/cs5535/cs5535.c | 10 +-
src/southbridge/amd/rs690/gfx.c | 62 +++----
src/southbridge/amd/rs690/pcie.c | 2 +-
src/southbridge/amd/rs780/rs780.h | 2 +-
src/southbridge/amd/sb700/sm.c | 4 +-
src/southbridge/amd/sr5650/early_setup.c | 32 ++--
src/southbridge/amd/sr5650/sr5650.c | 4 +-
src/southbridge/broadcom/bcm21000/pcie.c | 2 +-
src/southbridge/broadcom/bcm5780/nic.c | 12 +-
src/southbridge/broadcom/bcm5780/pcie.c | 16 +-
src/southbridge/broadcom/bcm5780/pcix.c | 20 +--
src/southbridge/broadcom/bcm5785/bcm5785.c | 12 +-
src/southbridge/broadcom/bcm5785/chip.h | 8 +-
src/southbridge/broadcom/bcm5785/early_setup.c | 236 ++++++++++++-------------
src/southbridge/broadcom/bcm5785/early_smbus.c | 8 +-
src/southbridge/broadcom/bcm5785/ide.c | 16 +-
src/southbridge/broadcom/bcm5785/lpc.c | 20 +--
src/southbridge/broadcom/bcm5785/reset.c | 24 +--
src/southbridge/broadcom/bcm5785/sata.c | 22 +--
src/southbridge/broadcom/bcm5785/sb_pci_main.c | 96 +++++-----
src/southbridge/broadcom/bcm5785/smbus.h | 106 +++++------
src/southbridge/broadcom/bcm5785/usb.c | 8 +-
src/southbridge/intel/bd82x6x/me.c | 2 +-
src/southbridge/intel/bd82x6x/pch.h | 4 +-
src/southbridge/intel/bd82x6x/reset.c | 4 +-
src/southbridge/intel/bd82x6x/smihandler.c | 62 +++----
src/southbridge/intel/fsp_bd82x6x/me.c | 2 +-
src/southbridge/intel/fsp_bd82x6x/me_8.x.c | 4 +-
src/southbridge/intel/fsp_bd82x6x/pch.h | 4 +-
src/southbridge/intel/fsp_bd82x6x/reset.c | 4 +-
src/southbridge/intel/fsp_bd82x6x/smihandler.c | 62 +++----
src/southbridge/intel/fsp_i89xx/me.c | 2 +-
src/southbridge/intel/fsp_i89xx/me_8.x.c | 2 +-
src/southbridge/intel/fsp_i89xx/pch.h | 2 +-
src/southbridge/intel/fsp_i89xx/smihandler.c | 62 +++----
src/southbridge/intel/fsp_rangeley/lpc.c | 2 +-
src/southbridge/intel/fsp_rangeley/sata.c | 4 +-
src/southbridge/intel/fsp_rangeley/soc.h | 4 +-
src/southbridge/intel/i3100/early_smbus.c | 2 +-
src/southbridge/intel/i3100/lpc.c | 28 +--
src/southbridge/intel/i82801dx/smihandler.c | 62 +++----
src/southbridge/intel/i82801ex/lpc.c | 6 +-
src/southbridge/intel/i82801ex/reset.c | 4 +-
src/southbridge/intel/i82801ex/watchdog.c | 34 ++--
src/southbridge/intel/i82801gx/bootblock.c | 16 +-
src/southbridge/intel/i82801gx/reset.c | 6 +-
src/southbridge/intel/i82801gx/smihandler.c | 62 +++----
src/southbridge/intel/i82801ix/bootblock.c | 16 +-
src/southbridge/intel/i82870/ioapic.c | 30 ++--
src/southbridge/intel/i82870/pci_parity.c | 24 +--
src/southbridge/intel/i82870/pcibridge.c | 16 +-
src/southbridge/intel/ibexpeak/pch.h | 4 +-
src/southbridge/intel/ibexpeak/sata.c | 2 +-
src/southbridge/intel/ibexpeak/smihandler.c | 62 +++----
src/southbridge/intel/lynxpoint/early_pch.c | 2 +-
src/southbridge/intel/lynxpoint/lpc.c | 2 +-
src/southbridge/intel/lynxpoint/me_9.x.c | 4 +-
src/southbridge/intel/lynxpoint/pch.h | 4 +-
src/southbridge/intel/lynxpoint/reset.c | 4 +-
src/southbridge/intel/lynxpoint/smihandler.c | 62 +++----
src/southbridge/nvidia/ck804/early_setup_car.c | 4 +-
src/southbridge/sis/sis966/aza.c | 60 +++----
src/southbridge/sis/sis966/early_smbus.c | 90 +++++-----
src/southbridge/sis/sis966/ide.c | 32 ++--
src/southbridge/sis/sis966/lpc.c | 54 +++---
src/southbridge/sis/sis966/nic.c | 124 ++++++-------
src/southbridge/sis/sis966/sata.c | 36 ++--
src/southbridge/sis/sis966/usb.c | 26 +--
src/southbridge/sis/sis966/usb2.c | 62 +++----
src/southbridge/via/vt8237r/lpc.c | 4 +-
84 files changed, 1171 insertions(+), 1171 deletions(-)
diff --git a/src/southbridge/amd/amd8111/early_ctrl.c b/src/southbridge/amd/amd8111/early_ctrl.c
index ece99ed..d84ef18 100644
--- a/src/southbridge/amd/amd8111/early_ctrl.c
+++ b/src/southbridge/amd/amd8111/early_ctrl.c
@@ -4,16 +4,16 @@
/* by yhlu 2005.10 */
static unsigned get_sbdn(unsigned bus)
{
- device_t dev;
+ device_t dev;
- /* Find the device.
- * There can only be one 8111 on a hypertransport chain/bus.
- */
- dev = pci_locate_device_on_bus(
- PCI_ID(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8111_PCI),
- bus);
+ /* Find the device.
+ * There can only be one 8111 on a hypertransport chain/bus.
+ */
+ dev = pci_locate_device_on_bus(
+ PCI_ID(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8111_PCI),
+ bus);
- return (dev>>15) & 0x1f;
+ return (dev>>15) & 0x1f;
}
@@ -40,34 +40,34 @@ static void enable_cf9(void)
void hard_reset(void)
{
- set_bios_reset();
- /* reset */
- enable_cf9();
- outb(0x0e, 0x0cf9); // make sure cf9 is enabled
+ set_bios_reset();
+ /* reset */
+ enable_cf9();
+ outb(0x0e, 0x0cf9); // make sure cf9 is enabled
}
void enable_fid_change_on_sb(unsigned sbbusn, unsigned sbdn)
{
- device_t dev;
+ device_t dev;
dev = PCI_DEV(sbbusn, sbdn+1, 3); // ACPI
- pci_write_config8(dev, 0x74, 4);
+ pci_write_config8(dev, 0x74, 4);
- /* set VFSMAF ( VID/FID System Management Action Field) to 2 */
- pci_write_config32(dev, 0x70, 2<<12);
+ /* set VFSMAF ( VID/FID System Management Action Field) to 2 */
+ pci_write_config32(dev, 0x70, 2<<12);
}
static void soft_reset_x(unsigned sbbusn, unsigned sbdn)
{
- device_t dev;
+ device_t dev;
dev = PCI_DEV(sbbusn, sbdn+1, 0); //ISA
- /* Reset */
- set_bios_reset();
- pci_write_config8(dev, 0x47, 1);
+ /* Reset */
+ set_bios_reset();
+ pci_write_config8(dev, 0x47, 1);
}
diff --git a/src/southbridge/amd/amd8111/ide.c b/src/southbridge/amd/amd8111/ide.c
index ef0cee1..a7eee35 100644
--- a/src/southbridge/amd/amd8111/ide.c
+++ b/src/southbridge/amd/amd8111/ide.c
@@ -33,8 +33,8 @@ static void ide_init(struct device *dev)
pci_write_config16(dev, 0x40, word);
- byte = 0x20 ; // Latency: 64-->32
- pci_write_config8(dev, 0xd, byte);
+ byte = 0x20 ; // Latency: 64-->32
+ pci_write_config8(dev, 0xd, byte);
word = 0x0f;
pci_write_config16(dev, 0x42, word);
diff --git a/src/southbridge/amd/amd8111/reset.c b/src/southbridge/amd/amd8111/reset.c
index 8824550..c133c36 100644
--- a/src/southbridge/amd/amd8111/reset.c
+++ b/src/southbridge/amd/amd8111/reset.c
@@ -12,26 +12,26 @@
static void pci_write_config8(pci_devfn_t dev, unsigned where, unsigned char value)
{
- unsigned addr;
- addr = (dev>>4) | where;
- outl(0x80000000 | (addr & ~3), 0xCF8);
- outb(value, 0xCFC + (addr & 3));
+ unsigned addr;
+ addr = (dev>>4) | where;
+ outl(0x80000000 | (addr & ~3), 0xCF8);
+ outb(value, 0xCFC + (addr & 3));
}
static void pci_write_config32(pci_devfn_t dev, unsigned where, unsigned value)
{
unsigned addr;
- addr = (dev>>4) | where;
- outl(0x80000000 | (addr & ~3), 0xCF8);
- outl(value, 0xCFC);
+ addr = (dev>>4) | where;
+ outl(0x80000000 | (addr & ~3), 0xCF8);
+ outl(value, 0xCFC);
}
static unsigned pci_read_config32(pci_devfn_t dev, unsigned where)
{
unsigned addr;
- addr = (dev>>4) | where;
- outl(0x80000000 | (addr & ~3), 0xCF8);
- return inl(0xCFC);
+ addr = (dev>>4) | where;
+ outl(0x80000000 | (addr & ~3), 0xCF8);
+ return inl(0xCFC);
}
#define PCI_DEV_INVALID (0xffffffffU)
diff --git a/src/southbridge/amd/amd8131/bridge.c b/src/southbridge/amd/amd8131/bridge.c
index 1587268..6b0a03c 100644
--- a/src/southbridge/amd/amd8131/bridge.c
+++ b/src/southbridge/amd/amd8131/bridge.c
@@ -280,52 +280,52 @@ static void amd8131_pcix_init(device_t dev)
/* Enable memory write and invalidate ??? */
byte = pci_read_config8(dev, 0x04);
- byte |= 0x10;
- pci_write_config8(dev, 0x04, byte);
+ byte |= 0x10;
+ pci_write_config8(dev, 0x04, byte);
/* Set drive strength */
word = pci_read_config16(dev, 0xe0);
- word = 0x0404;
- pci_write_config16(dev, 0xe0, word);
+ word = 0x0404;
+ pci_write_config16(dev, 0xe0, word);
word = pci_read_config16(dev, 0xe4);
- word = 0x0404;
- pci_write_config16(dev, 0xe4, word);
+ word = 0x0404;
+ pci_write_config16(dev, 0xe4, word);
/* Set impedance */
word = pci_read_config16(dev, 0xe8);
- word = 0x0404;
- pci_write_config16(dev, 0xe8, word);
+ word = 0x0404;
+ pci_write_config16(dev, 0xe8, word);
/* Set discard unrequested prefetch data */
/* Errata #51 */
word = pci_read_config16(dev, 0x4c);
- word |= 1;
- pci_write_config16(dev, 0x4c, word);
+ word |= 1;
+ pci_write_config16(dev, 0x4c, word);
/* Set split transaction limits */
word = pci_read_config16(dev, 0xa8);
- pci_write_config16(dev, 0xaa, word);
+ pci_write_config16(dev, 0xaa, word);
word = pci_read_config16(dev, 0xac);
- pci_write_config16(dev, 0xae, word);
+ pci_write_config16(dev, 0xae, word);
/* Set up error reporting, enable all */
/* system error enable */
dword = pci_read_config32(dev, 0x04);
- dword |= (1<<8);
- pci_write_config32(dev, 0x04, dword);
+ dword |= (1<<8);
+ pci_write_config32(dev, 0x04, dword);
/* system and error parity enable */
dword = pci_read_config32(dev, 0x3c);
- dword |= (3<<16);
- pci_write_config32(dev, 0x3c, dword);
+ dword |= (3<<16);
+ pci_write_config32(dev, 0x3c, dword);
/* NMI enable */
nmi_option = NMI_OFF;
get_option(&nmi_option, "nmi");
if(nmi_option) {
dword = pci_read_config32(dev, 0x44);
- dword |= (1<<0);
- pci_write_config32(dev, 0x44, dword);
+ dword |= (1<<0);
+ pci_write_config32(dev, 0x44, dword);
}
/* Set up CRC flood enable */
@@ -377,22 +377,22 @@ static void bridge_set_resources(struct device *dev)
static struct device_operations pcix_ops = {
#if BRIDGE_40_BIT_SUPPORT
- .read_resources = bridge_read_resources,
- .set_resources = bridge_set_resources,
+ .read_resources = bridge_read_resources,
+ .set_resources = bridge_set_resources,
#else
- .read_resources = pci_bus_read_resources,
- .set_resources = pci_dev_set_resources,
+ .read_resources = pci_bus_read_resources,
+ .set_resources = pci_dev_set_resources,
#endif
.enable_resources = pci_bus_enable_resources,
- .init = amd8131_pcix_init,
- .scan_bus = amd8131_scan_bridge,
+ .init = amd8131_pcix_init,
+ .scan_bus = amd8131_scan_bridge,
.reset_bus = pci_bus_reset,
};
static const struct pci_driver pcix_driver __pci_driver = {
- .ops = &pcix_ops,
- .vendor = PCI_VENDOR_ID_AMD,
- .device = 0x7450,
+ .ops = &pcix_ops,
+ .vendor = PCI_VENDOR_ID_AMD,
+ .device = 0x7450,
};
diff --git a/src/southbridge/amd/amd8132/bridge.c b/src/southbridge/amd/amd8132/bridge.c
index ee45c65..6a7cab2 100644
--- a/src/southbridge/amd/amd8132/bridge.c
+++ b/src/southbridge/amd/amd8132/bridge.c
@@ -126,11 +126,11 @@ static void amd8132_pcix_tune_dev(device_t dev, void *ptr)
cmd |= max_tran << 4;
}
- /* Don't attempt to handle PCI-X errors */
- cmd &= ~PCI_X_CMD_DPERR_E;
- if (orig_cmd != cmd) {
- pci_write_config16(dev, cap + PCI_X_CMD, cmd);
- }
+ /* Don't attempt to handle PCI-X errors */
+ cmd &= ~PCI_X_CMD_DPERR_E;
+ if (orig_cmd != cmd) {
+ pci_write_config16(dev, cap + PCI_X_CMD, cmd);
+ }
}
@@ -203,13 +203,13 @@ static void amd8132_pcix_init(device_t dev)
unsigned chip_rev;
/* Find the revision of the 8132 */
- chip_rev = pci_read_config8(dev, PCI_CLASS_REVISION);
+ chip_rev = pci_read_config8(dev, PCI_CLASS_REVISION);
/* Enable memory write and invalidate ??? */
dword = pci_read_config32(dev, 0x04);
- dword |= 0x10;
+ dword |= 0x10;
dword &= ~(1<<6); // PERSP Parity Error Response
- pci_write_config32(dev, 0x04, dword);
+ pci_write_config32(dev, 0x04, dword);
if (chip_rev == 0x01) {
/* Errata #37 */
@@ -229,54 +229,54 @@ static void amd8132_pcix_init(device_t dev)
/* Set up error reporting, enable all */
/* system error enable */
dword = pci_read_config32(dev, 0x04);
- dword |= (1<<8);
- pci_write_config32(dev, 0x04, dword);
+ dword |= (1<<8);
+ pci_write_config32(dev, 0x04, dword);
/* system and error parity enable */
dword = pci_read_config32(dev, 0x3c);
- dword |= (3<<16);
- pci_write_config32(dev, 0x3c, dword);
+ dword |= (3<<16);
+ pci_write_config32(dev, 0x3c, dword);
- dword = pci_read_config32(dev, 0x40);
-// dword &= ~(1<<31); /* WriteChainEnable */
+ dword = pci_read_config32(dev, 0x40);
+// dword &= ~(1<<31); /* WriteChainEnable */
dword |= (1<<31);
dword |= (1<<7);// must set to 1
dword |= (3<<21); //PCIErrorSerrDisable
- pci_write_config32(dev, 0x40, dword);
+ pci_write_config32(dev, 0x40, dword);
- /* EXTARB = 1, COMPAT = 0 */
- dword = pci_read_config32(dev, 0x48);
- dword |= (1<<3);
+ /* EXTARB = 1, COMPAT = 0 */
+ dword = pci_read_config32(dev, 0x48);
+ dword |= (1<<3);
dword &= ~(1<<0);
dword |= (1<<15); //CLEARPCILOG_L
dword |= (1<<19); //PERR FATAL Enable
dword |= (1<<22); // SERR FATAL Enable
dword |= (1<<23); // LPMARBENABLE
dword |= (0x61<<24); //LPMARBCOUNT
- pci_write_config32(dev, 0x48, dword);
+ pci_write_config32(dev, 0x48, dword);
- dword = pci_read_config32(dev, 0x4c);
- dword |= (1<<6); //Initial prefetch for memory read line request
+ dword = pci_read_config32(dev, 0x4c);
+ dword |= (1<<6); //Initial prefetch for memory read line request
dword |= (1<<9); //continuous prefetch Enable for memory read line request
- pci_write_config32(dev, 0x4c, dword);
+ pci_write_config32(dev, 0x4c, dword);
- /* Disable Single-Bit-Error Correction [30] = 0 */
- dword = pci_read_config32(dev, 0x70);
- dword &= ~(1<<30);
- pci_write_config32(dev, 0x70, dword);
+ /* Disable Single-Bit-Error Correction [30] = 0 */
+ dword = pci_read_config32(dev, 0x70);
+ dword &= ~(1<<30);
+ pci_write_config32(dev, 0x70, dword);
//link
- dword = pci_read_config32(dev, 0xd4);
- dword |= (0x5c<<16);
- pci_write_config32(dev, 0xd4, dword);
+ dword = pci_read_config32(dev, 0xd4);
+ dword |= (0x5c<<16);
+ pci_write_config32(dev, 0xd4, dword);
- /* TxSlack0 [16:17] = 0, RxHwLookahdEn0 [18] = 1, TxSlack1 [24:25] = 0, RxHwLookahdEn1 [26] = 1 */
- dword = pci_read_config32(dev, 0xdc);
+ /* TxSlack0 [16:17] = 0, RxHwLookahdEn0 [18] = 1, TxSlack1 [24:25] = 0, RxHwLookahdEn1 [26] = 1 */
+ dword = pci_read_config32(dev, 0xdc);
dword |= (1<<1) | (1<<4); // stream disable 1 to 0 , DBLINSRATE
- dword |= (1<<18)|(1<<26);
- dword &= ~((3<<16)|(3<<24));
- pci_write_config32(dev, 0xdc, dword);
+ dword |= (1<<18)|(1<<26);
+ dword &= ~((3<<16)|(3<<24));
+ pci_write_config32(dev, 0xdc, dword);
/* Set up CRC flood enable */
dword = pci_read_config32(dev, 0xc0);
@@ -290,12 +290,12 @@ static void amd8132_pcix_init(device_t dev)
pci_write_config32(dev, 0xc8, dword);
#endif
- if (chip_rev == 0x11) {
- /* [18] Clock Gate Enable = 1 */
- dword = pci_read_config32(dev, 0xf0);
- dword |= 0x00040008;
- pci_write_config32(dev, 0xf0, dword);
- }
+ if (chip_rev == 0x11) {
+ /* [18] Clock Gate Enable = 1 */
+ dword = pci_read_config32(dev, 0xf0);
+ dword |= 0x00040008;
+ pci_write_config32(dev, 0xf0, dword);
+ }
}
return;
@@ -337,22 +337,22 @@ static void bridge_set_resources(struct device *dev)
static struct device_operations pcix_ops = {
#if BRIDGE_40_BIT_SUPPORT
- .read_resources = bridge_read_resources,
- .set_resources = bridge_set_resources,
+ .read_resources = bridge_read_resources,
+ .set_resources = bridge_set_resources,
#else
- .read_resources = pci_bus_read_resources,
- .set_resources = pci_dev_set_resources,
+ .read_resources = pci_bus_read_resources,
+ .set_resources = pci_dev_set_resources,
#endif
.enable_resources = pci_bus_enable_resources,
- .init = amd8132_pcix_init,
- .scan_bus = amd8132_scan_bridge,
+ .init = amd8132_pcix_init,
+ .scan_bus = amd8132_scan_bridge,
.reset_bus = pci_bus_reset,
};
static const struct pci_driver pcix_driver __pci_driver = {
- .ops = &pcix_ops,
- .vendor = PCI_VENDOR_ID_AMD,
- .device = 0x7458,
+ .ops = &pcix_ops,
+ .vendor = PCI_VENDOR_ID_AMD,
+ .device = 0x7458,
};
static void ioapic_enable(device_t dev)
@@ -369,39 +369,39 @@ static void ioapic_enable(device_t dev)
}
static void amd8132_ioapic_init(device_t dev)
{
- uint32_t dword;
- unsigned chip_rev;
+ uint32_t dword;
+ unsigned chip_rev;
- /* Find the revision of the 8132 */
- chip_rev = pci_read_config8(dev, PCI_CLASS_REVISION);
+ /* Find the revision of the 8132 */
+ chip_rev = pci_read_config8(dev, PCI_CLASS_REVISION);
- if (chip_rev == 0x01) {
+ if (chip_rev == 0x01) {
#if 0
- /* Errata #43 */
- dword = pci_read_config32(dev, 0xc8);
+ /* Errata #43 */
+ dword = pci_read_config32(dev, 0xc8);
dword |= (0x3<<23);
pci_write_config32(dev, 0xc8, dword);
#endif
- }
-
-
- if( (chip_rev == 0x11) ||(chip_rev == 0x12) ) {
- //for b1 b2
- /* Errata #73 */
- dword = pci_read_config32(dev, 0x80);
- dword |= (0x1f<<5);
- pci_write_config32(dev, 0x80, dword);
- dword = pci_read_config32(dev, 0x88);
- dword |= (0x1f<<5);
- pci_write_config32(dev, 0x88, dword);
-
- /* Errata #74 */
- dword = pci_read_config32(dev, 0x7c);
- dword &= ~(0x3<<30);
- dword |= (0x01<<30);
- pci_write_config32(dev, 0x7c, dword);
- }
+ }
+
+
+ if( (chip_rev == 0x11) ||(chip_rev == 0x12) ) {
+ //for b1 b2
+ /* Errata #73 */
+ dword = pci_read_config32(dev, 0x80);
+ dword |= (0x1f<<5);
+ pci_write_config32(dev, 0x80, dword);
+ dword = pci_read_config32(dev, 0x88);
+ dword |= (0x1f<<5);
+ pci_write_config32(dev, 0x88, dword);
+
+ /* Errata #74 */
+ dword = pci_read_config32(dev, 0x7c);
+ dword &= ~(0x3<<30);
+ dword |= (0x01<<30);
+ pci_write_config32(dev, 0x7c, dword);
+ }
}
diff --git a/src/southbridge/amd/amd8151/agp3.c b/src/southbridge/amd/amd8151/agp3.c
index 57699ff..18dd6d5 100644
--- a/src/southbridge/amd/amd8151/agp3.c
+++ b/src/southbridge/amd/amd8151/agp3.c
@@ -66,7 +66,7 @@ static void agp3dev_enable(device_t dev)
}
static struct pci_operations pci_ops_pci_dev = {
- .set_subsystem = pci_dev_set_subsystem,
+ .set_subsystem = pci_dev_set_subsystem,
};
static struct device_operations agp3dev_ops = {
diff --git a/src/southbridge/amd/cimx/sb800/Amd.h b/src/southbridge/amd/cimx/sb800/Amd.h
index 42e2b3a..26d2f1e 100644
--- a/src/southbridge/amd/cimx/sb800/Amd.h
+++ b/src/southbridge/amd/cimx/sb800/Amd.h
@@ -143,7 +143,7 @@ typedef struct _AMD_MODULE_HEADER {
#if 0
#define MAKE_SBDFO(Seg, Bus, Dev, Fun, Off) ((((unsigned int) (Seg)) << 28) | (((unsigned int) (Bus)) << 20) | \
- (((unsigned int) (Dev)) << 15) | (((unsigned int) (Fun)) << 12) | ((unsigned int) (Off)))
+ (((unsigned int) (Dev)) << 15) | (((unsigned int) (Fun)) << 12) | ((unsigned int) (Off)))
#endif
#define ILLEGAL_SBDFO 0xFFFFFFFF
diff --git a/src/southbridge/amd/cimx/sb800/early.c b/src/southbridge/amd/cimx/sb800/early.c
index 2a10c0e..866353d 100644
--- a/src/southbridge/amd/cimx/sb800/early.c
+++ b/src/southbridge/amd/cimx/sb800/early.c
@@ -66,6 +66,6 @@ void sb800_clk_output_48Mhz(void)
/* AcpiMMioDecodeEn */
RWPMIO(SB_PMIOA_REG24, AccWidthUint8, ~(BIT0 + BIT1), BIT0);
- *(volatile u32 *)(ACPI_MMIO_BASE + MISC_BASE + 0x40) &= ~((1 << 0) | (1 << 2)); /* 48Mhz */
- *(volatile u32 *)(ACPI_MMIO_BASE + MISC_BASE + 0x40) |= 1 << 1; /* 48Mhz */
+ *(volatile u32 *)(ACPI_MMIO_BASE + MISC_BASE + 0x40) &= ~((1 << 0) | (1 << 2)); /* 48Mhz */
+ *(volatile u32 *)(ACPI_MMIO_BASE + MISC_BASE + 0x40) |= 1 << 1; /* 48Mhz */
}
diff --git a/src/southbridge/amd/cimx/sb800/late.c b/src/southbridge/amd/cimx/sb800/late.c
index 693190f..fa47a96 100644
--- a/src/southbridge/amd/cimx/sb800/late.c
+++ b/src/southbridge/amd/cimx/sb800/late.c
@@ -151,21 +151,21 @@ unsigned long acpi_fill_mcfg(unsigned long current)
}
static struct device_operations lpc_ops = {
- .read_resources = lpc_read_resources,
- .set_resources = lpc_set_resources,
- .enable_resources = pci_dev_enable_resources,
+ .read_resources = lpc_read_resources,
+ .set_resources = lpc_set_resources,
+ .enable_resources = pci_dev_enable_resources,
#if IS_ENABLED(CONFIG_HAVE_ACPI_TABLES)
.write_acpi_tables = acpi_write_hpet,
#endif
- .init = lpc_init,
- .scan_bus = scan_lpc_bus,
- .ops_pci = &lops_pci,
+ .init = lpc_init,
+ .scan_bus = scan_lpc_bus,
+ .ops_pci = &lops_pci,
};
static const struct pci_driver lpc_driver __pci_driver = {
- .ops = &lpc_ops,
- .vendor = PCI_VENDOR_ID_ATI,
- .device = PCI_DEVICE_ID_ATI_SB800_LPC,
+ .ops = &lpc_ops,
+ .vendor = PCI_VENDOR_ID_ATI,
+ .device = PCI_DEVICE_ID_ATI_SB800_LPC,
};
static struct device_operations sata_ops = {
@@ -226,34 +226,34 @@ static const struct pci_driver usb_ohci4_driver __pci_driver = {
static struct device_operations azalia_ops = {
- .read_resources = pci_dev_read_resources,
- .set_resources = pci_dev_set_resources,
- .enable_resources = pci_dev_enable_resources,
- .init = 0,
- .scan_bus = 0,
- .ops_pci = &lops_pci,
+ .read_resources = pci_dev_read_resources,
+ .set_resources = pci_dev_set_resources,
+ .enable_resources = pci_dev_enable_resources,
+ .init = 0,
+ .scan_bus = 0,
+ .ops_pci = &lops_pci,
};
static const struct pci_driver azalia_driver __pci_driver = {
- .ops = &azalia_ops,
- .vendor = PCI_VENDOR_ID_ATI,
- .device = PCI_DEVICE_ID_ATI_SB800_HDA,
+ .ops = &azalia_ops,
+ .vendor = PCI_VENDOR_ID_ATI,
+ .device = PCI_DEVICE_ID_ATI_SB800_HDA,
};
static struct device_operations gec_ops = {
- .read_resources = pci_dev_read_resources,
- .set_resources = pci_dev_set_resources,
- .enable_resources = pci_dev_enable_resources,
- .init = 0,
- .scan_bus = 0,
- .ops_pci = &lops_pci,
+ .read_resources = pci_dev_read_resources,
+ .set_resources = pci_dev_set_resources,
+ .enable_resources = pci_dev_enable_resources,
+ .init = 0,
+ .scan_bus = 0,
+ .ops_pci = &lops_pci,
};
static const struct pci_driver gec_driver __pci_driver = {
- .ops = &gec_ops,
- .vendor = PCI_VENDOR_ID_ATI,
- .device = PCI_DEVICE_ID_ATI_SB800_GEC,
+ .ops = &gec_ops,
+ .vendor = PCI_VENDOR_ID_ATI,
+ .device = PCI_DEVICE_ID_ATI_SB800_GEC,
};
/**
diff --git a/src/southbridge/amd/cimx/sb800/smbus.c b/src/southbridge/amd/cimx/sb800/smbus.c
index 93ac0aa..80395f1 100644
--- a/src/southbridge/amd/cimx/sb800/smbus.c
+++ b/src/southbridge/amd/cimx/sb800/smbus.c
@@ -63,7 +63,7 @@ int do_smbus_recv_byte(u32 smbus_io_base, u32 device)
u8 byte;
if (smbus_wait_until_ready(smbus_io_base) < 0) {
- printk(BIOS_DEBUG, "SB800 - Smbus.c - do_smbus_recv_byte - smbus not ready.\n");
+ printk(BIOS_DEBUG, "SB800 - Smbus.c - do_smbus_recv_byte - smbus not ready.\n");
return -2; /* not ready */
}
@@ -93,7 +93,7 @@ int do_smbus_send_byte(u32 smbus_io_base, u32 device, u8 val)
u8 byte;
if (smbus_wait_until_ready(smbus_io_base) < 0) {
- printk(BIOS_DEBUG, "SB800 - Smbus.c - do_smbus_send_byte - smbus not ready.\n");
+ printk(BIOS_DEBUG, "SB800 - Smbus.c - do_smbus_send_byte - smbus not ready.\n");
return -2; /* not ready */
}
@@ -123,7 +123,7 @@ int do_smbus_read_byte(u32 smbus_io_base, u32 device, u32 address)
u8 byte;
if (smbus_wait_until_ready(smbus_io_base) < 0) {
- printk(BIOS_DEBUG, "SB800 - Smbus.c - do_smbus_read_byte - smbus not ready.\n");
+ printk(BIOS_DEBUG, "SB800 - Smbus.c - do_smbus_read_byte - smbus not ready.\n");
return -2; /* not ready */
}
@@ -156,7 +156,7 @@ int do_smbus_write_byte(u32 smbus_io_base, u32 device, u32 address, u8 val)
u8 byte;
if (smbus_wait_until_ready(smbus_io_base) < 0) {
- printk(BIOS_DEBUG, "SB800 - Smbus.c - do_smbus_write_byte - smbus not ready.\n");
+ printk(BIOS_DEBUG, "SB800 - Smbus.c - do_smbus_write_byte - smbus not ready.\n");
return -2; /* not ready */
}
diff --git a/src/southbridge/amd/cimx/sb900/Amd.h b/src/southbridge/amd/cimx/sb900/Amd.h
index ec81400..1583c6f 100644
--- a/src/southbridge/amd/cimx/sb900/Amd.h
+++ b/src/southbridge/amd/cimx/sb900/Amd.h
@@ -143,7 +143,7 @@ typedef struct _AMD_MODULE_HEADER {
#if 0
#define MAKE_SBDFO(Seg, Bus, Dev, Fun, Off) ((((unsigned int) (Seg)) << 28) | (((unsigned int) (Bus)) << 20) | \
- (((unsigned int) (Dev)) << 15) | (((unsigned int) (Fun)) << 12) | ((unsigned int) (Off)))
+ (((unsigned int) (Dev)) << 15) | (((unsigned int) (Fun)) << 12) | ((unsigned int) (Off)))
#endif
#define ILLEGAL_SBDFO 0xFFFFFFFF
diff --git a/src/southbridge/amd/cimx/sb900/cfg.c b/src/southbridge/amd/cimx/sb900/cfg.c
index be54197..bc7e742 100644
--- a/src/southbridge/amd/cimx/sb900/cfg.c
+++ b/src/southbridge/amd/cimx/sb900/cfg.c
@@ -28,7 +28,7 @@
void sb900_cimx_config(AMDSBCFG *sb_config)
{
if (!sb_config) {
- printk(BIOS_INFO, "SB900 - Cfg.c - sb900_cimx_config - No sb_config.\n");
+ printk(BIOS_INFO, "SB900 - Cfg.c - sb900_cimx_config - No sb_config.\n");
return;
}
printk(BIOS_INFO, "SB900 - Cfg.c - sb900_cimx_config - Start.\n");
@@ -257,7 +257,7 @@ void sb900_cimx_config(AMDSBCFG *sb_config)
void SbPowerOnInit_Config(AMDSBCFG *sb_config)
{
if (!sb_config) {
- printk(BIOS_INFO, "SB900 - Cfg.c - SbPowerOnInit_Config - No sb_config.\n");
+ printk(BIOS_INFO, "SB900 - Cfg.c - SbPowerOnInit_Config - No sb_config.\n");
return;
}
printk(BIOS_INFO, "SB900 - Cfg.c - SbPowerOnInit_Config - Start.\n");
diff --git a/src/southbridge/amd/cimx/sb900/late.c b/src/southbridge/amd/cimx/sb900/late.c
index f078c51..65c2446 100644
--- a/src/southbridge/amd/cimx/sb900/late.c
+++ b/src/southbridge/amd/cimx/sb900/late.c
@@ -121,21 +121,21 @@ unsigned long acpi_fill_mcfg(unsigned long current)
}
static struct device_operations lpc_ops = {
- .read_resources = lpc_read_resources,
- .set_resources = lpc_set_resources,
- .enable_resources = lpc_enable_resources,
- .init = lpc_init,
+ .read_resources = lpc_read_resources,
+ .set_resources = lpc_set_resources,
+ .enable_resources = lpc_enable_resources,
+ .init = lpc_init,
#if IS_ENABLED(CONFIG_HAVE_ACPI_TABLES)
.write_acpi_tables = acpi_write_hpet,
#endif
- .scan_bus = scan_lpc_bus,
- .ops_pci = &lops_pci,
+ .scan_bus = scan_lpc_bus,
+ .ops_pci = &lops_pci,
};
static const struct pci_driver lpc_driver __pci_driver = {
- .ops = &lpc_ops,
- .vendor = PCI_VENDOR_ID_AMD,
- .device = PCI_DEVICE_ID_ATI_SB900_LPC,
+ .ops = &lpc_ops,
+ .vendor = PCI_VENDOR_ID_AMD,
+ .device = PCI_DEVICE_ID_ATI_SB900_LPC,
};
@@ -239,18 +239,18 @@ static void azalia_init(struct device *dev)
}
static struct device_operations azalia_ops = {
- .read_resources = pci_dev_read_resources,
- .set_resources = pci_dev_set_resources,
- .enable_resources = pci_dev_enable_resources,
- .init = azalia_init,
- .scan_bus = 0,
- .ops_pci = &lops_pci,
+ .read_resources = pci_dev_read_resources,
+ .set_resources = pci_dev_set_resources,
+ .enable_resources = pci_dev_enable_resources,
+ .init = azalia_init,
+ .scan_bus = 0,
+ .ops_pci = &lops_pci,
};
static const struct pci_driver azalia_driver __pci_driver = {
- .ops = &azalia_ops,
- .vendor = PCI_VENDOR_ID_AMD,
- .device = PCI_DEVICE_ID_ATI_SB900_HDA,
+ .ops = &azalia_ops,
+ .vendor = PCI_VENDOR_ID_AMD,
+ .device = PCI_DEVICE_ID_ATI_SB900_HDA,
};
@@ -263,18 +263,18 @@ static void gec_init(struct device *dev)
}
static struct device_operations gec_ops = {
- .read_resources = pci_dev_read_resources,
- .set_resources = pci_dev_set_resources,
- .enable_resources = pci_dev_enable_resources,
- .init = gec_init,
- .scan_bus = 0,
- .ops_pci = &lops_pci,
+ .read_resources = pci_dev_read_resources,
+ .set_resources = pci_dev_set_resources,
+ .enable_resources = pci_dev_enable_resources,
+ .init = gec_init,
+ .scan_bus = 0,
+ .ops_pci = &lops_pci,
};
static const struct pci_driver gec_driver __pci_driver = {
- .ops = &gec_ops,
- .vendor = PCI_VENDOR_ID_AMD,
- .device = PCI_DEVICE_ID_ATI_SB900_GEC,
+ .ops = &gec_ops,
+ .vendor = PCI_VENDOR_ID_AMD,
+ .device = PCI_DEVICE_ID_ATI_SB900_GEC,
};
@@ -286,19 +286,19 @@ static void pcie_init(device_t dev)
}
static struct device_operations pci_ops = {
- .read_resources = pci_bus_read_resources,
- .set_resources = pci_dev_set_resources,
- .enable_resources = pci_bus_enable_resources,
- .init = pcie_init,
- .scan_bus = pci_scan_bridge,
- .reset_bus = pci_bus_reset,
- .ops_pci = &lops_pci,
+ .read_resources = pci_bus_read_resources,
+ .set_resources = pci_dev_set_resources,
+ .enable_resources = pci_bus_enable_resources,
+ .init = pcie_init,
+ .scan_bus = pci_scan_bridge,
+ .reset_bus = pci_bus_reset,
+ .ops_pci = &lops_pci,
};
static const struct pci_driver pci_driver __pci_driver = {
- .ops = &pci_ops,
- .vendor = PCI_VENDOR_ID_AMD,
- .device = PCI_DEVICE_ID_ATI_SB900_PCI,
+ .ops = &pci_ops,
+ .vendor = PCI_VENDOR_ID_AMD,
+ .device = PCI_DEVICE_ID_ATI_SB900_PCI,
};
@@ -315,30 +315,30 @@ struct device_operations bridge_ops = {
/* 0:15:0 PCIe PortA */
static const struct pci_driver PORTA_driver __pci_driver = {
- .ops = &bridge_ops,
- .vendor = PCI_VENDOR_ID_AMD,
- .device = PCI_DEVICE_ID_ATI_SB900_PCIEA,
+ .ops = &bridge_ops,
+ .vendor = PCI_VENDOR_ID_AMD,
+ .device = PCI_DEVICE_ID_ATI_SB900_PCIEA,
};
/* 0:15:1 PCIe PortB */
static const struct pci_driver PORTB_driver __pci_driver = {
- .ops = &bridge_ops,
- .vendor = PCI_VENDOR_ID_AMD,
- .device = PCI_DEVICE_ID_ATI_SB900_PCIEB,
+ .ops = &bridge_ops,
+ .vendor = PCI_VENDOR_ID_AMD,
+ .device = PCI_DEVICE_ID_ATI_SB900_PCIEB,
};
/* 0:15:2 PCIe PortC */
static const struct pci_driver PORTC_driver __pci_driver = {
- .ops = &bridge_ops,
- .vendor = PCI_VENDOR_ID_AMD,
- .device = PCI_DEVICE_ID_ATI_SB900_PCIEC,
+ .ops = &bridge_ops,
+ .vendor = PCI_VENDOR_ID_AMD,
+ .device = PCI_DEVICE_ID_ATI_SB900_PCIEC,
};
/* 0:15:3 PCIe PortD */
static const struct pci_driver PORTD_driver __pci_driver = {
- .ops = &bridge_ops,
- .vendor = PCI_VENDOR_ID_AMD,
- .device = PCI_DEVICE_ID_ATI_SB900_PCIED,
+ .ops = &bridge_ops,
+ .vendor = PCI_VENDOR_ID_AMD,
+ .device = PCI_DEVICE_ID_ATI_SB900_PCIED,
};
diff --git a/src/southbridge/amd/cimx/sb900/smbus.c b/src/southbridge/amd/cimx/sb900/smbus.c
index 358bd48..7d11898 100644
--- a/src/southbridge/amd/cimx/sb900/smbus.c
+++ b/src/southbridge/amd/cimx/sb900/smbus.c
@@ -63,7 +63,7 @@ int do_smbus_recv_byte(u32 smbus_io_base, u32 device)
u8 byte;
if (smbus_wait_until_ready(smbus_io_base) < 0) {
- printk(BIOS_INFO, "SB900 - Smbus.c - do_smbus_recv_byte - smbus no ready.\n");
+ printk(BIOS_INFO, "SB900 - Smbus.c - do_smbus_recv_byte - smbus no ready.\n");
return -2; /* not ready */
}
@@ -93,7 +93,7 @@ int do_smbus_send_byte(u32 smbus_io_base, u32 device, u8 val)
u8 byte;
if (smbus_wait_until_ready(smbus_io_base) < 0) {
- printk(BIOS_INFO, "SB900 - Smbus.c - do_smbus_send_byte - smbus no ready.\n");
+ printk(BIOS_INFO, "SB900 - Smbus.c - do_smbus_send_byte - smbus no ready.\n");
return -2; /* not ready */
}
@@ -123,7 +123,7 @@ int do_smbus_read_byte(u32 smbus_io_base, u32 device, u32 address)
u8 byte;
if (smbus_wait_until_ready(smbus_io_base) < 0) {
- printk(BIOS_INFO, "SB900 - Smbus.c - do_smbus_read_byte - smbus no ready.\n");
+ printk(BIOS_INFO, "SB900 - Smbus.c - do_smbus_read_byte - smbus no ready.\n");
return -2; /* not ready */
}
@@ -156,7 +156,7 @@ int do_smbus_write_byte(u32 smbus_io_base, u32 device, u32 address, u8 val)
u8 byte;
if (smbus_wait_until_ready(smbus_io_base) < 0) {
- printk(BIOS_INFO, "SB900 - Smbus.c - do_smbus_write_byte - smbus no ready.\n");
+ printk(BIOS_INFO, "SB900 - Smbus.c - do_smbus_write_byte - smbus no ready.\n");
return -2; /* not ready */
}
diff --git a/src/southbridge/amd/cs5535/cs5535.c b/src/southbridge/amd/cs5535/cs5535.c
index 70b8386..c1f1960 100644
--- a/src/southbridge/amd/cs5535/cs5535.c
+++ b/src/southbridge/amd/cs5535/cs5535.c
@@ -103,9 +103,9 @@ static const struct pci_driver cs5535_pci_driver __pci_driver = {
};
struct chip_operations southbridge_amd_cs5535_ops = {
- CHIP_NAME("AMD Geode CS5535 Southbridge")
- /* This is only called when this device is listed in the
- * static device tree.
- */
- .enable_dev = southbridge_enable,
+ CHIP_NAME("AMD Geode CS5535 Southbridge")
+ /* This is only called when this device is listed in the
+ * static device tree.
+ */
+ .enable_dev = southbridge_enable,
};
diff --git a/src/southbridge/amd/rs690/gfx.c b/src/southbridge/amd/rs690/gfx.c
index 57d6628..bcba435 100644
--- a/src/southbridge/amd/rs690/gfx.c
+++ b/src/southbridge/amd/rs690/gfx.c
@@ -461,48 +461,48 @@ void rs690_gfx_init(device_t nb_dev, device_t dev, u32 port)
/* done by enable_pci_bar3() before */
/* step 6 SBIOS compile flags */
- if (cfg->gfx_tmds) {
- /* step 6.2.2 Clock-Muxing Control */
- /* step 6.2.2.1 */
- set_nbmisc_enable_bits(nb_dev, 0x7, 1 << 16, 1 << 16);
+ if (cfg->gfx_tmds) {
+ /* step 6.2.2 Clock-Muxing Control */
+ /* step 6.2.2.1 */
+ set_nbmisc_enable_bits(nb_dev, 0x7, 1 << 16, 1 << 16);
- /* step 6.2.2.2 */
- set_nbmisc_enable_bits(nb_dev, 0x7, 1 << 8, 1 << 8);
- set_nbmisc_enable_bits(nb_dev, 0x7, 1 << 10, 1 << 10);
+ /* step 6.2.2.2 */
+ set_nbmisc_enable_bits(nb_dev, 0x7, 1 << 8, 1 << 8);
+ set_nbmisc_enable_bits(nb_dev, 0x7, 1 << 10, 1 << 10);
- /* step 6.2.2.3 */
- set_nbmisc_enable_bits(nb_dev, 0x7, 1 << 26, 1 << 26);
+ /* step 6.2.2.3 */
+ set_nbmisc_enable_bits(nb_dev, 0x7, 1 << 26, 1 << 26);
- /* step 6.2.3 Lane-Muxing Control */
- /* step 6.2.3.1 */
- set_nbmisc_enable_bits(nb_dev, 0x37, 0x3 << 8, 0x2 << 8);
+ /* step 6.2.3 Lane-Muxing Control */
+ /* step 6.2.3.1 */
+ set_nbmisc_enable_bits(nb_dev, 0x37, 0x3 << 8, 0x2 << 8);
- /* step 6.2.4 Received Data Control */
- /* step 6.2.4.1 */
- set_pcie_enable_bits(nb_dev, 0x40, 0x3 << 16, 0x2 << 16);
+ /* step 6.2.4 Received Data Control */
+ /* step 6.2.4.1 */
+ set_pcie_enable_bits(nb_dev, 0x40, 0x3 << 16, 0x2 << 16);
- /* step 6.2.4.2 */
- set_pcie_enable_bits(nb_dev, 0x40, 0x3 << 18, 0x3 << 18);
+ /* step 6.2.4.2 */
+ set_pcie_enable_bits(nb_dev, 0x40, 0x3 << 18, 0x3 << 18);
- /* step 6.2.4.3 */
- set_pcie_enable_bits(nb_dev, 0x40, 0x3 << 20, 0x0 << 20);
+ /* step 6.2.4.3 */
+ set_pcie_enable_bits(nb_dev, 0x40, 0x3 << 20, 0x0 << 20);
- /* step 6.2.4.4 */
- set_pcie_enable_bits(nb_dev, 0x40, 0x3 << 22, 0x1 << 22);
+ /* step 6.2.4.4 */
+ set_pcie_enable_bits(nb_dev, 0x40, 0x3 << 22, 0x1 << 22);
- /* step 6.2.5 PLL Power Down Control */
- /* step 6.2.5.1 */
- set_nbmisc_enable_bits(nb_dev, 0x35, 0x3 << 6, 0x0 << 6);
+ /* step 6.2.5 PLL Power Down Control */
+ /* step 6.2.5.1 */
+ set_nbmisc_enable_bits(nb_dev, 0x35, 0x3 << 6, 0x0 << 6);
- /* step 6.2.6 Driving Strength Control */
- /* step 6.2.6.1 */
- set_nbmisc_enable_bits(nb_dev, 0x34, 0x1 << 24, 0x0 << 24);
+ /* step 6.2.6 Driving Strength Control */
+ /* step 6.2.6.1 */
+ set_nbmisc_enable_bits(nb_dev, 0x34, 0x1 << 24, 0x0 << 24);
- /* step 6.2.6.2 */
- set_nbmisc_enable_bits(nb_dev, 0x35, 0x3 << 2, 0x3 << 2);
- }
+ /* step 6.2.6.2 */
+ set_nbmisc_enable_bits(nb_dev, 0x35, 0x3 << 2, 0x3 << 2);
+ }
- printk(BIOS_INFO, "rs690_gfx_init step6.\n");
+ printk(BIOS_INFO, "rs690_gfx_init step6.\n");
/* step 7 compliance state, (only need if CMOS option is enabled) */
/* the compliance state is just for test. refer to 4.2.5.2 of PCIe specification */
diff --git a/src/southbridge/amd/rs690/pcie.c b/src/southbridge/amd/rs690/pcie.c
index bcf4f4d..043c2ee 100644
--- a/src/southbridge/amd/rs690/pcie.c
+++ b/src/southbridge/amd/rs690/pcie.c
@@ -84,7 +84,7 @@ static void PciePowerOffGppPorts(device_t nb_dev, device_t dev, u32 port)
PCIE_GFX_COMPLIANCE))) {
}
- if (!cfg->gfx_tmds){
+ if (!cfg->gfx_tmds){
/* step 3 Power Down Control for Southbridge */
reg = nbpcie_p_read_index(dev, 0xa2);
diff --git a/src/southbridge/amd/rs780/rs780.h b/src/southbridge/amd/rs780/rs780.h
index ffd0e15..dbd6651 100644
--- a/src/southbridge/amd/rs780/rs780.h
+++ b/src/southbridge/amd/rs780/rs780.h
@@ -101,7 +101,7 @@ typedef struct _ATOM_INTEGRATED_SYSTEM_INFO_V2
ULONG ulDockingPinCFGInfo;
ULONG ulCPUCapInfo;
USHORT usNumberOfCyclesInPeriod; //usNumberOfCyclesInPeriod[15] = 0 - invert waveform
- // 1 - non inverted waveform
+ // 1 - non inverted waveform
USHORT usMaxNBVoltage;
USHORT usMinNBVoltage;
USHORT usBootUpNBVoltage;
diff --git a/src/southbridge/amd/sb700/sm.c b/src/southbridge/amd/sb700/sm.c
index 6d93b17..77dd6ca 100644
--- a/src/southbridge/amd/sb700/sm.c
+++ b/src/southbridge/amd/sb700/sm.c
@@ -278,7 +278,7 @@ static void sm_init(device_t dev)
u16 word;
/* rpr v2.13 4.18 Enabling Posted Pass Non-Posted Downstream */
- axindxc_reg(0x02, 1 << 9, 1 << 9);
+ axindxc_reg(0x02, 1 << 9, 1 << 9);
abcfg_reg(0x9C, 0x00007CC0, 0x00007CC0);
abcfg_reg(0x1009C, 0x00000030, 0x00000030);
abcfg_reg(0x10090, 0x00001E00, 0x00001E00);
@@ -287,7 +287,7 @@ static void sm_init(device_t dev)
abcfg_reg(0x58, 0x0000F800, 0x0000E800);
/* rpr v2.13 4.20 64 bit Non-Posted Memory Write Support */
- axindxc_reg(0x02, 1 << 10, 1 << 10);
+ axindxc_reg(0x02, 1 << 10, 1 << 10);
/* rpr v2.13 2.38 Unconditional Shutdown */
byte = pci_read_config8(dev, 0x43);
diff --git a/src/southbridge/amd/sr5650/early_setup.c b/src/southbridge/amd/sr5650/early_setup.c
index a96b127..1c3b9fc 100644
--- a/src/southbridge/amd/sr5650/early_setup.c
+++ b/src/southbridge/amd/sr5650/early_setup.c
@@ -30,22 +30,22 @@
*/
static void alink_ax_indx(u32 space, u32 axindc, u32 mask, u32 val)
{
- u32 tmp;
-
- /* read axindc to tmp */
- outl(space << 30 | space << 3 | 0x30, AB_INDX);
- outl(axindc, AB_DATA);
- outl(space << 30 | space << 3 | 0x34, AB_INDX);
- tmp = inl(AB_DATA);
-
- tmp &= ~mask;
- tmp |= val;
-
- /* write tmp */
- outl(space << 30 | space << 3 | 0x30, AB_INDX);
- outl(axindc, AB_DATA);
- outl(space << 30 | space << 3 | 0x34, AB_INDX);
- outl(tmp, AB_DATA);
+ u32 tmp;
+
+ /* read axindc to tmp */
+ outl(space << 30 | space << 3 | 0x30, AB_INDX);
+ outl(axindc, AB_DATA);
+ outl(space << 30 | space << 3 | 0x34, AB_INDX);
+ tmp = inl(AB_DATA);
+
+ tmp &= ~mask;
+ tmp |= val;
+
+ /* write tmp */
+ outl(space << 30 | space << 3 | 0x30, AB_INDX);
+ outl(axindc, AB_DATA);
+ outl(space << 30 | space << 3 | 0x34, AB_INDX);
+ outl(tmp, AB_DATA);
}
diff --git a/src/southbridge/amd/sr5650/sr5650.c b/src/southbridge/amd/sr5650/sr5650.c
index d28adfc..87845c6 100644
--- a/src/southbridge/amd/sr5650/sr5650.c
+++ b/src/southbridge/amd/sr5650/sr5650.c
@@ -817,8 +817,8 @@ unsigned long acpi_fill_mcfg(unsigned long current)
resource_t mmconf_base = EXT_CONF_BASE_ADDRESS;
if (IS_ENABLED(CONFIG_EXT_CONF_SUPPORT)) {
- res = sr5650_retrieve_cpu_mmio_resource();
- if (res)
+ res = sr5650_retrieve_cpu_mmio_resource();
+ if (res)
mmconf_base = res->base;
current += acpi_create_mcfg_mmconfig((acpi_mcfg_mmconfig_t *)current, mmconf_base, 0x0, 0x0, 0x1f);
diff --git a/src/southbridge/broadcom/bcm21000/pcie.c b/src/southbridge/broadcom/bcm21000/pcie.c
index ca9a225..ab52029 100644
--- a/src/southbridge/broadcom/bcm21000/pcie.c
+++ b/src/southbridge/broadcom/bcm21000/pcie.c
@@ -43,7 +43,7 @@ static void pcie_init(struct device *dev)
}
static struct pci_operations lops_pci = {
- .set_subsystem = 0,
+ .set_subsystem = 0,
};
static struct device_operations pcie_ops = {
diff --git a/src/southbridge/broadcom/bcm5780/nic.c b/src/southbridge/broadcom/bcm5780/nic.c
index be23d68..d0ff9ca 100644
--- a/src/southbridge/broadcom/bcm5780/nic.c
+++ b/src/southbridge/broadcom/bcm5780/nic.c
@@ -23,12 +23,12 @@
static void lpci_set_subsystem(device_t dev, unsigned vendor, unsigned device)
{
- pci_write_config32(dev, 0x40,
- ((device & 0xffff) << 16) | (vendor & 0xffff));
+ pci_write_config32(dev, 0x40,
+ ((device & 0xffff) << 16) | (vendor & 0xffff));
}
static struct pci_operations lops_pci = {
- .set_subsystem = lpci_set_subsystem,
+ .set_subsystem = lpci_set_subsystem,
};
static struct device_operations nic_ops = {
@@ -47,7 +47,7 @@ static const struct pci_driver nic_driver __pci_driver = {
};
static const struct pci_driver nic1_driver __pci_driver = {
- .ops = &nic_ops,
- .vendor = PCI_VENDOR_ID_BROADCOM,
- .device = PCI_DEVICE_ID_BROADCOM_BCM5780_NIC1,
+ .ops = &nic_ops,
+ .vendor = PCI_VENDOR_ID_BROADCOM,
+ .device = PCI_DEVICE_ID_BROADCOM_BCM5780_NIC1,
};
diff --git a/src/southbridge/broadcom/bcm5780/pcie.c b/src/southbridge/broadcom/bcm5780/pcie.c
index 6f8493e..2ed6102 100644
--- a/src/southbridge/broadcom/bcm5780/pcie.c
+++ b/src/southbridge/broadcom/bcm5780/pcie.c
@@ -35,17 +35,17 @@ static void pcie_init(struct device *dev)
}
static struct pci_operations lops_pci = {
- .set_subsystem = 0,
+ .set_subsystem = 0,
};
static struct device_operations pcie_ops = {
- .read_resources = pci_bus_read_resources,
- .set_resources = pci_dev_set_resources,
- .enable_resources = pci_bus_enable_resources,
- .init = pcie_init,
- .scan_bus = pci_scan_bridge,
- .reset_bus = pci_bus_reset,
- .ops_pci = &lops_pci,
+ .read_resources = pci_bus_read_resources,
+ .set_resources = pci_dev_set_resources,
+ .enable_resources = pci_bus_enable_resources,
+ .init = pcie_init,
+ .scan_bus = pci_scan_bridge,
+ .reset_bus = pci_bus_reset,
+ .ops_pci = &lops_pci,
};
diff --git a/src/southbridge/broadcom/bcm5780/pcix.c b/src/southbridge/broadcom/bcm5780/pcix.c
index 22dc771..8aa37a6 100644
--- a/src/southbridge/broadcom/bcm5780/pcix.c
+++ b/src/southbridge/broadcom/bcm5780/pcix.c
@@ -22,22 +22,22 @@
static void lpci_set_subsystem(device_t dev, unsigned vendor, unsigned device)
{
- pci_write_config32(dev, 0x40,
- ((device & 0xffff) << 16) | (vendor & 0xffff));
+ pci_write_config32(dev, 0x40,
+ ((device & 0xffff) << 16) | (vendor & 0xffff));
}
static struct pci_operations lops_pci = {
- .set_subsystem = lpci_set_subsystem,
+ .set_subsystem = lpci_set_subsystem,
};
static struct device_operations ht_ops = {
- .read_resources = pci_bus_read_resources,
- .set_resources = pci_dev_set_resources,
- .enable_resources = pci_bus_enable_resources,
- .init = 0 ,
- .scan_bus = pci_scan_bridge,
- .reset_bus = pci_bus_reset,
- .ops_pci = &lops_pci,
+ .read_resources = pci_bus_read_resources,
+ .set_resources = pci_dev_set_resources,
+ .enable_resources = pci_bus_enable_resources,
+ .init = 0 ,
+ .scan_bus = pci_scan_bridge,
+ .reset_bus = pci_bus_reset,
+ .ops_pci = &lops_pci,
};
diff --git a/src/southbridge/broadcom/bcm5785/bcm5785.c b/src/southbridge/broadcom/bcm5785/bcm5785.c
index 7e8d8c3..5fc97c3 100644
--- a/src/southbridge/broadcom/bcm5785/bcm5785.c
+++ b/src/southbridge/broadcom/bcm5785/bcm5785.c
@@ -36,13 +36,13 @@ void bcm5785_enable(device_t dev)
sb_pci_main_dev = dev_find_slot(bus_dev->bus->secondary, devfn);
// index = ((dev->path.pci.devfn & ~7) >> 3) + 8;
} else if ((bus_dev->vendor == PCI_VENDOR_ID_SERVERWORKS) &&
- (bus_dev->device == 0x0104)) // device under PCI Bridge( under PCI-X )
- {
- unsigned devfn;
- devfn = bus_dev->bus->dev->path.pci.devfn + (1 << 3);
- sb_pci_main_dev = dev_find_slot(bus_dev->bus->dev->bus->secondary, devfn);
+ (bus_dev->device == 0x0104)) // device under PCI Bridge( under PCI-X )
+ {
+ unsigned devfn;
+ devfn = bus_dev->bus->dev->path.pci.devfn + (1 << 3);
+ sb_pci_main_dev = dev_find_slot(bus_dev->bus->dev->bus->secondary, devfn);
// index = ((dev->path.pci.devfn & ~7) >> 3) + 8;
- }
+ }
else { // same bus
unsigned devfn;
devfn = (dev->path.pci.devfn) & ~7;
diff --git a/src/southbridge/broadcom/bcm5785/chip.h b/src/southbridge/broadcom/bcm5785/chip.h
index ac39fd1..2c65734 100644
--- a/src/southbridge/broadcom/bcm5785/chip.h
+++ b/src/southbridge/broadcom/bcm5785/chip.h
@@ -19,10 +19,10 @@
struct southbridge_broadcom_bcm5785_config
{
- unsigned int ide0_enable : 1;
- unsigned int ide1_enable : 1;
- unsigned int sata0_enable : 1;
- unsigned int sata1_enable : 1;
+ unsigned int ide0_enable : 1;
+ unsigned int ide1_enable : 1;
+ unsigned int sata0_enable : 1;
+ unsigned int sata1_enable : 1;
};
#endif /* BCM5785_CHIP_H */
diff --git a/src/southbridge/broadcom/bcm5785/early_setup.c b/src/southbridge/broadcom/bcm5785/early_setup.c
index e29fab4..e8895fb 100644
--- a/src/southbridge/broadcom/bcm5785/early_setup.c
+++ b/src/southbridge/broadcom/bcm5785/early_setup.c
@@ -19,62 +19,62 @@
static void bcm5785_enable_lpc(void)
{
- uint8_t byte;
- device_t dev;
-
- dev = pci_locate_device(PCI_ID(0x1166, 0x0234), 0);
-
- /* LPC Control 0 */
- byte = pci_read_config8(dev, 0x44);
- /* Serial 0 */
- byte |= (1<<6);
- pci_write_config8(dev, 0x44, byte);
-
- /* LPC Control 4 */
- byte = pci_read_config8(dev, 0x48);
- /* superio port 0x2e/4e enable */
- byte |=(1<<1)|(1<<0);
- pci_write_config8(dev, 0x48, byte);
+ uint8_t byte;
+ device_t dev;
+
+ dev = pci_locate_device(PCI_ID(0x1166, 0x0234), 0);
+
+ /* LPC Control 0 */
+ byte = pci_read_config8(dev, 0x44);
+ /* Serial 0 */
+ byte |= (1<<6);
+ pci_write_config8(dev, 0x44, byte);
+
+ /* LPC Control 4 */
+ byte = pci_read_config8(dev, 0x48);
+ /* superio port 0x2e/4e enable */
+ byte |=(1<<1)|(1<<0);
+ pci_write_config8(dev, 0x48, byte);
}
static void bcm5785_enable_wdt_port_cf9(void)
{
- device_t dev;
- uint32_t dword;
- uint32_t dword_old;
+ device_t dev;
+ uint32_t dword;
+ uint32_t dword_old;
- dev = pci_locate_device(PCI_ID(0x1166, 0x0205), 0);
+ dev = pci_locate_device(PCI_ID(0x1166, 0x0205), 0);
- dword_old = pci_read_config32(dev, 0x4c);
- dword = dword_old | (1<<4); //enable Timer Func
- if(dword != dword_old ) {
- pci_write_config32(dev, 0x4c, dword);
- }
+ dword_old = pci_read_config32(dev, 0x4c);
+ dword = dword_old | (1<<4); //enable Timer Func
+ if(dword != dword_old ) {
+ pci_write_config32(dev, 0x4c, dword);
+ }
- dword_old = pci_read_config32(dev, 0x6c);
- dword = dword_old | (1<<9); //unhide Timer Func in pci space
- if(dword != dword_old ) {
- pci_write_config32(dev, 0x6c, dword);
- }
+ dword_old = pci_read_config32(dev, 0x6c);
+ dword = dword_old | (1<<9); //unhide Timer Func in pci space
+ if(dword != dword_old ) {
+ pci_write_config32(dev, 0x6c, dword);
+ }
- dev = pci_locate_device(PCI_ID(0x1166, 0x0238), 0);
+ dev = pci_locate_device(PCI_ID(0x1166, 0x0238), 0);
- /* enable cf9 */
- pci_write_config8(dev, 0x40, (1<<2));
+ /* enable cf9 */
+ pci_write_config8(dev, 0x40, (1<<2));
}
unsigned get_sbdn(unsigned bus)
{
- device_t dev;
+ device_t dev;
- /* Find the device.
- * There can only be one bcm5785 on a hypertransport chain/bus.
- */
- dev = pci_locate_device_on_bus(
- PCI_ID(0x1166, 0x0036),
- bus);
+ /* Find the device.
+ * There can only be one bcm5785 on a hypertransport chain/bus.
+ */
+ dev = pci_locate_device_on_bus(
+ PCI_ID(0x1166, 0x0036),
+ bus);
- return (dev>>15) & 0x1f;
+ return (dev>>15) & 0x1f;
}
@@ -89,8 +89,8 @@ void enable_fid_change_on_sb(unsigned sbbusn, unsigned sbdn)
// set port to 0x2060
outb(0x67, 0xcd6);
outb(0x60, 0xcd7);
- outb(0x68, 0xcd6);
- outb(0x20, 0xcd7);
+ outb(0x68, 0xcd6);
+ outb(0x20, 0xcd7);
outb(0x69, 0xcd6);
outb(7, 0xcd7);
@@ -107,113 +107,113 @@ void ldtstop_sb(void)
void hard_reset(void)
{
- bcm5785_enable_wdt_port_cf9();
+ bcm5785_enable_wdt_port_cf9();
- set_bios_reset();
+ set_bios_reset();
- /* full reset */
- outb(0x0a, 0x0cf9);
- outb(0x0e, 0x0cf9);
+ /* full reset */
+ outb(0x0a, 0x0cf9);
+ outb(0x0e, 0x0cf9);
}
void soft_reset(void)
{
- bcm5785_enable_wdt_port_cf9();
+ bcm5785_enable_wdt_port_cf9();
- set_bios_reset();
+ set_bios_reset();
#if 1
- /* link reset */
-// outb(0x02, 0x0cf9);
- outb(0x06, 0x0cf9);
+ /* link reset */
+// outb(0x02, 0x0cf9);
+ outb(0x06, 0x0cf9);
#endif
}
static void bcm5785_enable_msg(void)
{
- device_t dev;
- uint32_t dword;
- uint32_t dword_old;
- uint8_t byte;
-
- dev = pci_locate_device(PCI_ID(0x1166, 0x0205), 0);
-
- byte = pci_read_config8(dev, 0x42);
- byte = (1<<1); //enable a20
- pci_write_config8(dev, 0x42, byte);
-
- dword_old = pci_read_config32(dev, 0x6c);
- // bit 5: enable A20 Message
- // bit 4: enable interrupt messages
- // bit 3: enable reset init message
- // bit 2: enable keyboard init message
- // bit 1: enable upsteam messages
- // bit 0: enable shutdowm message to init generation
- dword = dword_old | (1<<5) | (1<<3) | (1<<2) | (1<<1) | (1<<0); // bit 1 and bit 4 must be set, otherwise interrupt msg will not be delivered to the processor
- if(dword != dword_old ) {
- pci_write_config32(dev, 0x6c, dword);
- }
+ device_t dev;
+ uint32_t dword;
+ uint32_t dword_old;
+ uint8_t byte;
+
+ dev = pci_locate_device(PCI_ID(0x1166, 0x0205), 0);
+
+ byte = pci_read_config8(dev, 0x42);
+ byte = (1<<1); //enable a20
+ pci_write_config8(dev, 0x42, byte);
+
+ dword_old = pci_read_config32(dev, 0x6c);
+ // bit 5: enable A20 Message
+ // bit 4: enable interrupt messages
+ // bit 3: enable reset init message
+ // bit 2: enable keyboard init message
+ // bit 1: enable upsteam messages
+ // bit 0: enable shutdowm message to init generation
+ dword = dword_old | (1<<5) | (1<<3) | (1<<2) | (1<<1) | (1<<0); // bit 1 and bit 4 must be set, otherwise interrupt msg will not be delivered to the processor
+ if(dword != dword_old ) {
+ pci_write_config32(dev, 0x6c, dword);
+ }
}
static void bcm5785_early_setup(void)
{
- uint8_t byte;
- uint32_t dword;
- device_t dev;
+ uint8_t byte;
+ uint32_t dword;
+ device_t dev;
//F0
- // enable device on bcm5785 at first
- dev = pci_locate_device(PCI_ID(0x1166, 0x0205), 0);
- dword = pci_read_config32(dev, 0x64);
- dword |= (1<<15) | (1<<11) | (1<<3); // ioapci enable
- dword |= (1<<8); // USB enable
- dword |= /* (1<<27)|*/(1<<14); // IDE enable
- pci_write_config32(dev, 0x64, dword);
-
- byte = pci_read_config8(dev, 0x84);
- byte |= (1<<0); // SATA enable
- pci_write_config8(dev, 0x84, byte);
+ // enable device on bcm5785 at first
+ dev = pci_locate_device(PCI_ID(0x1166, 0x0205), 0);
+ dword = pci_read_config32(dev, 0x64);
+ dword |= (1<<15) | (1<<11) | (1<<3); // ioapci enable
+ dword |= (1<<8); // USB enable
+ dword |= /* (1<<27)|*/(1<<14); // IDE enable
+ pci_write_config32(dev, 0x64, dword);
+
+ byte = pci_read_config8(dev, 0x84);
+ byte |= (1<<0); // SATA enable
+ pci_write_config8(dev, 0x84, byte);
// WDT and cf9 for later in ramstage to call hard_reset
- bcm5785_enable_wdt_port_cf9();
+ bcm5785_enable_wdt_port_cf9();
- bcm5785_enable_msg();
+ bcm5785_enable_msg();
// IDE related
//F0
- byte = pci_read_config8(dev, 0x4e);
- byte |= (1<<4); //enable IDE ext regs
- pci_write_config8(dev, 0x4e, byte);
+ byte = pci_read_config8(dev, 0x4e);
+ byte |= (1<<4); //enable IDE ext regs
+ pci_write_config8(dev, 0x4e, byte);
//F1
- dev = pci_locate_device(PCI_ID(0x1166, 0x0214), 0);
- byte = pci_read_config8(dev, 0x48);
- byte &= ~1; // disable pri channel
- pci_write_config8(dev, 0x48, byte);
- pci_write_config8(dev, 0xb0, 0x01);
- pci_write_config8(dev, 0xb2, 0x02);
- byte = pci_read_config8(dev, 0x06);
- byte |= (1<<4); // so b0, b2 can not be changed from now
- pci_write_config8(dev, 0x06, byte);
- byte = pci_read_config8(dev, 0x49);
- byte |= 1; // enable second channel
- pci_write_config8(dev, 0x49, byte);
+ dev = pci_locate_device(PCI_ID(0x1166, 0x0214), 0);
+ byte = pci_read_config8(dev, 0x48);
+ byte &= ~1; // disable pri channel
+ pci_write_config8(dev, 0x48, byte);
+ pci_write_config8(dev, 0xb0, 0x01);
+ pci_write_config8(dev, 0xb2, 0x02);
+ byte = pci_read_config8(dev, 0x06);
+ byte |= (1<<4); // so b0, b2 can not be changed from now
+ pci_write_config8(dev, 0x06, byte);
+ byte = pci_read_config8(dev, 0x49);
+ byte |= 1; // enable second channel
+ pci_write_config8(dev, 0x49, byte);
//F2
- dev = pci_locate_device(PCI_ID(0x1166, 0x0234), 0);
+ dev = pci_locate_device(PCI_ID(0x1166, 0x0234), 0);
- byte = pci_read_config8(dev, 0x40);
- byte |= (1<<3)|(1<<2); // LPC Retry, LPC to PCI DMA enable
- pci_write_config8(dev, 0x40, byte);
+ byte = pci_read_config8(dev, 0x40);
+ byte |= (1<<3)|(1<<2); // LPC Retry, LPC to PCI DMA enable
+ pci_write_config8(dev, 0x40, byte);
- pci_write_config32(dev, 0x60, 0x0000ffff); // LPC Memory hole start and end
+ pci_write_config32(dev, 0x60, 0x0000ffff); // LPC Memory hole start and end
// USB related
- pci_write_config8(dev, 0x90, 0x40);
- pci_write_config8(dev, 0x92, 0x06);
- pci_write_config8(dev, 0x9c, 0x7c); //PHY timinig register
- pci_write_config8(dev, 0xa4, 0x02); //mask reg - low/full speed func
- pci_write_config8(dev, 0xa5, 0x02); //mask reg - low/full speed func
- pci_write_config8(dev, 0xa6, 0x00); //mask reg - high speed func
- pci_write_config8(dev, 0xb4, 0x40);
+ pci_write_config8(dev, 0x90, 0x40);
+ pci_write_config8(dev, 0x92, 0x06);
+ pci_write_config8(dev, 0x9c, 0x7c); //PHY timinig register
+ pci_write_config8(dev, 0xa4, 0x02); //mask reg - low/full speed func
+ pci_write_config8(dev, 0xa5, 0x02); //mask reg - low/full speed func
+ pci_write_config8(dev, 0xa6, 0x00); //mask reg - high speed func
+ pci_write_config8(dev, 0xb4, 0x40);
}
diff --git a/src/southbridge/broadcom/bcm5785/early_smbus.c b/src/southbridge/broadcom/bcm5785/early_smbus.c
index 9d3d3e8..f37aed9 100644
--- a/src/southbridge/broadcom/bcm5785/early_smbus.c
+++ b/src/southbridge/broadcom/bcm5785/early_smbus.c
@@ -38,20 +38,20 @@ static void enable_smbus(void)
static inline int smbus_recv_byte(unsigned device)
{
- return do_smbus_recv_byte(SMBUS_IO_BASE, device);
+ return do_smbus_recv_byte(SMBUS_IO_BASE, device);
}
static inline int smbus_send_byte(unsigned device, unsigned char val)
{
- return do_smbus_send_byte(SMBUS_IO_BASE, device, val);
+ return do_smbus_send_byte(SMBUS_IO_BASE, device, val);
}
static inline int smbus_read_byte(unsigned device, unsigned address)
{
- return do_smbus_read_byte(SMBUS_IO_BASE, device, address);
+ return do_smbus_read_byte(SMBUS_IO_BASE, device, address);
}
static inline int smbus_write_byte(unsigned device, unsigned address, unsigned char val)
{
- return do_smbus_write_byte(SMBUS_IO_BASE, device, address, val);
+ return do_smbus_write_byte(SMBUS_IO_BASE, device, address, val);
}
diff --git a/src/southbridge/broadcom/bcm5785/ide.c b/src/southbridge/broadcom/bcm5785/ide.c
index 868586c..a6bb204 100644
--- a/src/southbridge/broadcom/bcm5785/ide.c
+++ b/src/southbridge/broadcom/bcm5785/ide.c
@@ -23,13 +23,13 @@
static void bcm5785_ide_read_resources(device_t dev)
{
- /* Get the normal pci resources of this device */
- pci_dev_read_resources(dev);
+ /* Get the normal pci resources of this device */
+ pci_dev_read_resources(dev);
- /* BAR */
- pci_get_resource(dev, 0x64);
+ /* BAR */
+ pci_get_resource(dev, 0x64);
- compact_resources(dev);
+ compact_resources(dev);
}
static void ide_init(struct device *dev)
@@ -38,12 +38,12 @@ static void ide_init(struct device *dev)
static void lpci_set_subsystem(device_t dev, unsigned vendor, unsigned device)
{
- pci_write_config32(dev, 0x40,
- ((device & 0xffff) << 16) | (vendor & 0xffff));
+ pci_write_config32(dev, 0x40,
+ ((device & 0xffff) << 16) | (vendor & 0xffff));
}
static struct pci_operations lops_pci = {
- .set_subsystem = lpci_set_subsystem,
+ .set_subsystem = lpci_set_subsystem,
};
static struct device_operations ide_ops = {
diff --git a/src/southbridge/broadcom/bcm5785/lpc.c b/src/southbridge/broadcom/bcm5785/lpc.c
index f0d7416..6ac4c95 100644
--- a/src/southbridge/broadcom/bcm5785/lpc.c
+++ b/src/southbridge/broadcom/bcm5785/lpc.c
@@ -74,15 +74,15 @@ static void bcm5785_lpc_enable_childrens_resources(device_t dev)
reg = pci_read_config8(dev, 0x44);
for (link = dev->link_list; link; link = link->next) {
- device_t child;
- for (child = link->children; child; child = child->sibling) {
+ device_t child;
+ for (child = link->children; child; child = child->sibling) {
if(child->enabled && (child->path.type == DEVICE_PATH_PNP)) {
struct resource *res;
for(res = child->resource_list; res; res = res->next) {
unsigned long base, end; // don't need long long
if(!(res->flags & IORESOURCE_IO)) continue;
base = res->base;
- end = resource_end(res);
+ end = resource_end(res);
printk(BIOS_DEBUG, "bcm5785lpc decode:%s, base=0x%08lx, end=0x%08lx\n",dev_path(child),base, end);
switch(base) {
case 0x60: //KBC
@@ -103,8 +103,8 @@ static void bcm5785_lpc_enable_childrens_resources(device_t dev)
}
}
}
- }
- }
+ }
+ }
pci_write_config32(dev, 0x44, reg);
@@ -112,18 +112,18 @@ static void bcm5785_lpc_enable_childrens_resources(device_t dev)
static void bcm5785_lpc_enable_resources(device_t dev)
{
- pci_dev_enable_resources(dev);
- bcm5785_lpc_enable_childrens_resources(dev);
+ pci_dev_enable_resources(dev);
+ bcm5785_lpc_enable_childrens_resources(dev);
}
static void lpci_set_subsystem(device_t dev, unsigned vendor, unsigned device)
{
- pci_write_config32(dev, 0x40,
- ((device & 0xffff) << 16) | (vendor & 0xffff));
+ pci_write_config32(dev, 0x40,
+ ((device & 0xffff) << 16) | (vendor & 0xffff));
}
static struct pci_operations lops_pci = {
- .set_subsystem = lpci_set_subsystem,
+ .set_subsystem = lpci_set_subsystem,
};
static struct device_operations lpc_ops = {
diff --git a/src/southbridge/broadcom/bcm5785/reset.c b/src/southbridge/broadcom/bcm5785/reset.c
index 7064b19..8140e01 100644
--- a/src/southbridge/broadcom/bcm5785/reset.c
+++ b/src/southbridge/broadcom/bcm5785/reset.c
@@ -18,24 +18,24 @@
#include <reset.h>
#define PCI_DEV(BUS, DEV, FN) ( \
- (((BUS) & 0xFFF) << 20) | \
- (((DEV) & 0x1F) << 15) | \
- (((FN) & 0x7) << 12))
+ (((BUS) & 0xFFF) << 20) | \
+ (((DEV) & 0x1F) << 15) | \
+ (((FN) & 0x7) << 12))
static void pci_write_config32(pci_devfn_t dev, unsigned where, unsigned value)
{
- unsigned addr;
- addr = (dev>>4) | where;
- outl(0x80000000 | (addr & ~3), 0xCF8);
- outl(value, 0xCFC);
+ unsigned addr;
+ addr = (dev>>4) | where;
+ outl(0x80000000 | (addr & ~3), 0xCF8);
+ outl(value, 0xCFC);
}
static unsigned pci_read_config32(pci_devfn_t dev, unsigned where)
{
- unsigned addr;
- addr = (dev>>4) | where;
- outl(0x80000000 | (addr & ~3), 0xCF8);
- return inl(0xCFC);
+ unsigned addr;
+ addr = (dev>>4) | where;
+ outl(0x80000000 | (addr & ~3), 0xCF8);
+ return inl(0xCFC);
}
#include "../../../northbridge/amd/amdk8/reset_test.c"
@@ -43,7 +43,7 @@ static unsigned pci_read_config32(pci_devfn_t dev, unsigned where)
void hard_reset(void)
{
set_bios_reset();
- /* Try rebooting through port 0xcf9 */
+ /* Try rebooting through port 0xcf9 */
/* Actually it is not a real hard_reset --- it only reset coherent link table, but not reset link freq and width */
outb((0 <<3)|(0<<2)|(1<<1), 0xcf9);
outb((0 <<3)|(1<<2)|(1<<1), 0xcf9);
diff --git a/src/southbridge/broadcom/bcm5785/sata.c b/src/southbridge/broadcom/bcm5785/sata.c
index 75f2d46..571c444 100644
--- a/src/southbridge/broadcom/bcm5785/sata.c
+++ b/src/southbridge/broadcom/bcm5785/sata.c
@@ -28,27 +28,27 @@ static void sata_init(struct device *dev)
uint8_t byte;
u8 *mmio;
- struct resource *res;
- u8 *mmio_base;
+ struct resource *res;
+ u8 *mmio_base;
int i;
if(!(dev->path.pci.devfn & 7)) { // only set it in Func0
byte = pci_read_config8(dev, 0x78);
byte |= (1<<7);
- pci_write_config8(dev, 0x78, byte);
+ pci_write_config8(dev, 0x78, byte);
res = find_resource(dev, 0x24);
- mmio_base = res2mmio(res, 0, 3);
+ mmio_base = res2mmio(res, 0, 3);
write32(mmio_base + 0x10f0, 0x40000001);
write32(mmio_base + 0x8c, 0x00ff2007);
- mdelay( 10 );
+ mdelay( 10 );
write32(mmio_base + 0x8c, 0x78592009);
- mdelay( 10 );
+ mdelay( 10 );
write32(mmio_base + 0x8c, 0x00082004);
- mdelay( 10 );
+ mdelay( 10 );
write32(mmio_base + 0x8c, 0x00002004);
- mdelay( 10 );
+ mdelay( 10 );
//init PHY
@@ -70,12 +70,12 @@ static void sata_init(struct device *dev)
static void lpci_set_subsystem(device_t dev, unsigned vendor, unsigned device)
{
- pci_write_config32(dev, 0x40,
- ((device & 0xffff) << 16) | (vendor & 0xffff));
+ pci_write_config32(dev, 0x40,
+ ((device & 0xffff) << 16) | (vendor & 0xffff));
}
static struct pci_operations lops_pci = {
- .set_subsystem = lpci_set_subsystem,
+ .set_subsystem = lpci_set_subsystem,
};
static struct device_operations sata_ops = {
diff --git a/src/southbridge/broadcom/bcm5785/sb_pci_main.c b/src/southbridge/broadcom/bcm5785/sb_pci_main.c
index 1898ca6..6950f06 100644
--- a/src/southbridge/broadcom/bcm5785/sb_pci_main.c
+++ b/src/southbridge/broadcom/bcm5785/sb_pci_main.c
@@ -63,101 +63,101 @@ static void bcm5785_sb_read_resources(device_t dev)
compact_resources(dev);
- /* Add an extra subtractive resource for both memory and I/O */
- res = new_resource(dev, IOINDEX_SUBTRACTIVE(0, 0));
- res->flags = IORESOURCE_IO | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED;
+ /* Add an extra subtractive resource for both memory and I/O */
+ res = new_resource(dev, IOINDEX_SUBTRACTIVE(0, 0));
+ res->flags = IORESOURCE_IO | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED;
- res = new_resource(dev, IOINDEX_SUBTRACTIVE(1, 0));
- res->flags = IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED;
+ res = new_resource(dev, IOINDEX_SUBTRACTIVE(1, 0));
+ res->flags = IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED;
}
static int lsmbus_recv_byte(device_t dev)
{
- unsigned device;
- struct resource *res;
+ unsigned device;
+ struct resource *res;
struct bus *pbus;
- device = dev->path.i2c.device;
+ device = dev->path.i2c.device;
pbus = get_pbus_smbus(dev);
- res = find_resource(pbus->dev, 0x90);
+ res = find_resource(pbus->dev, 0x90);
- return do_smbus_recv_byte(res->base, device);
+ return do_smbus_recv_byte(res->base, device);
}
static int lsmbus_send_byte(device_t dev, uint8_t val)
{
- unsigned device;
- struct resource *res;
- struct bus *pbus;
+ unsigned device;
+ struct resource *res;
+ struct bus *pbus;
- device = dev->path.i2c.device;
- pbus = get_pbus_smbus(dev);
+ device = dev->path.i2c.device;
+ pbus = get_pbus_smbus(dev);
- res = find_resource(pbus->dev, 0x90);
+ res = find_resource(pbus->dev, 0x90);
- return do_smbus_send_byte(res->base, device, val);
+ return do_smbus_send_byte(res->base, device, val);
}
static int lsmbus_read_byte(device_t dev, uint8_t address)
{
- unsigned device;
- struct resource *res;
- struct bus *pbus;
+ unsigned device;
+ struct resource *res;
+ struct bus *pbus;
- device = dev->path.i2c.device;
- pbus = get_pbus_smbus(dev);
+ device = dev->path.i2c.device;
+ pbus = get_pbus_smbus(dev);
- res = find_resource(pbus->dev, 0x90);
+ res = find_resource(pbus->dev, 0x90);
- return do_smbus_read_byte(res->base, device, address);
+ return do_smbus_read_byte(res->base, device, address);
}
static int lsmbus_write_byte(device_t dev, uint8_t address, uint8_t val)
{
- unsigned device;
- struct resource *res;
- struct bus *pbus;
+ unsigned device;
+ struct resource *res;
+ struct bus *pbus;
- device = dev->path.i2c.device;
- pbus = get_pbus_smbus(dev);
+ device = dev->path.i2c.device;
+ pbus = get_pbus_smbus(dev);
- res = find_resource(pbus->dev, 0x90);
+ res = find_resource(pbus->dev, 0x90);
- return do_smbus_write_byte(res->base, device, address, val);
+ return do_smbus_write_byte(res->base, device, address, val);
}
static struct smbus_bus_operations lops_smbus_bus = {
- .recv_byte = lsmbus_recv_byte,
- .send_byte = lsmbus_send_byte,
- .read_byte = lsmbus_read_byte,
- .write_byte = lsmbus_write_byte,
+ .recv_byte = lsmbus_recv_byte,
+ .send_byte = lsmbus_send_byte,
+ .read_byte = lsmbus_read_byte,
+ .write_byte = lsmbus_write_byte,
};
static void lpci_set_subsystem(device_t dev, unsigned vendor, unsigned device)
{
- pci_write_config32(dev, 0x2c,
- ((device & 0xffff) << 16) | (vendor & 0xffff));
+ pci_write_config32(dev, 0x2c,
+ ((device & 0xffff) << 16) | (vendor & 0xffff));
}
static struct pci_operations lops_pci = {
- .set_subsystem = lpci_set_subsystem,
+ .set_subsystem = lpci_set_subsystem,
};
static struct device_operations sb_ops = {
- .read_resources = bcm5785_sb_read_resources,
- .set_resources = pci_dev_set_resources,
- .enable_resources = pci_dev_enable_resources,
- .init = sb_init,
- .scan_bus = scan_smbus,
+ .read_resources = bcm5785_sb_read_resources,
+ .set_resources = pci_dev_set_resources,
+ .enable_resources = pci_dev_enable_resources,
+ .init = sb_init,
+ .scan_bus = scan_smbus,
// .enable = bcm5785_enable,
- .ops_pci = &lops_pci,
- .ops_smbus_bus = &lops_smbus_bus,
+ .ops_pci = &lops_pci,
+ .ops_smbus_bus = &lops_smbus_bus,
};
static const struct pci_driver sb_driver __pci_driver = {
- .ops = &sb_ops,
- .vendor = PCI_VENDOR_ID_SERVERWORKS,
- .device = PCI_DEVICE_ID_SERVERWORKS_BCM5785_SB_PCI_MAIN,
+ .ops = &sb_ops,
+ .vendor = PCI_VENDOR_ID_SERVERWORKS,
+ .device = PCI_DEVICE_ID_SERVERWORKS_BCM5785_SB_PCI_MAIN,
};
diff --git a/src/southbridge/broadcom/bcm5785/smbus.h b/src/southbridge/broadcom/bcm5785/smbus.h
index bb43269..22545d2 100644
--- a/src/southbridge/broadcom/bcm5785/smbus.h
+++ b/src/southbridge/broadcom/bcm5785/smbus.h
@@ -81,54 +81,54 @@ static int do_smbus_recv_byte(unsigned smbus_io_base, unsigned device)
{
uint8_t byte;
- if (smbus_wait_until_ready(smbus_io_base) < 0) {
- return -2; // not ready
- }
+ if (smbus_wait_until_ready(smbus_io_base) < 0) {
+ return -2; // not ready
+ }
- /* set the device I'm talking too */
- outb(((device & 0x7f) << 1)|1 , smbus_io_base + SMBHSTADDR);
+ /* set the device I'm talking too */
+ outb(((device & 0x7f) << 1)|1 , smbus_io_base + SMBHSTADDR);
- byte = inb(smbus_io_base + SMBHSTCTRL);
- byte &= 0xe3; // Clear [4:2]
- byte |= (1<<2) | (1<<6); // Byte data read/write command, start the command
- outb(byte, smbus_io_base + SMBHSTCTRL);
+ byte = inb(smbus_io_base + SMBHSTCTRL);
+ byte &= 0xe3; // Clear [4:2]
+ byte |= (1<<2) | (1<<6); // Byte data read/write command, start the command
+ outb(byte, smbus_io_base + SMBHSTCTRL);
- /* poll for transaction completion */
- if (smbus_wait_until_done(smbus_io_base) < 0) {
- return -3; // timeout or error
- }
+ /* poll for transaction completion */
+ if (smbus_wait_until_done(smbus_io_base) < 0) {
+ return -3; // timeout or error
+ }
- /* read results of transaction */
- byte = inb(smbus_io_base + SMBHSTCMD);
+ /* read results of transaction */
+ byte = inb(smbus_io_base + SMBHSTCMD);
return byte;
}
static int do_smbus_send_byte(unsigned smbus_io_base, unsigned device, unsigned char val)
{
- uint8_t byte;
+ uint8_t byte;
- if (smbus_wait_until_ready(smbus_io_base) < 0) {
- return -2; // not ready
- }
+ if (smbus_wait_until_ready(smbus_io_base) < 0) {
+ return -2; // not ready
+ }
- /* set the command... */
- outb(val, smbus_io_base + SMBHSTCMD);
+ /* set the command... */
+ outb(val, smbus_io_base + SMBHSTCMD);
- /* set the device I'm talking too */
- outb(((device & 0x7f) << 1)|0 , smbus_io_base + SMBHSTADDR);
+ /* set the device I'm talking too */
+ outb(((device & 0x7f) << 1)|0 , smbus_io_base + SMBHSTADDR);
- byte = inb(smbus_io_base + SMBHSTCTRL);
- byte &= 0xe3; // Clear [4:2]
- byte |= (1<<2) | (1<<6); // Byte data read/write command, start the command
- outb(byte, smbus_io_base + SMBHSTCTRL);
+ byte = inb(smbus_io_base + SMBHSTCTRL);
+ byte &= 0xe3; // Clear [4:2]
+ byte |= (1<<2) | (1<<6); // Byte data read/write command, start the command
+ outb(byte, smbus_io_base + SMBHSTCTRL);
- /* poll for transaction completion */
- if (smbus_wait_until_done(smbus_io_base) < 0) {
- return -3; // timeout or error
- }
+ /* poll for transaction completion */
+ if (smbus_wait_until_done(smbus_io_base) < 0) {
+ return -3; // timeout or error
+ }
- return 0;
+ return 0;
}
static int do_smbus_read_byte(unsigned smbus_io_base, unsigned device, unsigned address)
@@ -142,8 +142,8 @@ static int do_smbus_read_byte(unsigned smbus_io_base, unsigned device, unsigned
/* set the command/address... */
outb(address & 0xff, smbus_io_base + SMBHSTCMD);
- /* set the device I'm talking too */
- outb(((device & 0x7f) << 1)|1 , smbus_io_base + SMBHSTADDR);
+ /* set the device I'm talking too */
+ outb(((device & 0x7f) << 1)|1 , smbus_io_base + SMBHSTADDR);
byte = inb(smbus_io_base + SMBHSTCTRL);
byte &= 0xe3; // Clear [4:2]
@@ -163,30 +163,30 @@ static int do_smbus_read_byte(unsigned smbus_io_base, unsigned device, unsigned
static int do_smbus_write_byte(unsigned smbus_io_base, unsigned device, unsigned address, unsigned char val)
{
- uint8_t byte;
+ uint8_t byte;
- if (smbus_wait_until_ready(smbus_io_base) < 0) {
- return -2; // not ready
- }
+ if (smbus_wait_until_ready(smbus_io_base) < 0) {
+ return -2; // not ready
+ }
- /* set the command/address... */
- outb(address & 0xff, smbus_io_base + SMBHSTCMD);
+ /* set the command/address... */
+ outb(address & 0xff, smbus_io_base + SMBHSTCMD);
- /* set the device I'm talking too */
- outb(((device & 0x7f) << 1)|0 , smbus_io_base + SMBHSTADDR);
+ /* set the device I'm talking too */
+ outb(((device & 0x7f) << 1)|0 , smbus_io_base + SMBHSTADDR);
- /* output value */
- outb(val, smbus_io_base + SMBHSTDAT0);
+ /* output value */
+ outb(val, smbus_io_base + SMBHSTDAT0);
- byte = inb(smbus_io_base + SMBHSTCTRL);
- byte &= 0xe3; // Clear [4:2]
- byte |= (1<<3) | (1<<6); // Byte data read/write command, start the command
- outb(byte, smbus_io_base + SMBHSTCTRL);
+ byte = inb(smbus_io_base + SMBHSTCTRL);
+ byte &= 0xe3; // Clear [4:2]
+ byte |= (1<<3) | (1<<6); // Byte data read/write command, start the command
+ outb(byte, smbus_io_base + SMBHSTCTRL);
- /* poll for transaction completion */
- if (smbus_wait_until_done(smbus_io_base) < 0) {
- return -3; // timeout or error
- }
+ /* poll for transaction completion */
+ if (smbus_wait_until_done(smbus_io_base) < 0) {
+ return -3; // timeout or error
+ }
- return 0;
+ return 0;
}
diff --git a/src/southbridge/broadcom/bcm5785/usb.c b/src/southbridge/broadcom/bcm5785/usb.c
index fa73b2f..9aa64df 100644
--- a/src/southbridge/broadcom/bcm5785/usb.c
+++ b/src/southbridge/broadcom/bcm5785/usb.c
@@ -23,7 +23,7 @@
static void usb_init(struct device *dev)
{
- uint32_t dword;
+ uint32_t dword;
dword = pci_read_config32(dev, 0x04);
dword |= (1<<2)|(1<<1)|(1<<0);
@@ -35,12 +35,12 @@ static void usb_init(struct device *dev)
static void lpci_set_subsystem(device_t dev, unsigned vendor, unsigned device)
{
- pci_write_config32(dev, 0x40,
- ((device & 0xffff) << 16) | (vendor & 0xffff));
+ pci_write_config32(dev, 0x40,
+ ((device & 0xffff) << 16) | (vendor & 0xffff));
}
static struct pci_operations lops_pci = {
- .set_subsystem = lpci_set_subsystem,
+ .set_subsystem = lpci_set_subsystem,
};
static struct device_operations usb_ops = {
diff --git a/src/southbridge/intel/bd82x6x/me.c b/src/southbridge/intel/bd82x6x/me.c
index 83c99e0..23915c3 100644
--- a/src/southbridge/intel/bd82x6x/me.c
+++ b/src/southbridge/intel/bd82x6x/me.c
@@ -445,7 +445,7 @@ static int mkhi_get_fwcaps(void)
print_cap("IntelR Power Sharing Technology (MPC)",
cap.caps_sku.intel_mpc);
print_cap("ICC Over Clocking", cap.caps_sku.icc_over_clocking);
- print_cap("Protected Audio Video Path (PAVP)", cap.caps_sku.pavp);
+ print_cap("Protected Audio Video Path (PAVP)", cap.caps_sku.pavp);
print_cap("IPV6", cap.caps_sku.ipv6);
print_cap("KVM Remote Control (KVM)", cap.caps_sku.kvm);
print_cap("Outbreak Containment Heuristic (OCH)", cap.caps_sku.och);
diff --git a/src/southbridge/intel/bd82x6x/pch.h b/src/southbridge/intel/bd82x6x/pch.h
index f22fed5..a4866e7 100644
--- a/src/southbridge/intel/bd82x6x/pch.h
+++ b/src/southbridge/intel/bd82x6x/pch.h
@@ -289,7 +289,7 @@ early_usb_init (const struct southbridge_usb_port *portmap);
#define RCBA32(x) *((volatile u32 *)(DEFAULT_RCBA + x))
#define RCBA_AND_OR(bits, x, and, or) \
- RCBA##bits(x) = ((RCBA##bits(x) & (and)) | (or))
+ RCBA##bits(x) = ((RCBA##bits(x) & (and)) | (or))
#define RCBA8_AND_OR(x, and, or) RCBA_AND_OR(8, x, and, or)
#define RCBA16_AND_OR(x, and, or) RCBA_AND_OR(16, x, and, or)
#define RCBA32_AND_OR(x, and, or) RCBA_AND_OR(32, x, and, or)
@@ -426,7 +426,7 @@ early_usb_init (const struct southbridge_usb_port *portmap);
#define DIR_ROUTE(x,a,b,c,d) \
RCBA32(x) = (((d) << DIR_IDR) | ((c) << DIR_ICR) | \
- ((b) << DIR_IBR) | ((a) << DIR_IAR))
+ ((b) << DIR_IBR) | ((a) << DIR_IAR))
#define RC 0x3400 /* 32bit */
#define HPTC 0x3404 /* 32bit */
diff --git a/src/southbridge/intel/bd82x6x/reset.c b/src/southbridge/intel/bd82x6x/reset.c
index daabbbc..804fb81 100644
--- a/src/southbridge/intel/bd82x6x/reset.c
+++ b/src/southbridge/intel/bd82x6x/reset.c
@@ -19,10 +19,10 @@
void soft_reset(void)
{
- outb(0x04, 0xcf9);
+ outb(0x04, 0xcf9);
}
void hard_reset(void)
{
- outb(0x06, 0xcf9);
+ outb(0x06, 0xcf9);
}
diff --git a/src/southbridge/intel/bd82x6x/smihandler.c b/src/southbridge/intel/bd82x6x/smihandler.c
index e4e5b81..4a0149f 100644
--- a/src/southbridge/intel/bd82x6x/smihandler.c
+++ b/src/southbridge/intel/bd82x6x/smihandler.c
@@ -271,37 +271,37 @@ void southbridge_smi_set_eos(void)
static void busmaster_disable_on_bus(int bus)
{
- int slot, func;
- unsigned int val;
- unsigned char hdr;
-
- for (slot = 0; slot < 0x20; slot++) {
- for (func = 0; func < 8; func++) {
- u32 reg32;
- device_t dev = PCI_DEV(bus, slot, func);
-
- val = pci_read_config32(dev, PCI_VENDOR_ID);
-
- if (val == 0xffffffff || val == 0x00000000 ||
- val == 0x0000ffff || val == 0xffff0000)
- continue;
-
- /* Disable Bus Mastering for this one device */
- reg32 = pci_read_config32(dev, PCI_COMMAND);
- reg32 &= ~PCI_COMMAND_MASTER;
- pci_write_config32(dev, PCI_COMMAND, reg32);
-
- /* If this is a bridge, then follow it. */
- hdr = pci_read_config8(dev, PCI_HEADER_TYPE);
- hdr &= 0x7f;
- if (hdr == PCI_HEADER_TYPE_BRIDGE ||
- hdr == PCI_HEADER_TYPE_CARDBUS) {
- unsigned int buses;
- buses = pci_read_config32(dev, PCI_PRIMARY_BUS);
- busmaster_disable_on_bus((buses >> 8) & 0xff);
- }
- }
- }
+ int slot, func;
+ unsigned int val;
+ unsigned char hdr;
+
+ for (slot = 0; slot < 0x20; slot++) {
+ for (func = 0; func < 8; func++) {
+ u32 reg32;
+ device_t dev = PCI_DEV(bus, slot, func);
+
+ val = pci_read_config32(dev, PCI_VENDOR_ID);
+
+ if (val == 0xffffffff || val == 0x00000000 ||
+ val == 0x0000ffff || val == 0xffff0000)
+ continue;
+
+ /* Disable Bus Mastering for this one device */
+ reg32 = pci_read_config32(dev, PCI_COMMAND);
+ reg32 &= ~PCI_COMMAND_MASTER;
+ pci_write_config32(dev, PCI_COMMAND, reg32);
+
+ /* If this is a bridge, then follow it. */
+ hdr = pci_read_config8(dev, PCI_HEADER_TYPE);
+ hdr &= 0x7f;
+ if (hdr == PCI_HEADER_TYPE_BRIDGE ||
+ hdr == PCI_HEADER_TYPE_CARDBUS) {
+ unsigned int buses;
+ buses = pci_read_config32(dev, PCI_PRIMARY_BUS);
+ busmaster_disable_on_bus((buses >> 8) & 0xff);
+ }
+ }
+ }
}
static void southbridge_gate_memory_reset_real(int offset,
diff --git a/src/southbridge/intel/fsp_bd82x6x/me.c b/src/southbridge/intel/fsp_bd82x6x/me.c
index 68a9ee5..a951f9f 100644
--- a/src/southbridge/intel/fsp_bd82x6x/me.c
+++ b/src/southbridge/intel/fsp_bd82x6x/me.c
@@ -444,7 +444,7 @@ static int mkhi_get_fwcaps(void)
print_cap("IntelR Power Sharing Technology (MPC)",
cap.caps_sku.intel_mpc);
print_cap("ICC Over Clocking", cap.caps_sku.icc_over_clocking);
- print_cap("Protected Audio Video Path (PAVP)", cap.caps_sku.pavp);
+ print_cap("Protected Audio Video Path (PAVP)", cap.caps_sku.pavp);
print_cap("IPV6", cap.caps_sku.ipv6);
print_cap("KVM Remote Control (KVM)", cap.caps_sku.kvm);
print_cap("Outbreak Containment Heuristic (OCH)", cap.caps_sku.och);
diff --git a/src/southbridge/intel/fsp_bd82x6x/me_8.x.c b/src/southbridge/intel/fsp_bd82x6x/me_8.x.c
index e29d86b..b7edd77 100644
--- a/src/southbridge/intel/fsp_bd82x6x/me_8.x.c
+++ b/src/southbridge/intel/fsp_bd82x6x/me_8.x.c
@@ -389,7 +389,7 @@ static int mkhi_get_fwcaps(mefwcaps_sku *cap)
< 0) {
printk(BIOS_ERR, "ME: GET FWCAPS message failed\n");
return -1;
- }
+ }
*cap = cap_msg.caps_sku;
return 0;
}
@@ -413,7 +413,7 @@ static void me_print_fwcaps(mbp_fw_caps *caps_section)
print_cap("IntelR Capability Licensing Service (CLS)", cap->intel_cls);
print_cap("IntelR Power Sharing Technology (MPC)", cap->intel_mpc);
print_cap("ICC Over Clocking", cap->icc_over_clocking);
- print_cap("Protected Audio Video Path (PAVP)", cap->pavp);
+ print_cap("Protected Audio Video Path (PAVP)", cap->pavp);
print_cap("IPV6", cap->ipv6);
print_cap("KVM Remote Control (KVM)", cap->kvm);
print_cap("Outbreak Containment Heuristic (OCH)", cap->och);
diff --git a/src/southbridge/intel/fsp_bd82x6x/pch.h b/src/southbridge/intel/fsp_bd82x6x/pch.h
index 7fe40f7..0c34449 100644
--- a/src/southbridge/intel/fsp_bd82x6x/pch.h
+++ b/src/southbridge/intel/fsp_bd82x6x/pch.h
@@ -271,7 +271,7 @@ void display_fd_settings(void);
#define RCBA32(x) *((volatile u32 *)(DEFAULT_RCBA + x))
#define RCBA_AND_OR(bits, x, and, or) \
- RCBA##bits(x) = ((RCBA##bits(x) & (and)) | (or))
+ RCBA##bits(x) = ((RCBA##bits(x) & (and)) | (or))
#define RCBA8_AND_OR(x, and, or) RCBA_AND_OR(8, x, and, or)
#define RCBA16_AND_OR(x, and, or) RCBA_AND_OR(16, x, and, or)
#define RCBA32_AND_OR(x, and, or) RCBA_AND_OR(32, x, and, or)
@@ -408,7 +408,7 @@ void display_fd_settings(void);
#define DIR_ROUTE(x,a,b,c,d) \
RCBA32(x) = (((d) << DIR_IDR) | ((c) << DIR_ICR) | \
- ((b) << DIR_IBR) | ((a) << DIR_IAR))
+ ((b) << DIR_IBR) | ((a) << DIR_IAR))
#define RC 0x3400 /* 32bit */
#define HPTC 0x3404 /* 32bit */
diff --git a/src/southbridge/intel/fsp_bd82x6x/reset.c b/src/southbridge/intel/fsp_bd82x6x/reset.c
index c2e76d5..a2e8236 100644
--- a/src/southbridge/intel/fsp_bd82x6x/reset.c
+++ b/src/southbridge/intel/fsp_bd82x6x/reset.c
@@ -20,10 +20,10 @@
void soft_reset(void)
{
- outb(0x04, 0xcf9);
+ outb(0x04, 0xcf9);
}
void hard_reset(void)
{
- outb(0x06, 0xcf9);
+ outb(0x06, 0xcf9);
}
diff --git a/src/southbridge/intel/fsp_bd82x6x/smihandler.c b/src/southbridge/intel/fsp_bd82x6x/smihandler.c
index 987d6d1..2eec026 100644
--- a/src/southbridge/intel/fsp_bd82x6x/smihandler.c
+++ b/src/southbridge/intel/fsp_bd82x6x/smihandler.c
@@ -235,37 +235,37 @@ void southbridge_smi_set_eos(void)
static void busmaster_disable_on_bus(int bus)
{
- int slot, func;
- unsigned int val;
- unsigned char hdr;
-
- for (slot = 0; slot < 0x20; slot++) {
- for (func = 0; func < 8; func++) {
- u32 reg32;
- device_t dev = PCI_DEV(bus, slot, func);
-
- val = pci_read_config32(dev, PCI_VENDOR_ID);
-
- if (val == 0xffffffff || val == 0x00000000 ||
- val == 0x0000ffff || val == 0xffff0000)
- continue;
-
- /* Disable Bus Mastering for this one device */
- reg32 = pci_read_config32(dev, PCI_COMMAND);
- reg32 &= ~PCI_COMMAND_MASTER;
- pci_write_config32(dev, PCI_COMMAND, reg32);
-
- /* If this is a bridge, then follow it. */
- hdr = pci_read_config8(dev, PCI_HEADER_TYPE);
- hdr &= 0x7f;
- if (hdr == PCI_HEADER_TYPE_BRIDGE ||
- hdr == PCI_HEADER_TYPE_CARDBUS) {
- unsigned int buses;
- buses = pci_read_config32(dev, PCI_PRIMARY_BUS);
- busmaster_disable_on_bus((buses >> 8) & 0xff);
- }
- }
- }
+ int slot, func;
+ unsigned int val;
+ unsigned char hdr;
+
+ for (slot = 0; slot < 0x20; slot++) {
+ for (func = 0; func < 8; func++) {
+ u32 reg32;
+ device_t dev = PCI_DEV(bus, slot, func);
+
+ val = pci_read_config32(dev, PCI_VENDOR_ID);
+
+ if (val == 0xffffffff || val == 0x00000000 ||
+ val == 0x0000ffff || val == 0xffff0000)
+ continue;
+
+ /* Disable Bus Mastering for this one device */
+ reg32 = pci_read_config32(dev, PCI_COMMAND);
+ reg32 &= ~PCI_COMMAND_MASTER;
+ pci_write_config32(dev, PCI_COMMAND, reg32);
+
+ /* If this is a bridge, then follow it. */
+ hdr = pci_read_config8(dev, PCI_HEADER_TYPE);
+ hdr &= 0x7f;
+ if (hdr == PCI_HEADER_TYPE_BRIDGE ||
+ hdr == PCI_HEADER_TYPE_CARDBUS) {
+ unsigned int buses;
+ buses = pci_read_config32(dev, PCI_PRIMARY_BUS);
+ busmaster_disable_on_bus((buses >> 8) & 0xff);
+ }
+ }
+ }
}
/*
diff --git a/src/southbridge/intel/fsp_i89xx/me.c b/src/southbridge/intel/fsp_i89xx/me.c
index caf24e3..7ea42d4 100644
--- a/src/southbridge/intel/fsp_i89xx/me.c
+++ b/src/southbridge/intel/fsp_i89xx/me.c
@@ -444,7 +444,7 @@ static int mkhi_get_fwcaps(void)
print_cap("IntelR Power Sharing Technology (MPC)",
cap.caps_sku.intel_mpc);
print_cap("ICC Over Clocking", cap.caps_sku.icc_over_clocking);
- print_cap("Protected Audio Video Path (PAVP)", cap.caps_sku.pavp);
+ print_cap("Protected Audio Video Path (PAVP)", cap.caps_sku.pavp);
print_cap("IPV6", cap.caps_sku.ipv6);
print_cap("KVM Remote Control (KVM)", cap.caps_sku.kvm);
print_cap("Outbreak Containment Heuristic (OCH)", cap.caps_sku.och);
diff --git a/src/southbridge/intel/fsp_i89xx/me_8.x.c b/src/southbridge/intel/fsp_i89xx/me_8.x.c
index 090d8d0..fc14020 100644
--- a/src/southbridge/intel/fsp_i89xx/me_8.x.c
+++ b/src/southbridge/intel/fsp_i89xx/me_8.x.c
@@ -413,7 +413,7 @@ static void me_print_fwcaps(mbp_fw_caps *caps_section)
print_cap("IntelR Capability Licensing Service (CLS)", cap->intel_cls);
print_cap("IntelR Power Sharing Technology (MPC)", cap->intel_mpc);
print_cap("ICC Over Clocking", cap->icc_over_clocking);
- print_cap("Protected Audio Video Path (PAVP)", cap->pavp);
+ print_cap("Protected Audio Video Path (PAVP)", cap->pavp);
print_cap("IPV6", cap->ipv6);
print_cap("KVM Remote Control (KVM)", cap->kvm);
print_cap("Outbreak Containment Heuristic (OCH)", cap->och);
diff --git a/src/southbridge/intel/fsp_i89xx/pch.h b/src/southbridge/intel/fsp_i89xx/pch.h
index 6d8b873..ed9a3b3 100644
--- a/src/southbridge/intel/fsp_i89xx/pch.h
+++ b/src/southbridge/intel/fsp_i89xx/pch.h
@@ -204,7 +204,7 @@ void early_pch_init(void);
#define RCBA32(x) *((volatile u32 *)(DEFAULT_RCBA + x))
#define RCBA_AND_OR(bits, x, and, or) \
- RCBA##bits(x) = ((RCBA##bits(x) & (and)) | (or))
+ RCBA##bits(x) = ((RCBA##bits(x) & (and)) | (or))
#define RCBA8_AND_OR(x, and, or) RCBA_AND_OR(8, x, and, or)
#define RCBA16_AND_OR(x, and, or) RCBA_AND_OR(16, x, and, or)
#define RCBA32_AND_OR(x, and, or) RCBA_AND_OR(32, x, and, or)
diff --git a/src/southbridge/intel/fsp_i89xx/smihandler.c b/src/southbridge/intel/fsp_i89xx/smihandler.c
index e0d19d6..d8cbed2 100644
--- a/src/southbridge/intel/fsp_i89xx/smihandler.c
+++ b/src/southbridge/intel/fsp_i89xx/smihandler.c
@@ -235,37 +235,37 @@ void southbridge_smi_set_eos(void)
static void busmaster_disable_on_bus(int bus)
{
- int slot, func;
- unsigned int val;
- unsigned char hdr;
-
- for (slot = 0; slot < 0x20; slot++) {
- for (func = 0; func < 8; func++) {
- u32 reg32;
- device_t dev = PCI_DEV(bus, slot, func);
-
- val = pci_read_config32(dev, PCI_VENDOR_ID);
-
- if (val == 0xffffffff || val == 0x00000000 ||
- val == 0x0000ffff || val == 0xffff0000)
- continue;
-
- /* Disable Bus Mastering for this one device */
- reg32 = pci_read_config32(dev, PCI_COMMAND);
- reg32 &= ~PCI_COMMAND_MASTER;
- pci_write_config32(dev, PCI_COMMAND, reg32);
-
- /* If this is a bridge, then follow it. */
- hdr = pci_read_config8(dev, PCI_HEADER_TYPE);
- hdr &= 0x7f;
- if (hdr == PCI_HEADER_TYPE_BRIDGE ||
- hdr == PCI_HEADER_TYPE_CARDBUS) {
- unsigned int buses;
- buses = pci_read_config32(dev, PCI_PRIMARY_BUS);
- busmaster_disable_on_bus((buses >> 8) & 0xff);
- }
- }
- }
+ int slot, func;
+ unsigned int val;
+ unsigned char hdr;
+
+ for (slot = 0; slot < 0x20; slot++) {
+ for (func = 0; func < 8; func++) {
+ u32 reg32;
+ device_t dev = PCI_DEV(bus, slot, func);
+
+ val = pci_read_config32(dev, PCI_VENDOR_ID);
+
+ if (val == 0xffffffff || val == 0x00000000 ||
+ val == 0x0000ffff || val == 0xffff0000)
+ continue;
+
+ /* Disable Bus Mastering for this one device */
+ reg32 = pci_read_config32(dev, PCI_COMMAND);
+ reg32 &= ~PCI_COMMAND_MASTER;
+ pci_write_config32(dev, PCI_COMMAND, reg32);
+
+ /* If this is a bridge, then follow it. */
+ hdr = pci_read_config8(dev, PCI_HEADER_TYPE);
+ hdr &= 0x7f;
+ if (hdr == PCI_HEADER_TYPE_BRIDGE ||
+ hdr == PCI_HEADER_TYPE_CARDBUS) {
+ unsigned int buses;
+ buses = pci_read_config32(dev, PCI_PRIMARY_BUS);
+ busmaster_disable_on_bus((buses >> 8) & 0xff);
+ }
+ }
+ }
}
/*
diff --git a/src/southbridge/intel/fsp_rangeley/lpc.c b/src/southbridge/intel/fsp_rangeley/lpc.c
index 3a144ea..8201a1d 100644
--- a/src/southbridge/intel/fsp_rangeley/lpc.c
+++ b/src/southbridge/intel/fsp_rangeley/lpc.c
@@ -465,7 +465,7 @@ static struct device_operations device_ops = {
/* IDs for LPC device of Intel 89xx Series Chipset */
static const unsigned short pci_device_ids[] = { 0x1F38, 0x1F39, 0x1F3A, 0x1F3B,
- 0 };
+ 0 };
static const struct pci_driver soc_lpc __pci_driver = {
.ops = &device_ops,
diff --git a/src/southbridge/intel/fsp_rangeley/sata.c b/src/southbridge/intel/fsp_rangeley/sata.c
index 4861f83..72a2a55 100644
--- a/src/southbridge/intel/fsp_rangeley/sata.c
+++ b/src/southbridge/intel/fsp_rangeley/sata.c
@@ -121,8 +121,8 @@ static struct device_operations sata_ops = {
};
static const unsigned short pci_device_ids[] = { 0x1f20, 0x1f21, 0x1f22, 0x1f23,
- 0x1f30, 0x1f31, 0x1f32, 0x1f33,
- 0 };
+ 0x1f30, 0x1f31, 0x1f32, 0x1f33,
+ 0 };
static const struct pci_driver soc_sata __pci_driver = {
.ops = &sata_ops,
diff --git a/src/southbridge/intel/fsp_rangeley/soc.h b/src/southbridge/intel/fsp_rangeley/soc.h
index 0674dca..388209a 100644
--- a/src/southbridge/intel/fsp_rangeley/soc.h
+++ b/src/southbridge/intel/fsp_rangeley/soc.h
@@ -200,7 +200,7 @@ void rangeley_sb_early_initialization(void);
#define RCBA32(x) *((volatile u32 *)(DEFAULT_RCBA + x))
#define RCBA_AND_OR(bits, x, and, or) \
- RCBA##bits(x) = ((RCBA##bits(x) & (and)) | (or))
+ RCBA##bits(x) = ((RCBA##bits(x) & (and)) | (or))
#define RCBA8_AND_OR(x, and, or) RCBA_AND_OR(8, x, and, or)
#define RCBA16_AND_OR(x, and, or) RCBA_AND_OR(16, x, and, or)
#define RCBA32_AND_OR(x, and, or) RCBA_AND_OR(32, x, and, or)
@@ -248,7 +248,7 @@ void rangeley_sb_early_initialization(void);
#define DIR_ROUTE(x,a,b,c,d) \
RCBA32(x) = (((d) << DIR_IDR) | ((c) << DIR_ICR) | \
- ((b) << DIR_IBR) | ((a) << DIR_IAR))
+ ((b) << DIR_IBR) | ((a) << DIR_IAR))
/* PBASE Registers */
#define PMC_CFG 0x08
diff --git a/src/southbridge/intel/i3100/early_smbus.c b/src/southbridge/intel/i3100/early_smbus.c
index 12a9202..2cb241a 100644
--- a/src/southbridge/intel/i3100/early_smbus.c
+++ b/src/southbridge/intel/i3100/early_smbus.c
@@ -27,7 +27,7 @@ static void enable_smbus(void)
pci_write_config8(dev, 0x40, 1);
pci_write_config8(dev, 0x4, 1);
/* SMBALERT_DIS */
- outb(4, SMBUS_IO_BASE + SMBSLVCMD);
+ outb(4, SMBUS_IO_BASE + SMBSLVCMD);
/* Disable interrupt generation */
outb(0, SMBUS_IO_BASE + SMBHSTCTL);
diff --git a/src/southbridge/intel/i3100/lpc.c b/src/southbridge/intel/i3100/lpc.c
index 4d529ca..355b0d4 100644
--- a/src/southbridge/intel/i3100/lpc.c
+++ b/src/southbridge/intel/i3100/lpc.c
@@ -206,19 +206,19 @@ static void i3100_pirq_init(device_t dev)
if(config->pirq_e_h)
pci_write_config32(dev, 0x68, config->pirq_e_h);
- for(irq_dev = all_devices; irq_dev; irq_dev = irq_dev->next) {
- u8 int_pin=0, int_line=0;
+ for(irq_dev = all_devices; irq_dev; irq_dev = irq_dev->next) {
+ u8 int_pin=0, int_line=0;
- if (!irq_dev->enabled || irq_dev->path.type != DEVICE_PATH_PCI)
- continue;
+ if (!irq_dev->enabled || irq_dev->path.type != DEVICE_PATH_PCI)
+ continue;
- int_pin = pci_read_config8(irq_dev, PCI_INTERRUPT_PIN);
- switch (int_pin) {
- case 1: /* INTA# */
+ int_pin = pci_read_config8(irq_dev, PCI_INTERRUPT_PIN);
+ switch (int_pin) {
+ case 1: /* INTA# */
int_line = config->pirq_a_d & 0xff;
break;
- case 2: /* INTB# */
+ case 2: /* INTB# */
int_line = (config->pirq_a_d >> 8) & 0xff;
break;
@@ -226,17 +226,17 @@ static void i3100_pirq_init(device_t dev)
int_line = (config->pirq_a_d >> 16) & 0xff;
break;
- case 4: /* INTD# */
+ case 4: /* INTD# */
int_line = (config->pirq_a_d >> 24) & 0xff;
break;
- }
+ }
- if (!int_line)
- continue;
+ if (!int_line)
+ continue;
printk(BIOS_DEBUG, "%s: irq pin %d, irq line %d\n", dev_path(irq_dev), int_pin, int_line);
- pci_write_config8(irq_dev, PCI_INTERRUPT_LINE, int_line);
- }
+ pci_write_config8(irq_dev, PCI_INTERRUPT_LINE, int_line);
+ }
}
diff --git a/src/southbridge/intel/i82801dx/smihandler.c b/src/southbridge/intel/i82801dx/smihandler.c
index 326a9e5..1eae32d 100644
--- a/src/southbridge/intel/i82801dx/smihandler.c
+++ b/src/southbridge/intel/i82801dx/smihandler.c
@@ -233,37 +233,37 @@ void southbridge_smi_set_eos(void)
static void busmaster_disable_on_bus(int bus)
{
- int slot, func;
- unsigned int val;
- unsigned char hdr;
-
- for (slot = 0; slot < 0x20; slot++) {
- for (func = 0; func < 8; func++) {
- u32 reg32;
- device_t dev = PCI_DEV(bus, slot, func);
-
- val = pci_read_config32(dev, PCI_VENDOR_ID);
-
- if (val == 0xffffffff || val == 0x00000000 ||
- val == 0x0000ffff || val == 0xffff0000)
- continue;
-
- /* Disable Bus Mastering for this one device */
- reg32 = pci_read_config32(dev, PCI_COMMAND);
- reg32 &= ~PCI_COMMAND_MASTER;
- pci_write_config32(dev, PCI_COMMAND, reg32);
-
- /* If this is a bridge, then follow it. */
- hdr = pci_read_config8(dev, PCI_HEADER_TYPE);
- hdr &= 0x7f;
- if (hdr == PCI_HEADER_TYPE_BRIDGE ||
- hdr == PCI_HEADER_TYPE_CARDBUS) {
- unsigned int buses;
- buses = pci_read_config32(dev, PCI_PRIMARY_BUS);
- busmaster_disable_on_bus((buses >> 8) & 0xff);
- }
- }
- }
+ int slot, func;
+ unsigned int val;
+ unsigned char hdr;
+
+ for (slot = 0; slot < 0x20; slot++) {
+ for (func = 0; func < 8; func++) {
+ u32 reg32;
+ device_t dev = PCI_DEV(bus, slot, func);
+
+ val = pci_read_config32(dev, PCI_VENDOR_ID);
+
+ if (val == 0xffffffff || val == 0x00000000 ||
+ val == 0x0000ffff || val == 0xffff0000)
+ continue;
+
+ /* Disable Bus Mastering for this one device */
+ reg32 = pci_read_config32(dev, PCI_COMMAND);
+ reg32 &= ~PCI_COMMAND_MASTER;
+ pci_write_config32(dev, PCI_COMMAND, reg32);
+
+ /* If this is a bridge, then follow it. */
+ hdr = pci_read_config8(dev, PCI_HEADER_TYPE);
+ hdr &= 0x7f;
+ if (hdr == PCI_HEADER_TYPE_BRIDGE ||
+ hdr == PCI_HEADER_TYPE_CARDBUS) {
+ unsigned int buses;
+ buses = pci_read_config32(dev, PCI_PRIMARY_BUS);
+ busmaster_disable_on_bus((buses >> 8) & 0xff);
+ }
+ }
+ }
}
diff --git a/src/southbridge/intel/i82801ex/lpc.c b/src/southbridge/intel/i82801ex/lpc.c
index 630484a..4ff3fb5 100644
--- a/src/southbridge/intel/i82801ex/lpc.c
+++ b/src/southbridge/intel/i82801ex/lpc.c
@@ -78,8 +78,8 @@ static void i82801ex_pci_dma_cfg(device_t dev)
#define LPC_EN 0xe6
static void i82801ex_enable_lpc(device_t dev)
{
- /* lpc i/f enable */
- pci_write_config8(dev, LPC_EN, 0x0d);
+ /* lpc i/f enable */
+ pci_write_config8(dev, LPC_EN, 0x0d);
}
typedef struct southbridge_intel_i82801ex_config config_t;
@@ -292,7 +292,7 @@ static void lpc_init(struct device *dev)
/* Clear SATA to non raid */
pci_write_config8(dev, 0xae, 0x00);
- get_option(&pwr_on, "power_on_after_fail");
+ get_option(&pwr_on, "power_on_after_fail");
byte = pci_read_config8(dev, 0xa4);
byte &= 0xfe;
if (!pwr_on) {
diff --git a/src/southbridge/intel/i82801ex/reset.c b/src/southbridge/intel/i82801ex/reset.c
index 9936892..8036ffd 100644
--- a/src/southbridge/intel/i82801ex/reset.c
+++ b/src/southbridge/intel/i82801ex/reset.c
@@ -3,6 +3,6 @@
void hard_reset(void)
{
- /* Try rebooting through port 0xcf9 */
- outb((0 <<3)|(1<<2)|(1<<1), 0xcf9);
+ /* Try rebooting through port 0xcf9 */
+ outb((0 <<3)|(1<<2)|(1<<1), 0xcf9);
}
diff --git a/src/southbridge/intel/i82801ex/watchdog.c b/src/southbridge/intel/i82801ex/watchdog.c
index 28e1f5e..6aba270 100644
--- a/src/southbridge/intel/i82801ex/watchdog.c
+++ b/src/southbridge/intel/i82801ex/watchdog.c
@@ -6,23 +6,23 @@
void watchdog_off(void)
{
- device_t dev;
- unsigned long value,base;
+ device_t dev;
+ unsigned long value,base;
/* turn off the ICH5 watchdog */
- dev = dev_find_slot(0, PCI_DEVFN(0x1f,0));
- /* Enable I/O space */
- value = pci_read_config16(dev, 0x04);
- value |= (1 << 10);
- pci_write_config16(dev, 0x04, value);
- /* Get TCO base */
- base = (pci_read_config32(dev, 0x40) & 0x0fffe) + 0x60;
- /* Disable the watchdog timer */
- value = inw(base + 0x08);
- value |= 1 << 11;
- outw(value, base + 0x08);
- /* Clear TCO timeout status */
- outw(0x0008, base + 0x04);
- outw(0x0002, base + 0x06);
- printk(BIOS_DEBUG, "Watchdog ICH5 disabled\n");
+ dev = dev_find_slot(0, PCI_DEVFN(0x1f,0));
+ /* Enable I/O space */
+ value = pci_read_config16(dev, 0x04);
+ value |= (1 << 10);
+ pci_write_config16(dev, 0x04, value);
+ /* Get TCO base */
+ base = (pci_read_config32(dev, 0x40) & 0x0fffe) + 0x60;
+ /* Disable the watchdog timer */
+ value = inw(base + 0x08);
+ value |= 1 << 11;
+ outw(value, base + 0x08);
+ /* Clear TCO timeout status */
+ outw(0x0008, base + 0x04);
+ outw(0x0002, base + 0x06);
+ printk(BIOS_DEBUG, "Watchdog ICH5 disabled\n");
}
diff --git a/src/southbridge/intel/i82801gx/bootblock.c b/src/southbridge/intel/i82801gx/bootblock.c
index 50268b6..c9c19a3 100644
--- a/src/southbridge/intel/i82801gx/bootblock.c
+++ b/src/southbridge/intel/i82801gx/bootblock.c
@@ -30,22 +30,22 @@ static void store_initial_timestamp(void)
static void enable_spi_prefetch(void)
{
- u8 reg8;
- pci_devfn_t dev;
+ u8 reg8;
+ pci_devfn_t dev;
- dev = PCI_DEV(0, 0x1f, 0);
+ dev = PCI_DEV(0, 0x1f, 0);
- reg8 = pci_read_config8(dev, 0xdc);
- reg8 &= ~(3 << 2);
- reg8 |= (2 << 2); /* Prefetching and Caching Enabled */
- pci_write_config8(dev, 0xdc, reg8);
+ reg8 = pci_read_config8(dev, 0xdc);
+ reg8 &= ~(3 << 2);
+ reg8 |= (2 << 2); /* Prefetching and Caching Enabled */
+ pci_write_config8(dev, 0xdc, reg8);
}
static void bootblock_southbridge_init(void)
{
store_initial_timestamp();
- enable_spi_prefetch();
+ enable_spi_prefetch();
/* Enable RCBA */
pci_write_config32(PCI_DEV(0, 0x1f, 0), RCBA, (uintptr_t)DEFAULT_RCBA | 1);
diff --git a/src/southbridge/intel/i82801gx/reset.c b/src/southbridge/intel/i82801gx/reset.c
index 39c4f31..97b8225 100644
--- a/src/southbridge/intel/i82801gx/reset.c
+++ b/src/southbridge/intel/i82801gx/reset.c
@@ -19,7 +19,7 @@
void soft_reset(void)
{
- outb(0x04, 0xcf9);
+ outb(0x04, 0xcf9);
}
#if 0
@@ -32,6 +32,6 @@ void hard_reset(void)
void hard_reset(void)
{
- outb(0x02, 0xcf9);
- outb(0x06, 0xcf9);
+ outb(0x02, 0xcf9);
+ outb(0x06, 0xcf9);
}
diff --git a/src/southbridge/intel/i82801gx/smihandler.c b/src/southbridge/intel/i82801gx/smihandler.c
index b128280..609355c 100644
--- a/src/southbridge/intel/i82801gx/smihandler.c
+++ b/src/southbridge/intel/i82801gx/smihandler.c
@@ -269,37 +269,37 @@ void southbridge_smi_set_eos(void)
static void busmaster_disable_on_bus(int bus)
{
- int slot, func;
- unsigned int val;
- unsigned char hdr;
-
- for (slot = 0; slot < 0x20; slot++) {
- for (func = 0; func < 8; func++) {
- u32 reg32;
- device_t dev = PCI_DEV(bus, slot, func);
-
- val = pci_read_config32(dev, PCI_VENDOR_ID);
-
- if (val == 0xffffffff || val == 0x00000000 ||
- val == 0x0000ffff || val == 0xffff0000)
- continue;
-
- /* Disable Bus Mastering for this one device */
- reg32 = pci_read_config32(dev, PCI_COMMAND);
- reg32 &= ~PCI_COMMAND_MASTER;
- pci_write_config32(dev, PCI_COMMAND, reg32);
-
- /* If this is a bridge, then follow it. */
- hdr = pci_read_config8(dev, PCI_HEADER_TYPE);
- hdr &= 0x7f;
- if (hdr == PCI_HEADER_TYPE_BRIDGE ||
- hdr == PCI_HEADER_TYPE_CARDBUS) {
- unsigned int buses;
- buses = pci_read_config32(dev, PCI_PRIMARY_BUS);
- busmaster_disable_on_bus((buses >> 8) & 0xff);
- }
- }
- }
+ int slot, func;
+ unsigned int val;
+ unsigned char hdr;
+
+ for (slot = 0; slot < 0x20; slot++) {
+ for (func = 0; func < 8; func++) {
+ u32 reg32;
+ device_t dev = PCI_DEV(bus, slot, func);
+
+ val = pci_read_config32(dev, PCI_VENDOR_ID);
+
+ if (val == 0xffffffff || val == 0x00000000 ||
+ val == 0x0000ffff || val == 0xffff0000)
+ continue;
+
+ /* Disable Bus Mastering for this one device */
+ reg32 = pci_read_config32(dev, PCI_COMMAND);
+ reg32 &= ~PCI_COMMAND_MASTER;
+ pci_write_config32(dev, PCI_COMMAND, reg32);
+
+ /* If this is a bridge, then follow it. */
+ hdr = pci_read_config8(dev, PCI_HEADER_TYPE);
+ hdr &= 0x7f;
+ if (hdr == PCI_HEADER_TYPE_BRIDGE ||
+ hdr == PCI_HEADER_TYPE_CARDBUS) {
+ unsigned int buses;
+ buses = pci_read_config32(dev, PCI_PRIMARY_BUS);
+ busmaster_disable_on_bus((buses >> 8) & 0xff);
+ }
+ }
+ }
}
diff --git a/src/southbridge/intel/i82801ix/bootblock.c b/src/southbridge/intel/i82801ix/bootblock.c
index e222368..6252712 100644
--- a/src/southbridge/intel/i82801ix/bootblock.c
+++ b/src/southbridge/intel/i82801ix/bootblock.c
@@ -17,18 +17,18 @@
static void enable_spi_prefetch(void)
{
- u8 reg8;
- pci_devfn_t dev;
+ u8 reg8;
+ pci_devfn_t dev;
- dev = PCI_DEV(0, 0x1f, 0);
+ dev = PCI_DEV(0, 0x1f, 0);
- reg8 = pci_read_config8(dev, 0xdc);
- reg8 &= ~(3 << 2);
- reg8 |= (2 << 2); /* Prefetching and Caching Enabled */
- pci_write_config8(dev, 0xdc, reg8);
+ reg8 = pci_read_config8(dev, 0xdc);
+ reg8 &= ~(3 << 2);
+ reg8 |= (2 << 2); /* Prefetching and Caching Enabled */
+ pci_write_config8(dev, 0xdc, reg8);
}
static void bootblock_southbridge_init(void)
{
- enable_spi_prefetch();
+ enable_spi_prefetch();
}
diff --git a/src/southbridge/intel/i82870/ioapic.c b/src/southbridge/intel/i82870/ioapic.c
index 6a0f0d2..e6a21ad 100644
--- a/src/southbridge/intel/i82870/ioapic.c
+++ b/src/southbridge/intel/i82870/ioapic.c
@@ -49,9 +49,9 @@ static void p64h2_ioapic_init(device_t dev)
// IDs 3, 4, 5, and 8+ are available (see above note)
if (apic_index < 3)
- apic_id = apic_index + 3;
+ apic_id = apic_index + 3;
else
- apic_id = apic_index + 5;
+ apic_id = apic_index + 5;
ASSERT(apic_id < 16); // ID is only 4 bits
@@ -63,8 +63,8 @@ static void p64h2_ioapic_init(device_t dev)
pWindowRegister = (volatile uint32_t*)(memoryBase + 0x10);
printk(BIOS_DEBUG, "IOAPIC %d at %02x:%02x.%01x MBAR = %p DataAddr = %p\n",
- apic_id, dev->bus->secondary, PCI_SLOT(dev->path.pci.devfn),
- PCI_FUNC(dev->path.pci.devfn), pIndexRegister, pWindowRegister);
+ apic_id, dev->bus->secondary, PCI_SLOT(dev->path.pci.devfn),
+ PCI_FUNC(dev->path.pci.devfn), pIndexRegister, pWindowRegister);
apic_id <<= 24; // Convert ID to bitmask
@@ -72,27 +72,27 @@ static void p64h2_ioapic_init(device_t dev)
*pWindowRegister = (*pWindowRegister & ~(0xF<<24)) | apic_id; // Set the ID
if ((*pWindowRegister & (0xF<<24)) != apic_id)
- die("p64h2_ioapic_init failed");
+ die("p64h2_ioapic_init failed");
*pIndexRegister = 3; // Select Boot Configuration register
*pWindowRegister |= 1; // Use Processor System Bus to deliver interrupts
if (!(*pWindowRegister & 1))
- die("p64h2_ioapic_init failed");
+ die("p64h2_ioapic_init failed");
}
static struct device_operations ioapic_ops = {
- .read_resources = pci_dev_read_resources,
- .set_resources = pci_dev_set_resources,
- .enable_resources = pci_dev_enable_resources,
- .init = p64h2_ioapic_init,
- .scan_bus = 0,
- .enable = p64h2_ioapic_enable,
+ .read_resources = pci_dev_read_resources,
+ .set_resources = pci_dev_set_resources,
+ .enable_resources = pci_dev_enable_resources,
+ .init = p64h2_ioapic_init,
+ .scan_bus = 0,
+ .enable = p64h2_ioapic_enable,
};
static const struct pci_driver ioapic_driver __pci_driver = {
- .ops = &ioapic_ops,
- .vendor = PCI_VENDOR_ID_INTEL,
- .device = PCI_DEVICE_ID_INTEL_82870_1E0,
+ .ops = &ioapic_ops,
+ .vendor = PCI_VENDOR_ID_INTEL,
+ .device = PCI_DEVICE_ID_INTEL_82870_1E0,
};
diff --git a/src/southbridge/intel/i82870/pci_parity.c b/src/southbridge/intel/i82870/pci_parity.c
index 71d2c53..b886c52 100644
--- a/src/southbridge/intel/i82870/pci_parity.c
+++ b/src/southbridge/intel/i82870/pci_parity.c
@@ -5,19 +5,19 @@
void p64h2_pci_parity_enable(void)
{
- uint8_t reg;
+ uint8_t reg;
- /* 2SERREN - SERR enable for PCI bridge secondary device */
- /* 2PEREN - Parity error for PCI bridge secondary device */
- pcibios_read_config_byte(1, ((29 << 3) + (0 << 0)), 0x3e, ®);
- reg |= ((1 << 1) + (1 << 0));
- pcibios_write_config_byte(1, ((29 << 3) + (0 << 0)), 0x3e, reg);
+ /* 2SERREN - SERR enable for PCI bridge secondary device */
+ /* 2PEREN - Parity error for PCI bridge secondary device */
+ pcibios_read_config_byte(1, ((29 << 3) + (0 << 0)), 0x3e, ®);
+ reg |= ((1 << 1) + (1 << 0));
+ pcibios_write_config_byte(1, ((29 << 3) + (0 << 0)), 0x3e, reg);
- /* 2SERREN - SERR enable for PCI bridge secondary device */
- /* 2PEREN - Parity error for PCI bridge secondary device */
- pcibios_read_config_byte(1, ((31 << 3) + (0 << 0)), 0x3e, ®);
- reg |= ((1 << 1) + (1 << 0));
- pcibios_write_config_byte(1, ((31 << 3) + (0 << 0)), 0x3e, reg);
+ /* 2SERREN - SERR enable for PCI bridge secondary device */
+ /* 2PEREN - Parity error for PCI bridge secondary device */
+ pcibios_read_config_byte(1, ((31 << 3) + (0 << 0)), 0x3e, ®);
+ reg |= ((1 << 1) + (1 << 0));
+ pcibios_write_config_byte(1, ((31 << 3) + (0 << 0)), 0x3e, reg);
- return;
+ return;
}
diff --git a/src/southbridge/intel/i82870/pcibridge.c b/src/southbridge/intel/i82870/pcibridge.c
index b46b338..e8d890a 100644
--- a/src/southbridge/intel/i82870/pcibridge.c
+++ b/src/southbridge/intel/i82870/pcibridge.c
@@ -23,16 +23,16 @@ static void p64h2_pcix_init(device_t dev)
}
static struct device_operations pcix_ops = {
- .read_resources = pci_bus_read_resources,
- .set_resources = pci_dev_set_resources,
- .enable_resources = pci_bus_enable_resources,
- .init = p64h2_pcix_init,
- .scan_bus = pci_scan_bridge,
+ .read_resources = pci_bus_read_resources,
+ .set_resources = pci_dev_set_resources,
+ .enable_resources = pci_bus_enable_resources,
+ .init = p64h2_pcix_init,
+ .scan_bus = pci_scan_bridge,
.reset_bus = pci_bus_reset,
};
static const struct pci_driver pcix_driver __pci_driver = {
- .ops = &pcix_ops,
- .vendor = PCI_VENDOR_ID_INTEL,
- .device = PCI_DEVICE_ID_INTEL_82870_1F0,
+ .ops = &pcix_ops,
+ .vendor = PCI_VENDOR_ID_INTEL,
+ .device = PCI_DEVICE_ID_INTEL_82870_1F0,
};
diff --git a/src/southbridge/intel/ibexpeak/pch.h b/src/southbridge/intel/ibexpeak/pch.h
index 6c694fd..62341ff 100644
--- a/src/southbridge/intel/ibexpeak/pch.h
+++ b/src/southbridge/intel/ibexpeak/pch.h
@@ -263,7 +263,7 @@ void southbridge_configure_default_intmap(void);
#define RCBA32(x) *((volatile u32 *)(DEFAULT_RCBA + x))
#define RCBA_AND_OR(bits, x, and, or) \
- RCBA##bits(x) = ((RCBA##bits(x) & (and)) | (or))
+ RCBA##bits(x) = ((RCBA##bits(x) & (and)) | (or))
#define RCBA8_AND_OR(x, and, or) RCBA_AND_OR(8, x, and, or)
#define RCBA16_AND_OR(x, and, or) RCBA_AND_OR(16, x, and, or)
#define RCBA32_AND_OR(x, and, or) RCBA_AND_OR(32, x, and, or)
@@ -401,7 +401,7 @@ void southbridge_configure_default_intmap(void);
#define DIR_ROUTE(x,a,b,c,d) \
RCBA32(x) = (((d) << DIR_IDR) | ((c) << DIR_ICR) | \
- ((b) << DIR_IBR) | ((a) << DIR_IAR))
+ ((b) << DIR_IBR) | ((a) << DIR_IAR))
#define RC 0x3400 /* 32bit */
#define HPTC 0x3404 /* 32bit */
diff --git a/src/southbridge/intel/ibexpeak/sata.c b/src/southbridge/intel/ibexpeak/sata.c
index e7681fb..19ef098 100644
--- a/src/southbridge/intel/ibexpeak/sata.c
+++ b/src/southbridge/intel/ibexpeak/sata.c
@@ -126,7 +126,7 @@ static void sata_init(struct device *dev)
reg32 &= ~0x00000005;
write32(abar + 0x28, reg32);
} else {
- /* IDE */
+ /* IDE */
printk(BIOS_DEBUG, "SATA: Controller in plain mode.\n");
/* No AHCI: clear AHCI base */
diff --git a/src/southbridge/intel/ibexpeak/smihandler.c b/src/southbridge/intel/ibexpeak/smihandler.c
index d4fbed4..b5450a0 100644
--- a/src/southbridge/intel/ibexpeak/smihandler.c
+++ b/src/southbridge/intel/ibexpeak/smihandler.c
@@ -273,37 +273,37 @@ void southbridge_smi_set_eos(void)
static void busmaster_disable_on_bus(int bus)
{
- int slot, func;
- unsigned int val;
- unsigned char hdr;
-
- for (slot = 0; slot < 0x20; slot++) {
- for (func = 0; func < 8; func++) {
- u32 reg32;
- device_t dev = PCI_DEV(bus, slot, func);
-
- val = pci_read_config32(dev, PCI_VENDOR_ID);
-
- if (val == 0xffffffff || val == 0x00000000 ||
- val == 0x0000ffff || val == 0xffff0000)
- continue;
-
- /* Disable Bus Mastering for this one device */
- reg32 = pci_read_config32(dev, PCI_COMMAND);
- reg32 &= ~PCI_COMMAND_MASTER;
- pci_write_config32(dev, PCI_COMMAND, reg32);
-
- /* If this is a bridge, then follow it. */
- hdr = pci_read_config8(dev, PCI_HEADER_TYPE);
- hdr &= 0x7f;
- if (hdr == PCI_HEADER_TYPE_BRIDGE ||
- hdr == PCI_HEADER_TYPE_CARDBUS) {
- unsigned int buses;
- buses = pci_read_config32(dev, PCI_PRIMARY_BUS);
- busmaster_disable_on_bus((buses >> 8) & 0xff);
- }
- }
- }
+ int slot, func;
+ unsigned int val;
+ unsigned char hdr;
+
+ for (slot = 0; slot < 0x20; slot++) {
+ for (func = 0; func < 8; func++) {
+ u32 reg32;
+ device_t dev = PCI_DEV(bus, slot, func);
+
+ val = pci_read_config32(dev, PCI_VENDOR_ID);
+
+ if (val == 0xffffffff || val == 0x00000000 ||
+ val == 0x0000ffff || val == 0xffff0000)
+ continue;
+
+ /* Disable Bus Mastering for this one device */
+ reg32 = pci_read_config32(dev, PCI_COMMAND);
+ reg32 &= ~PCI_COMMAND_MASTER;
+ pci_write_config32(dev, PCI_COMMAND, reg32);
+
+ /* If this is a bridge, then follow it. */
+ hdr = pci_read_config8(dev, PCI_HEADER_TYPE);
+ hdr &= 0x7f;
+ if (hdr == PCI_HEADER_TYPE_BRIDGE ||
+ hdr == PCI_HEADER_TYPE_CARDBUS) {
+ unsigned int buses;
+ buses = pci_read_config32(dev, PCI_PRIMARY_BUS);
+ busmaster_disable_on_bus((buses >> 8) & 0xff);
+ }
+ }
+ }
}
static void southbridge_gate_memory_reset_real(int offset,
diff --git a/src/southbridge/intel/lynxpoint/early_pch.c b/src/southbridge/intel/lynxpoint/early_pch.c
index 0e4fa3d..8e2d42f 100644
--- a/src/southbridge/intel/lynxpoint/early_pch.c
+++ b/src/southbridge/intel/lynxpoint/early_pch.c
@@ -125,7 +125,7 @@ void pch_enable_lpc(void)
}
int early_pch_init(const void *gpio_map,
- const struct rcba_config_instruction *rcba_config)
+ const struct rcba_config_instruction *rcba_config)
{
int wake_from_s3;
diff --git a/src/southbridge/intel/lynxpoint/lpc.c b/src/southbridge/intel/lynxpoint/lpc.c
index 1d20bbb..5af6bf5 100644
--- a/src/southbridge/intel/lynxpoint/lpc.c
+++ b/src/southbridge/intel/lynxpoint/lpc.c
@@ -194,7 +194,7 @@ static void pch_power_options(device_t dev)
* If the option is not existent (Laptops), use Kconfig setting.
*/
get_option(&pwr_on, "power_on_after_fail");
- pwr_on = MAINBOARD_POWER_KEEP;
+ pwr_on = MAINBOARD_POWER_KEEP;
reg16 = pci_read_config16(dev, GEN_PMCON_3);
reg16 &= 0xfffe;
diff --git a/src/southbridge/intel/lynxpoint/me_9.x.c b/src/southbridge/intel/lynxpoint/me_9.x.c
index 43e5289..355db4b 100644
--- a/src/southbridge/intel/lynxpoint/me_9.x.c
+++ b/src/southbridge/intel/lynxpoint/me_9.x.c
@@ -485,7 +485,7 @@ static int mkhi_get_fwcaps(mbp_mefwcaps *cap)
&cap_msg, sizeof(cap_msg)) < 0) {
printk(BIOS_ERR, "ME: GET FWCAPS message failed\n");
return -1;
- }
+ }
*cap = cap_msg.caps_sku;
return 0;
}
@@ -650,7 +650,7 @@ static int me_icc_set_clock_enables(u32 mask)
if (mei_sendrecv_icc(&icc, &clk, sizeof(clk), NULL, 0) < 0) {
printk(BIOS_ERR, "ME: ICC SET CLOCK ENABLES message failed\n");
return -1;
- } else {
+ } else {
printk(BIOS_INFO, "ME: ICC SET CLOCK ENABLES 0x%08x\n", mask);
}
diff --git a/src/southbridge/intel/lynxpoint/pch.h b/src/southbridge/intel/lynxpoint/pch.h
index 8cae50a..b170755 100644
--- a/src/southbridge/intel/lynxpoint/pch.h
+++ b/src/southbridge/intel/lynxpoint/pch.h
@@ -201,7 +201,7 @@ void enable_usb_bar(void);
int smbus_read_byte(unsigned device, unsigned address);
int early_spi_read(u32 offset, u32 size, u8 *buffer);
int early_pch_init(const void *gpio_map,
- const struct rcba_config_instruction *rcba_config);
+ const struct rcba_config_instruction *rcba_config);
void pch_enable_lpc(void);
#endif /* !__PRE_RAM__ && !__SMM__ */
#endif /* __ASSEMBLER__ */
@@ -503,7 +503,7 @@ void pch_enable_lpc(void);
#define RCBA32(x) *((volatile u32 *)(DEFAULT_RCBA + x))
#define RCBA_AND_OR(bits, x, and, or) \
- RCBA##bits(x) = ((RCBA##bits(x) & (and)) | (or))
+ RCBA##bits(x) = ((RCBA##bits(x) & (and)) | (or))
#define RCBA8_AND_OR(x, and, or) RCBA_AND_OR(8, x, and, or)
#define RCBA16_AND_OR(x, and, or) RCBA_AND_OR(16, x, and, or)
#define RCBA32_AND_OR(x, and, or) RCBA_AND_OR(32, x, and, or)
diff --git a/src/southbridge/intel/lynxpoint/reset.c b/src/southbridge/intel/lynxpoint/reset.c
index daabbbc..804fb81 100644
--- a/src/southbridge/intel/lynxpoint/reset.c
+++ b/src/southbridge/intel/lynxpoint/reset.c
@@ -19,10 +19,10 @@
void soft_reset(void)
{
- outb(0x04, 0xcf9);
+ outb(0x04, 0xcf9);
}
void hard_reset(void)
{
- outb(0x06, 0xcf9);
+ outb(0x06, 0xcf9);
}
diff --git a/src/southbridge/intel/lynxpoint/smihandler.c b/src/southbridge/intel/lynxpoint/smihandler.c
index 4f0db1b..4a156ea 100644
--- a/src/southbridge/intel/lynxpoint/smihandler.c
+++ b/src/southbridge/intel/lynxpoint/smihandler.c
@@ -68,37 +68,37 @@ void southbridge_smi_set_eos(void)
static void busmaster_disable_on_bus(int bus)
{
- int slot, func;
- unsigned int val;
- unsigned char hdr;
-
- for (slot = 0; slot < 0x20; slot++) {
- for (func = 0; func < 8; func++) {
- u32 reg32;
- device_t dev = PCI_DEV(bus, slot, func);
-
- val = pci_read_config32(dev, PCI_VENDOR_ID);
-
- if (val == 0xffffffff || val == 0x00000000 ||
- val == 0x0000ffff || val == 0xffff0000)
- continue;
-
- /* Disable Bus Mastering for this one device */
- reg32 = pci_read_config32(dev, PCI_COMMAND);
- reg32 &= ~PCI_COMMAND_MASTER;
- pci_write_config32(dev, PCI_COMMAND, reg32);
-
- /* If this is a bridge, then follow it. */
- hdr = pci_read_config8(dev, PCI_HEADER_TYPE);
- hdr &= 0x7f;
- if (hdr == PCI_HEADER_TYPE_BRIDGE ||
- hdr == PCI_HEADER_TYPE_CARDBUS) {
- unsigned int buses;
- buses = pci_read_config32(dev, PCI_PRIMARY_BUS);
- busmaster_disable_on_bus((buses >> 8) & 0xff);
- }
- }
- }
+ int slot, func;
+ unsigned int val;
+ unsigned char hdr;
+
+ for (slot = 0; slot < 0x20; slot++) {
+ for (func = 0; func < 8; func++) {
+ u32 reg32;
+ device_t dev = PCI_DEV(bus, slot, func);
+
+ val = pci_read_config32(dev, PCI_VENDOR_ID);
+
+ if (val == 0xffffffff || val == 0x00000000 ||
+ val == 0x0000ffff || val == 0xffff0000)
+ continue;
+
+ /* Disable Bus Mastering for this one device */
+ reg32 = pci_read_config32(dev, PCI_COMMAND);
+ reg32 &= ~PCI_COMMAND_MASTER;
+ pci_write_config32(dev, PCI_COMMAND, reg32);
+
+ /* If this is a bridge, then follow it. */
+ hdr = pci_read_config8(dev, PCI_HEADER_TYPE);
+ hdr &= 0x7f;
+ if (hdr == PCI_HEADER_TYPE_BRIDGE ||
+ hdr == PCI_HEADER_TYPE_CARDBUS) {
+ unsigned int buses;
+ buses = pci_read_config32(dev, PCI_PRIMARY_BUS);
+ busmaster_disable_on_bus((buses >> 8) & 0xff);
+ }
+ }
+ }
}
diff --git a/src/southbridge/nvidia/ck804/early_setup_car.c b/src/southbridge/nvidia/ck804/early_setup_car.c
index ae8b6a0..6b21a3f 100644
--- a/src/southbridge/nvidia/ck804/early_setup_car.c
+++ b/src/southbridge/nvidia/ck804/early_setup_car.c
@@ -377,6 +377,6 @@ void soft_reset(void)
void enable_fid_change_on_sb(unsigned sbbusn, unsigned sbdn)
{
- /* The default value for CK804 is good. */
- /* Set VFSMAF (VID/FID System Management Action Field) to 2. */
+ /* The default value for CK804 is good. */
+ /* Set VFSMAF (VID/FID System Management Action Field) to 2. */
}
diff --git a/src/southbridge/sis/sis966/aza.c b/src/southbridge/sis/sis966/aza.c
index a7c3319..4cb9215 100644
--- a/src/southbridge/sis/sis966/aza.c
+++ b/src/southbridge/sis/sis966/aza.c
@@ -184,7 +184,7 @@ static u32 verb_data[] = {
static unsigned find_verb(u32 viddid, u32 **verb)
{
- if((viddid == 0x10ec0883) || (viddid == 0x10ec0882) || (viddid == 0x10ec0880)) return 0;
+ if((viddid == 0x10ec0883) || (viddid == 0x10ec0882) || (viddid == 0x10ec0880)) return 0;
*verb = (u32 *)verb_data;
return sizeof(verb_data)/sizeof(u32);
}
@@ -236,45 +236,45 @@ static void codecs_init(u8 *base, u32 codec_mask)
static void aza_init(struct device *dev)
{
- u8 *base;
- struct resource *res;
- u32 codec_mask;
+ u8 *base;
+ struct resource *res;
+ u32 codec_mask;
- printk(BIOS_DEBUG, "AZALIA_INIT:---------->\n");
+ printk(BIOS_DEBUG, "AZALIA_INIT:---------->\n");
//-------------- enable AZA (SiS7502) -------------------------
{
- u8 temp8;
- int i=0;
- while(SiS_SiS7502_init[i][0] != 0)
- {
- temp8 = pci_read_config8(dev, SiS_SiS7502_init[i][0]);
- temp8 &= SiS_SiS7502_init[i][1];
- temp8 |= SiS_SiS7502_init[i][2];
- pci_write_config8(dev, SiS_SiS7502_init[i][0], temp8);
- i++;
- };
+ u8 temp8;
+ int i=0;
+ while(SiS_SiS7502_init[i][0] != 0)
+ {
+ temp8 = pci_read_config8(dev, SiS_SiS7502_init[i][0]);
+ temp8 &= SiS_SiS7502_init[i][1];
+ temp8 |= SiS_SiS7502_init[i][2];
+ pci_write_config8(dev, SiS_SiS7502_init[i][0], temp8);
+ i++;
+ };
}
//-----------------------------------------------------------
- // put audio to D0 state
- pci_write_config8(dev, 0x54,0x00);
+ // put audio to D0 state
+ pci_write_config8(dev, 0x54,0x00);
#if DEBUG_AZA
{
- int i;
-
- printk(BIOS_DEBUG, "****** Azalia PCI config ******");
- printk(BIOS_DEBUG, "\n 03020100 07060504 0B0A0908 0F0E0D0C");
-
- for(i=0;i<0xff;i+=4){
- if((i%16)==0){
- printk(BIOS_DEBUG, "\n%02x: ", i);
- }
- printk(BIOS_DEBUG, "%08x ", pci_read_config32(dev,i));
- }
- printk(BIOS_DEBUG, "\n");
+ int i;
+
+ printk(BIOS_DEBUG, "****** Azalia PCI config ******");
+ printk(BIOS_DEBUG, "\n 03020100 07060504 0B0A0908 0F0E0D0C");
+
+ for(i=0;i<0xff;i+=4){
+ if((i%16)==0){
+ printk(BIOS_DEBUG, "\n%02x: ", i);
+ }
+ printk(BIOS_DEBUG, "%08x ", pci_read_config32(dev,i));
+ }
+ printk(BIOS_DEBUG, "\n");
}
#endif
@@ -292,7 +292,7 @@ static void aza_init(struct device *dev)
codecs_init(base, codec_mask);
}
- printk(BIOS_DEBUG, "AZALIA_INIT:<----------\n");
+ printk(BIOS_DEBUG, "AZALIA_INIT:<----------\n");
}
static void lpci_set_subsystem(device_t dev, unsigned vendor, unsigned device)
diff --git a/src/southbridge/sis/sis966/early_smbus.c b/src/southbridge/sis/sis966/early_smbus.c
index 15d4f4c..d29c405 100644
--- a/src/southbridge/sis/sis966/early_smbus.c
+++ b/src/southbridge/sis/sis966/early_smbus.c
@@ -502,11 +502,11 @@ static const uint8_t SiS_SiS1183_init[44][3]={
};
/* In => Share Memory size
- => 00h : 0MBytes
- => 02h : 32MBytes
- => 03h : 64MBytes
- => 04h : 128MBytes
- => Others: Reserved
+ => 00h : 0MBytes
+ => 02h : 32MBytes
+ => 03h : 64MBytes
+ => 04h : 128MBytes
+ => Others: Reserved
*/
static void Init_Share_Memory(uint8_t ShareSize)
{
@@ -517,31 +517,31 @@ static void Init_Share_Memory(uint8_t ShareSize)
}
/* In: => Aperture size
- => 00h : 32MBytes
- => 01h : 64MBytes
- => 02h : 128MBytes
- => 03h : 256MBytes
- => 04h : 512MBytes
- => Others: Reserved
+ => 00h : 32MBytes
+ => 01h : 64MBytes
+ => 02h : 128MBytes
+ => 03h : 256MBytes
+ => 04h : 512MBytes
+ => Others: Reserved
*/
static void Init_Aper_Size(uint8_t AperSize)
{
- device_t dev;
- uint16_t SiSAperSizeTable[]={0x0F38, 0x0F30, 0x0F20, 0x0F00, 0x0E00};
+ device_t dev;
+ uint16_t SiSAperSizeTable[]={0x0F38, 0x0F30, 0x0F20, 0x0F00, 0x0E00};
- dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_AMD, 0x1103), 0);
- pci_write_config8(dev, 0x90, AperSize << 1);
+ dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_AMD, 0x1103), 0);
+ pci_write_config8(dev, 0x90, AperSize << 1);
- dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_SIS, PCI_DEVICE_ID_SIS_SIS761), 0);
- pci_write_config16(dev, 0xB4, SiSAperSizeTable[AperSize]);
+ dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_SIS, PCI_DEVICE_ID_SIS_SIS761), 0);
+ pci_write_config16(dev, 0xB4, SiSAperSizeTable[AperSize]);
}
static void sis_init_stage1(void)
{
- device_t dev;
- uint8_t temp8;
- int i;
- uint8_t GUI_En;
+ device_t dev;
+ uint8_t temp8;
+ int i;
+ uint8_t GUI_En;
// SiS_Chipset_Initialization
// ========================== NB =============================
@@ -608,20 +608,20 @@ static void sis_init_stage2(void)
// ========================== NB_AGP =============================
- dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_SIS, PCI_DEVICE_ID_SIS_SIS761), 0); //Enable Internal GUI enable bit
- pci_write_config8(dev, 0x4C, pci_read_config8(dev, 0x4C) | 0x10);
+ dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_SIS, PCI_DEVICE_ID_SIS_SIS761), 0); //Enable Internal GUI enable bit
+ pci_write_config8(dev, 0x4C, pci_read_config8(dev, 0x4C) | 0x10);
- dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_SIS, PCI_DEVICE_ID_SIS_AGP), 0);
- i=0;
+ dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_SIS, PCI_DEVICE_ID_SIS_AGP), 0);
+ i=0;
- while(SiS_NBAGP_init[i][0] != 0)
- {
- temp8 = pci_read_config8(dev, SiS_NBAGP_init[i][0]);
- temp8 &= SiS_NBAGP_init[i][1];
- temp8 |= SiS_NBAGP_init[i][2];
- pci_write_config8(dev, SiS_NBAGP_init[i][0], temp8);
- i++;
- };
+ while(SiS_NBAGP_init[i][0] != 0)
+ {
+ temp8 = pci_read_config8(dev, SiS_NBAGP_init[i][0]);
+ temp8 &= SiS_NBAGP_init[i][1];
+ temp8 |= SiS_NBAGP_init[i][2];
+ pci_write_config8(dev, SiS_NBAGP_init[i][0], temp8);
+ i++;
+ };
/**
* Share Memory size
@@ -640,24 +640,24 @@ static void sis_init_stage2(void)
* => Others: Reserved
*/
- Init_Share_Memory(0x02); //0x02 : 32M
- Init_Aper_Size(0x01); //0x1 : 64M
+ Init_Share_Memory(0x02); //0x02 : 32M
+ Init_Aper_Size(0x01); //0x1 : 64M
// ========================== NB =============================
- printk(BIOS_DEBUG, "Init NorthBridge sis761 -------->\n");
- dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_SIS, PCI_DEVICE_ID_SIS_SIS761), 0);
- msr = rdmsr(0xC001001A);
+ printk(BIOS_DEBUG, "Init NorthBridge sis761 -------->\n");
+ dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_SIS, PCI_DEVICE_ID_SIS_SIS761), 0);
+ msr = rdmsr(0xC001001A);
printk(BIOS_DEBUG, "Memory Top Bound %x\n",msr.lo );
- temp16=(pci_read_config8(dev, 0x4C) & 0xE0) >> 5;
- temp16=0x0001<<(temp16-1);
- temp16<<=8;
+ temp16=(pci_read_config8(dev, 0x4C) & 0xE0) >> 5;
+ temp16=0x0001<<(temp16-1);
+ temp16<<=8;
- printk(BIOS_DEBUG, "Integrated VGA Shared memory size=%dM bytes\n", temp16 >> 4);
- pci_write_config16(dev, 0x8E, (msr.lo >> 16) -temp16*1);
- pci_write_config8(dev, 0x7F, 0x08); // ACPI Base
- outb(inb(0x856) | 0x40, 0x856); // Auto-Reset Function
+ printk(BIOS_DEBUG, "Integrated VGA Shared memory size=%dM bytes\n", temp16 >> 4);
+ pci_write_config16(dev, 0x8E, (msr.lo >> 16) -temp16*1);
+ pci_write_config8(dev, 0x7F, 0x08); // ACPI Base
+ outb(inb(0x856) | 0x40, 0x856); // Auto-Reset Function
// ========================== ACPI =============================
i=0;
diff --git a/src/southbridge/sis/sis966/ide.c b/src/southbridge/sis/sis966/ide.c
index f3fa079..faee0a0 100644
--- a/src/southbridge/sis/sis966/ide.c
+++ b/src/southbridge/sis/sis966/ide.c
@@ -101,15 +101,15 @@ printk(BIOS_DEBUG, "IDE_INIT:---------->\n");
//-------------- enable IDE (SiS5513) -------------------------
{
- uint8_t temp8;
- int i=0;
+ uint8_t temp8;
+ int i=0;
while(SiS_SiS5513_init[i][0] != 0)
{
- temp8 = pci_read_config8(dev, SiS_SiS5513_init[i][0]);
- temp8 &= SiS_SiS5513_init[i][1];
- temp8 |= SiS_SiS5513_init[i][2];
- pci_write_config8(dev, SiS_SiS5513_init[i][0], temp8);
- i++;
+ temp8 = pci_read_config8(dev, SiS_SiS5513_init[i][0]);
+ temp8 &= SiS_SiS5513_init[i][1];
+ temp8 |= SiS_SiS5513_init[i][2];
+ pci_write_config8(dev, SiS_SiS5513_init[i][0], temp8);
+ i++;
};
}
//-----------------------------------------------------------
@@ -143,17 +143,17 @@ printk(BIOS_DEBUG, "IDE_INIT:---------->\n");
#if DEBUG_IDE
{
- int i;
+ int i;
- printk(BIOS_DEBUG, "****** IDE PCI config ******");
- printk(BIOS_DEBUG, "\n 03020100 07060504 0B0A0908 0F0E0D0C");
+ printk(BIOS_DEBUG, "****** IDE PCI config ******");
+ printk(BIOS_DEBUG, "\n 03020100 07060504 0B0A0908 0F0E0D0C");
- for(i=0;i<0xff;i+=4){
- if((i%16)==0)
- printk(BIOS_DEBUG, "\n%02x: ", i);
- printk(BIOS_DEBUG, "%08x ", pci_read_config32(dev,i));
- }
- printk(BIOS_DEBUG, "\n");
+ for(i=0;i<0xff;i+=4){
+ if((i%16)==0)
+ printk(BIOS_DEBUG, "\n%02x: ", i);
+ printk(BIOS_DEBUG, "%08x ", pci_read_config32(dev,i));
+ }
+ printk(BIOS_DEBUG, "\n");
}
#endif
printk(BIOS_DEBUG, "IDE_INIT:<----------\n");
diff --git a/src/southbridge/sis/sis966/lpc.c b/src/southbridge/sis/sis966/lpc.c
index 0a5adf0..35691a8 100644
--- a/src/southbridge/sis/sis966/lpc.c
+++ b/src/southbridge/sis/sis966/lpc.c
@@ -123,33 +123,33 @@ static void lpc_init(device_t dev)
(on*12)+(on>>1),(on&1)*5);
}
- /* Enable Error reporting */
- /* Set up sync flood detected */
- byte = pci_read_config8(dev, 0x47);
- byte |= (1 << 1);
- pci_write_config8(dev, 0x47, byte);
-
- /* Set up NMI on errors */
- byte = inb(0x70); // RTC70
- byte_old = byte;
- nmi_option = NMI_OFF;
- get_option(&nmi_option, "nmi");
- if (nmi_option) {
- byte &= ~(1 << 7); /* set NMI */
- } else {
- byte |= ( 1 << 7); // Can not mask NMI from PCI-E and NMI_NOW
- }
- if( byte != byte_old) {
- outb(byte, 0x70);
- }
-
- /* Initialize the real time clock */
- cmos_init(0);
-
- /* Initialize isa dma */
- isa_dma_init();
-
- printk(BIOS_DEBUG, "LPC_INIT <--------\n");
+ /* Enable Error reporting */
+ /* Set up sync flood detected */
+ byte = pci_read_config8(dev, 0x47);
+ byte |= (1 << 1);
+ pci_write_config8(dev, 0x47, byte);
+
+ /* Set up NMI on errors */
+ byte = inb(0x70); // RTC70
+ byte_old = byte;
+ nmi_option = NMI_OFF;
+ get_option(&nmi_option, "nmi");
+ if (nmi_option) {
+ byte &= ~(1 << 7); /* set NMI */
+ } else {
+ byte |= ( 1 << 7); // Can not mask NMI from PCI-E and NMI_NOW
+ }
+ if( byte != byte_old) {
+ outb(byte, 0x70);
+ }
+
+ /* Initialize the real time clock */
+ cmos_init(0);
+
+ /* Initialize isa dma */
+ isa_dma_init();
+
+ printk(BIOS_DEBUG, "LPC_INIT <--------\n");
}
static void sis966_lpc_read_resources(device_t dev)
diff --git a/src/southbridge/sis/sis966/nic.c b/src/southbridge/sis/sis966/nic.c
index cd376ab..f9ec7ff 100644
--- a/src/southbridge/sis/sis966/nic.c
+++ b/src/southbridge/sis/sis966/nic.c
@@ -75,7 +75,7 @@ static void readApcMacAddr(void)
printk(BIOS_DEBUG, "MAC addr in APC = ");
for(i = 0x9 ; i <=0xe ; i++)
{
- printk(BIOS_DEBUG, "%2.2x",readApcByte(i));
+ printk(BIOS_DEBUG, "%2.2x",readApcByte(i));
}
printk(BIOS_DEBUG, "\n");
@@ -103,7 +103,7 @@ static void set_apc(struct device *dev)
addr=0x9+2*i;
writeApcByte(addr,(u8)(MacAddr[i]&0xFF));
writeApcByte(addr+1L,(u8)((MacAddr[i]>>8)&0xFF));
- // printf("%x - ",readMacAddrByte(0x59+i));
+ // printf("%x - ",readMacAddrByte(0x59+i));
}
/* Set APC Reload */
@@ -146,10 +146,10 @@ static unsigned long ReadEEprom( struct device *dev, u8 *base, u32 Reg)
{
ulValue=read32(base + 0x3c);
- if(!(ulValue & 0x0080)) //BIT_7
- break;
+ if(!(ulValue & 0x0080)) //BIT_7
+ break;
- mdelay(100);
+ mdelay(100);
}
mdelay(50);
@@ -172,22 +172,22 @@ static int phy_read(u8 *base, unsigned phy_addr, unsigned phy_reg)
Read_Cmd = ((phy_reg << 11) |
- (phy_addr << 6) |
+ (phy_addr << 6) |
SMI_READ |
SMI_REQUEST);
- // SmiMgtInterface Reg is the SMI management interface register(offset 44h) of MAC
+ // SmiMgtInterface Reg is the SMI management interface register(offset 44h) of MAC
write32(base + 0x44, Read_Cmd);
- // Polling SMI_REQ bit to be deasserted indicated read command completed
- do
- {
+ // Polling SMI_REQ bit to be deasserted indicated read command completed
+ do
+ {
// Wait 20 usec before checking status
mdelay(20);
ulValue = read32(base + 0x44);
- } while((ulValue & SMI_REQUEST) != 0);
- //printk(BIOS_DEBUG, "base %x cmd %lx ret val %lx\n", tmp,Read_Cmd,ulValue);
- usData=(ulValue>>16);
+ } while((ulValue & SMI_REQUEST) != 0);
+ //printk(BIOS_DEBUG, "base %x cmd %lx ret val %lx\n", tmp,Read_Cmd,ulValue);
+ usData=(ulValue>>16);
@@ -204,19 +204,19 @@ static int phy_detect(u8 *base,u16 *PhyAddr) //BOOL PHY_Detect()
int PhyAddress = 0;
- // Scan all PHY address(0 ~ 31) to find a valid PHY
- for(PhyAddress = 0; PhyAddress < 32; PhyAddress++)
- {
+ // Scan all PHY address(0 ~ 31) to find a valid PHY
+ for(PhyAddress = 0; PhyAddress < 32; PhyAddress++)
+ {
usData=phy_read(base,PhyAddress,StatusReg); // Status register is a PHY's register(offset 01h)
- // Found a valid PHY
+ // Found a valid PHY
- if((usData != 0x0) && (usData != 0xffff))
- {
- bFoundPhy = TRUE;
- break;
- }
- }
+ if((usData != 0x0) && (usData != 0xffff))
+ {
+ bFoundPhy = TRUE;
+ break;
+ }
+ }
if(!bFoundPhy)
@@ -232,31 +232,31 @@ static int phy_detect(u8 *base,u16 *PhyAddr) //BOOL PHY_Detect()
static void nic_init(struct device *dev)
{
- int val;
- u16 PhyAddr;
- u8 *base;
- struct resource *res;
+ int val;
+ u16 PhyAddr;
+ u8 *base;
+ struct resource *res;
- printk(BIOS_DEBUG, "NIC_INIT:---------->\n");
+ printk(BIOS_DEBUG, "NIC_INIT:---------->\n");
//-------------- enable NIC (SiS19x) -------------------------
{
- u8 temp8;
- int i=0;
- while(SiS_SiS191_init[i][0] != 0)
+ u8 temp8;
+ int i=0;
+ while(SiS_SiS191_init[i][0] != 0)
{
- temp8 = pci_read_config8(dev, SiS_SiS191_init[i][0]);
- temp8 &= SiS_SiS191_init[i][1];
- temp8 |= SiS_SiS191_init[i][2];
- pci_write_config8(dev, SiS_SiS191_init[i][0], temp8);
- i++;
+ temp8 = pci_read_config8(dev, SiS_SiS191_init[i][0]);
+ temp8 &= SiS_SiS191_init[i][1];
+ temp8 |= SiS_SiS191_init[i][2];
+ pci_write_config8(dev, SiS_SiS191_init[i][0], temp8);
+ i++;
};
}
//-----------------------------------------------------------
{
- unsigned long i;
- unsigned long ulValue;
+ unsigned long i;
+ unsigned long ulValue;
res = find_resource(dev, 0x10);
@@ -266,7 +266,7 @@ static void nic_init(struct device *dev)
return;
}
base = res2mmio(res, 0, 0);
- printk(BIOS_DEBUG, "NIC base address %p\n",base);
+ printk(BIOS_DEBUG, "NIC base address %p\n",base);
if(!(val=phy_detect(base,&PhyAddr)))
{
@@ -274,14 +274,14 @@ static void nic_init(struct device *dev)
return;
}
- ulValue=read32(base + 0x38L); // check EEPROM existing
+ ulValue=read32(base + 0x38L); // check EEPROM existing
- if((ulValue & 0x0002))
- {
+ if((ulValue & 0x0002))
+ {
- // read MAC address from EEPROM at first
+ // read MAC address from EEPROM at first
- // if that is valid we will use that
+ // if that is valid we will use that
printk(BIOS_DEBUG, "EEPROM contents %lx \n",ReadEEprom( dev, base, 0LL));
for(i=0;i<3;i++) {
@@ -292,31 +292,31 @@ static void nic_init(struct device *dev)
MacAddr[i] =ulValue & 0xFFFF;
}
- }else{
- // read MAC address from firmware
- printk(BIOS_DEBUG, "EEPROM invalid!!\nReg 0x38h=%.8lx \n",ulValue);
- MacAddr[0]=read16((u16 *)0xffffffc0); // mac address store at here
- MacAddr[1]=read16((u16 *)0xffffffc2);
- MacAddr[2]=read16((u16 *)0xffffffc4);
- }
+ }else{
+ // read MAC address from firmware
+ printk(BIOS_DEBUG, "EEPROM invalid!!\nReg 0x38h=%.8lx \n",ulValue);
+ MacAddr[0]=read16((u16 *)0xffffffc0); // mac address store at here
+ MacAddr[1]=read16((u16 *)0xffffffc2);
+ MacAddr[2]=read16((u16 *)0xffffffc4);
+ }
- set_apc(dev);
+ set_apc(dev);
- readApcMacAddr();
+ readApcMacAddr();
#if DEBUG_NIC
{
- int i;
+ int i;
- printk(BIOS_DEBUG, "****** NIC PCI config ******");
- printk(BIOS_DEBUG, "\n 03020100 07060504 0B0A0908 0F0E0D0C");
+ printk(BIOS_DEBUG, "****** NIC PCI config ******");
+ printk(BIOS_DEBUG, "\n 03020100 07060504 0B0A0908 0F0E0D0C");
- for(i=0;i<0xff;i+=4){
- if((i%16)==0)
- printk(BIOS_DEBUG, "\n%02x: ", i);
- printk(BIOS_DEBUG, "%08x ", pci_read_config32(dev,i));
- }
- printk(BIOS_DEBUG, "\n");
+ for(i=0;i<0xff;i+=4){
+ if((i%16)==0)
+ printk(BIOS_DEBUG, "\n%02x: ", i);
+ printk(BIOS_DEBUG, "%08x ", pci_read_config32(dev,i));
+ }
+ printk(BIOS_DEBUG, "\n");
}
diff --git a/src/southbridge/sis/sis966/sata.c b/src/southbridge/sis/sis966/sata.c
index 197f4d2..92737bf 100644
--- a/src/southbridge/sis/sis966/sata.c
+++ b/src/southbridge/sis/sis966/sata.c
@@ -112,19 +112,19 @@ static void sata_init(struct device *dev)
conf = dev->chip_info;
- printk(BIOS_DEBUG, "SATA_INIT:---------->\n");
+ printk(BIOS_DEBUG, "SATA_INIT:---------->\n");
//-------------- enable IDE (SiS1183) -------------------------
{
- uint8_t temp8;
- int i=0;
+ uint8_t temp8;
+ int i=0;
while(SiS_SiS1183_init[i][0] != 0)
{
- temp8 = pci_read_config8(dev, SiS_SiS1183_init[i][0]);
- temp8 &= SiS_SiS1183_init[i][1];
- temp8 |= SiS_SiS1183_init[i][2];
- pci_write_config8(dev, SiS_SiS1183_init[i][0], temp8);
- i++;
+ temp8 = pci_read_config8(dev, SiS_SiS1183_init[i][0]);
+ temp8 &= SiS_SiS1183_init[i][1];
+ temp8 |= SiS_SiS1183_init[i][2];
+ pci_write_config8(dev, SiS_SiS1183_init[i][0], temp8);
+ i++;
};
}
//-----------------------------------------------------------
@@ -145,21 +145,21 @@ for (i=0;i<10;i++){
#if DEBUG_SATA
{
- int i;
+ int i;
- printk(BIOS_DEBUG, "****** SATA PCI config ******");
- printk(BIOS_DEBUG, "\n 03020100 07060504 0B0A0908 0F0E0D0C");
+ printk(BIOS_DEBUG, "****** SATA PCI config ******");
+ printk(BIOS_DEBUG, "\n 03020100 07060504 0B0A0908 0F0E0D0C");
- for(i=0;i<0xff;i+=4){
- if((i%16)==0)
- printk(BIOS_DEBUG, "\n%02x: ", i);
- printk(BIOS_DEBUG, "%08x ", pci_read_config32(dev,i));
- }
- printk(BIOS_DEBUG, "\n");
+ for(i=0;i<0xff;i+=4){
+ if((i%16)==0)
+ printk(BIOS_DEBUG, "\n%02x: ", i);
+ printk(BIOS_DEBUG, "%08x ", pci_read_config32(dev,i));
+ }
+ printk(BIOS_DEBUG, "\n");
}
#endif
- printk(BIOS_DEBUG, "SATA_INIT:<----------\n");
+ printk(BIOS_DEBUG, "SATA_INIT:<----------\n");
}
diff --git a/src/southbridge/sis/sis966/usb.c b/src/southbridge/sis/sis966/usb.c
index 95f01d1..d616a7d 100644
--- a/src/southbridge/sis/sis966/usb.c
+++ b/src/southbridge/sis/sis966/usb.c
@@ -51,12 +51,12 @@ uint8_t SiS_SiS7001_init[16][3]={
static void usb_init(struct device *dev)
{
- printk(BIOS_DEBUG, "USB 1.1 INIT:---------->\n");
+ printk(BIOS_DEBUG, "USB 1.1 INIT:---------->\n");
//-------------- enable USB1.1 (SiS7001) -------------------------
{
- uint8_t temp8;
- int i=0;
+ uint8_t temp8;
+ int i=0;
while(SiS_SiS7001_init[i][0] != 0)
{ temp8 = pci_read_config8(dev, SiS_SiS7001_init[i][0]);
@@ -70,20 +70,20 @@ static void usb_init(struct device *dev)
#if DEBUG_USB
{
- int i;
+ int i;
- printk(BIOS_DEBUG, "****** USB 1.1 PCI config ******");
- printk(BIOS_DEBUG, "\n 03020100 07060504 0B0A0908 0F0E0D0C");
+ printk(BIOS_DEBUG, "****** USB 1.1 PCI config ******");
+ printk(BIOS_DEBUG, "\n 03020100 07060504 0B0A0908 0F0E0D0C");
- for(i=0;i<0xff;i+=4){
- if((i%16)==0)
- printk(BIOS_DEBUG, "\n%02x: ", i);
- printk(BIOS_DEBUG, "%08x ", pci_read_config32(dev,i));
- }
- printk(BIOS_DEBUG, "\n");
+ for(i=0;i<0xff;i+=4){
+ if((i%16)==0)
+ printk(BIOS_DEBUG, "\n%02x: ", i);
+ printk(BIOS_DEBUG, "%08x ", pci_read_config32(dev,i));
+ }
+ printk(BIOS_DEBUG, "\n");
}
#endif
- printk(BIOS_DEBUG, "USB 1.1 INIT:<----------\n");
+ printk(BIOS_DEBUG, "USB 1.1 INIT:<----------\n");
}
static void lpci_set_subsystem(device_t dev, unsigned vendor, unsigned device)
diff --git a/src/southbridge/sis/sis966/usb2.c b/src/southbridge/sis/sis966/usb2.c
index 5bad6b3..ad0bd6c 100644
--- a/src/southbridge/sis/sis966/usb2.c
+++ b/src/southbridge/sis/sis966/usb2.c
@@ -62,46 +62,46 @@ static const u8 SiS_SiS7002_init[22][3]={
static void usb2_init(struct device *dev)
{
- u8 *base;
- struct resource *res;
- int i;
- u8 temp8;
+ u8 *base;
+ struct resource *res;
+ int i;
+ u8 temp8;
- printk(BIOS_DEBUG, "USB 2.0 INIT:---------->\n");
+ printk(BIOS_DEBUG, "USB 2.0 INIT:---------->\n");
//-------------- enable USB2.0 (SiS7002) ----------------------
i = 0;
- while(SiS_SiS7002_init[i][0] != 0)
- {
- temp8 = pci_read_config8(dev, SiS_SiS7002_init[i][0]);
- temp8 &= SiS_SiS7002_init[i][1];
- temp8 |= SiS_SiS7002_init[i][2];
- pci_write_config8(dev, SiS_SiS7002_init[i][0], temp8);
- i++;
- };
-
- res = find_resource(dev, 0x10);
- if(!res)
- return;
-
- base = res2mmio(res, 0, 0);
- printk(BIOS_DEBUG, "base = 0x%p\n", base);
- write32(base + 0x20, 0x2);
+ while(SiS_SiS7002_init[i][0] != 0)
+ {
+ temp8 = pci_read_config8(dev, SiS_SiS7002_init[i][0]);
+ temp8 &= SiS_SiS7002_init[i][1];
+ temp8 |= SiS_SiS7002_init[i][2];
+ pci_write_config8(dev, SiS_SiS7002_init[i][0], temp8);
+ i++;
+ };
+
+ res = find_resource(dev, 0x10);
+ if(!res)
+ return;
+
+ base = res2mmio(res, 0, 0);
+ printk(BIOS_DEBUG, "base = 0x%p\n", base);
+ write32(base + 0x20, 0x2);
//-------------------------------------------------------------
#if DEBUG_USB2
- printk(BIOS_DEBUG, "****** USB 2.0 PCI config ******");
- printk(BIOS_DEBUG, "\n 03020100 07060504 0B0A0908 0F0E0D0C");
-
- for(i=0;i<0xff;i+=4){
- if((i%16)==0)
- printk(BIOS_DEBUG, "\n%02x: ", i);
- printk(BIOS_DEBUG, "%08x ", pci_read_config32(dev,i));
- }
- printk(BIOS_DEBUG, "\n");
+ printk(BIOS_DEBUG, "****** USB 2.0 PCI config ******");
+ printk(BIOS_DEBUG, "\n 03020100 07060504 0B0A0908 0F0E0D0C");
+
+ for(i=0;i<0xff;i+=4){
+ if((i%16)==0)
+ printk(BIOS_DEBUG, "\n%02x: ", i);
+ printk(BIOS_DEBUG, "%08x ", pci_read_config32(dev,i));
+ }
+ printk(BIOS_DEBUG, "\n");
#endif
- printk(BIOS_DEBUG, "USB 2.0 INIT:<----------\n");
+ printk(BIOS_DEBUG, "USB 2.0 INIT:<----------\n");
}
static void lpci_set_subsystem(device_t dev, unsigned vendor, unsigned device)
diff --git a/src/southbridge/via/vt8237r/lpc.c b/src/southbridge/via/vt8237r/lpc.c
index dd3bcae..478a9ee 100644
--- a/src/southbridge/via/vt8237r/lpc.c
+++ b/src/southbridge/via/vt8237r/lpc.c
@@ -35,10 +35,10 @@
static void southbridge_init_common(struct device *dev);
#if CONFIG_EPIA_VT8237R_INIT
- /* Interrupts for INT# A B C D */
+ /* Interrupts for INT# A B C D */
static const unsigned char pciIrqs[4] = { 10, 11, 12, 0};
- /* Interrupt Assignments for Pins 1 2 3 4 */
+ /* Interrupt Assignments for Pins 1 2 3 4 */
static const unsigned char sataPins[4] = { 'A','B','C','D'};
static const unsigned char vgaPins[4] = { 'A','B','C','D'};
static const unsigned char usbPins[4] = { 'A','B','C','D'};
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