[coreboot-gerrit] New patch to review for coreboot: driver/intel/fsp2.0: Add External stage cache region helper

[Rizwan Qureshi (rizwan.qureshi@intel.com)]

Rizwan Qureshi (rizwan.qureshi at intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16312

-gerrit

commit edbb6d5f216365225edb8e9ad802b06b871b9cc5
Author: Rizwan Qureshi <rizwan.qureshi at intel.com>
Date:   Wed Aug 24 16:05:32 2016 +0530

    driver/intel/fsp2.0: Add External stage cache region helper
    
    If Ramstage caching outside CBMEM is enabled
    i.e CONFIG_CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM, then a
    helper function to determine the caching region in SMM
    should be implemented. Add the same to FSP2.0 driver.
    
    The SoC code should implement the smm_subregion to provide
    the base and size of the caching region within SMM.
    
    Change-Id: I4412a710391dc0cee044b96403c50260c3534e6f
    Signed-off-by: Rizwan Qureshi <rizwan.qureshi at intel.com>
---
 src/drivers/intel/fsp2_0/Makefile.inc  |  2 ++
 src/drivers/intel/fsp2_0/stage_cache.c | 28 ++++++++++++++++++++++++++++
 2 files changed, 30 insertions(+)

diff --git a/src/drivers/intel/fsp2_0/Makefile.inc b/src/drivers/intel/fsp2_0/Makefile.inc
index 0a6ae43..79b57f6 100644
--- a/src/drivers/intel/fsp2_0/Makefile.inc
+++ b/src/drivers/intel/fsp2_0/Makefile.inc
@@ -23,6 +23,7 @@ romstage-$(CONFIG_DISPLAY_UPD_DATA) += upd_display.c
 romstage-$(CONFIG_VERIFY_HOBS) += hob_verify.c
 romstage-y += util.c
 romstage-y += memory_init.c
+romstage-$(CONFIG_CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM) += stage_cache.c
 
 ramstage-y += debug.c
 ramstage-y += graphics.c
@@ -32,6 +33,7 @@ ramstage-$(CONFIG_DISPLAY_HOBS) += hob_display.c
 ramstage-$(CONFIG_VERIFY_HOBS) += hob_verify.c
 ramstage-y += notify.c
 ramstage-y += silicon_init.c
+ramstage-$(CONFIG_CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM) += stage_cache.c
 ramstage-$(CONFIG_DISPLAY_UPD_DATA) += upd_display.c
 ramstage-y += util.c
 
diff --git a/src/drivers/intel/fsp2_0/stage_cache.c b/src/drivers/intel/fsp2_0/stage_cache.c
new file mode 100644
index 0000000..98bd174
--- /dev/null
+++ b/src/drivers/intel/fsp2_0/stage_cache.c
@@ -0,0 +1,28 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2013 Google Inc.
+ * Copyright (C) 2015 Intel Corp.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <console/console.h>
+#include <soc/memmap.h>
+#include <stage_cache.h>
+
+void stage_cache_external_region(void **base, size_t *size)
+{
+	if (smm_subregion(SMM_SUBREGION_CACHE, base, size)) {
+		printk(BIOS_ERR, "ERROR: No cache SMM subregion.\n");
+		*base = NULL;
+		*size = 0;
+	}
+}