[coreboot-gerrit] Patch set updated for coreboot: soc/intel/skylake: align chromium Chrome OS config

[Aaron Durbin (adurbin@chromium.org)]

Aaron Durbin (adurbin at chromium.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16313

-gerrit

commit 7aeb3a9e7f1fd5056e408dd47542f5fca6bd56b3
Author: Aaron Durbin <adurbin at chromium.org>
Date:   Wed Aug 24 08:49:29 2016 -0500

    soc/intel/skylake: align chromium Chrome OS config
    
    The chromium tree is currently using a different config for
    Chrome OS than what is being built in coreboot.org. Align those
    settings to reflect how skylake Chrome OS boards are actually
    shipped to provide proper parity between coreboot.org and chromium.
    
    Change-Id: I7ab9c1dfa8c6be03ac2125fb06cb7022f3befa97
    Signed-off-by: Aaron Durbin <adurbin at chromium.org>
---
 src/soc/intel/skylake/Kconfig      | 2 ++
 src/soc/intel/skylake/Makefile.inc | 1 +
 2 files changed, 3 insertions(+)

diff --git a/src/soc/intel/skylake/Kconfig b/src/soc/intel/skylake/Kconfig
index 7fa129b..3bf8798 100644
--- a/src/soc/intel/skylake/Kconfig
+++ b/src/soc/intel/skylake/Kconfig
@@ -56,9 +56,11 @@ config CPU_SPECIFIC_OPTIONS
 config CHROMEOS
 	select CHROMEOS_RAMOOPS_DYNAMIC
 	select EC_SOFTWARE_SYNC if EC_GOOGLE_CHROMEEC
+	select SEPARATE_VERSTAGE
 	select VBOOT_EC_SLOW_UPDATE
 	select VBOOT_OPROM_MATTERS
 	select VBOOT_SAVE_RECOVERY_REASON_ON_REBOOT
+	select VBOOT_STARTS_IN_BOOTBLOCK
 	select VBOOT_VBNV_CMOS
 	select VBOOT_VBNV_CMOS_BACKUP_TO_FLASH
 	select VIRTUAL_DEV_SWITCH
diff --git a/src/soc/intel/skylake/Makefile.inc b/src/soc/intel/skylake/Makefile.inc
index b92eab3..716c3d5 100644
--- a/src/soc/intel/skylake/Makefile.inc
+++ b/src/soc/intel/skylake/Makefile.inc
@@ -28,6 +28,7 @@ bootblock-y += pmutil.c
 bootblock-y += tsc_freq.c
 
 verstage-y += flash_controller.c
+verstage-y += monotonic_timer.c
 verstage-y += pch.c
 verstage-$(CONFIG_UART_DEBUG) += uart_debug.c