[coreboot-gerrit] Patch set updated for coreboot: kunimitsu: Add FSP 2.0 support in romstage

[Rizwan Qureshi (rizwan.qureshi@intel.com)]

Rizwan Qureshi (rizwan.qureshi at intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16316

-gerrit

commit 162fa34c9fd96078cc7d951d6bfc726b4bd7016a
Author: Rizwan Qureshi <rizwan.qureshi at intel.com>
Date:   Wed Aug 24 20:50:54 2016 +0530

    kunimitsu: Add FSP 2.0 support in romstage
    
    Populate mainboard related Memory Init Params i.e, SPD
    Rcomp values, DQ and DQs values.
    
    Change-Id: Id62c43a72a0e34fa2e8d177ce895d395418e2347
    Signed-off-by: Rizwan Qureshi <rizwan.qureshi at intel.com>
    Signed-off-by: Naresh G Solanki <naresh.solanki at intel.com>
---
 src/mainboard/intel/kunimitsu/devicetree.cb    |  3 +
 src/mainboard/intel/kunimitsu/romstage_fsp20.c | 86 +++++++++++++++++++++++++-
 2 files changed, 88 insertions(+), 1 deletion(-)

diff --git a/src/mainboard/intel/kunimitsu/devicetree.cb b/src/mainboard/intel/kunimitsu/devicetree.cb
index 2aa3d95..a5789b0 100644
--- a/src/mainboard/intel/kunimitsu/devicetree.cb
+++ b/src/mainboard/intel/kunimitsu/devicetree.cb
@@ -187,6 +187,9 @@ chip soc/intel/skylake
 	# Send an extra VR mailbox command for the PS4 exit issue
 	register "SendVrMbxCmd" = "2"
 
+	# Enable/Disable VMX feature
+	register "VmxEnable" = "0"
+
 	# Use default SD card detect GPIO configuration
 	register "sdcard_cd_gpio_default" = "GPP_A7"
 
diff --git a/src/mainboard/intel/kunimitsu/romstage_fsp20.c b/src/mainboard/intel/kunimitsu/romstage_fsp20.c
index 10bdd21..152d35d 100644
--- a/src/mainboard/intel/kunimitsu/romstage_fsp20.c
+++ b/src/mainboard/intel/kunimitsu/romstage_fsp20.c
@@ -13,9 +13,93 @@
  * GNU General Public License for more details.
  */
 
+#include <arch/byteorder.h>
+#include <cbfs.h>
+#include <console/console.h>
+#include <fsp/api.h>
+#include <gpio.h>
+#include "gpio.h"
 #include <soc/romstage.h>
+#include "spd/spd.h"
+#include <string.h>
+
+#define RCOMP_TARGET_PARAMS	0x5
 
 void mainboard_memory_init_params(struct FSPM_UPD *mupd)
 {
-	/* TODO: Read and copy SPD and fill up Rcomp and DQ param */
+	struct FSP_M_CONFIG *mem_cfg;
+	mem_cfg = &mupd->FspmConfig;
+	char *spd_file;
+	size_t spd_file_len;
+	int spd_index, spd_span;
+
+	/* DQ byte map */
+	const u8 dq_map[2][12] = {
+		  { 0x0F, 0xF0, 0x00, 0xF0, 0x0F, 0xF0 ,
+		    0x0F, 0x00, 0xFF, 0x00, 0xFF, 0x00 },
+		  { 0x0F, 0xF0, 0x00, 0xF0, 0x0F, 0xF0 ,
+		    0x0F, 0x00, 0xFF, 0x00, 0xFF, 0x00 } };
+	/* DQS CPU<>DRAM map */
+	const u8 dqs_map[2][8] = {
+		{ 0, 1, 3, 2, 6, 5, 4, 7 },
+		{ 2, 3, 0, 1, 6, 7, 4, 5 } };
+
+	/* Rcomp resistor */
+	const u16 RcompResistor[3] = { 200, 81, 162 };
+
+	/* Rcomp target */
+	static const u16 RcompTarget[RCOMP_TARGET_PARAMS] = {
+		100, 40, 40, 23, 40 };
+
+	/*Strengthen the Rcomp Target Ctrl for 8GB K4E6E304EE -EGCF*/
+	//static const u16 StrengthendRcompTarget[RCOMP_TARGET_PARAMS] = {
+	//	100, 40, 40, 21, 40 };
+
+	memcpy((void*)mem_cfg->DqByteMapCh0, dq_map, sizeof(dq_map));
+	memcpy((void *)mem_cfg->DqsMapCpu2DramCh0, dqs_map, sizeof(dqs_map));
+	memcpy((void*)mem_cfg->RcompResistor, RcompResistor,  sizeof(RcompResistor));
+	memcpy((void*)mem_cfg->RcompTarget, RcompTarget, sizeof(RcompTarget));
+	mem_cfg->DqPinsInterleaved = 0;
+
+	/* fill SPD Data */
+
+	/* PCH_MEM_CFG[3:0] */
+		gpio_t spd_gpios[] = {
+			GPIO_MEM_CONFIG_0,
+			GPIO_MEM_CONFIG_1,
+			GPIO_MEM_CONFIG_2,
+			GPIO_MEM_CONFIG_3,
+		};
+
+	spd_index = gpio_base2_value(spd_gpios,	ARRAY_SIZE(spd_gpios));
+
+	printk(BIOS_INFO, "SPD index %d\n", spd_index);
+
+        /* Load SPD data from CBFS */
+        spd_file = cbfs_boot_map_with_leak("spd.bin", CBFS_TYPE_SPD,
+                &spd_file_len);
+        if (!spd_file)
+                die("SPD data not found.");
+
+        /* make sure we have at least one SPD in the file. */
+        if (spd_file_len < SPD_LEN)
+                die("Missing SPD data.");
+
+        /* Make sure we did not overrun the buffer */
+        if (spd_file_len < ((spd_index + 1) * SPD_LEN)) {
+                printk(BIOS_ERR, "SPD index override to 0 - old hardware?\n");
+                spd_index = 0;
+        }
+
+        /* Assume same memory in both channels */
+        spd_span = spd_index * SPD_LEN;
+
+	mem_cfg->MemorySpdPtr00 = ( uint32_t )spd_file + spd_span;
+	mem_cfg->MemorySpdPtr10 = (uint32_t)spd_file + spd_span;
+
+	printk(BIOS_DEBUG, " spd pointer address 00 -> 0x%8X \n" , (unsigned int)mem_cfg->MemorySpdPtr00);
+	printk(BIOS_DEBUG, " spd pointer address 00 -> 0x%8X \n" , (unsigned int)mem_cfg->MemorySpdPtr10);
+	printk(BIOS_DEBUG, " spd span -> 0x%8X \n" , (unsigned int) spd_file + spd_span);
+
+	mem_cfg->MemorySpdDataLen = SPD_LEN;
 }