[coreboot-gerrit] New patch to review for coreboot: arch/riscv: Add missing "break; "

[Jonathan Neuschäfer (j.neuschaefer@gmx.net)]

Jonathan Neuschäfer (j.neuschaefer at gmx.net) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16335

-gerrit

commit 8ee5be13b486c5ea69a85af3230fc51ee2dd0c54
Author: Jonathan Neuschäfer <j.neuschaefer at gmx.net>
Date:   Sat Aug 27 00:07:58 2016 +0200

    arch/riscv: Add missing "break;"
    
    Change-Id: Iea3f12a5a7eb37586f5424db2d7a84c4319492f8
    Reported-by: Coverity (1361947)
    Signed-off-by: Jonathan Neuschäfer <j.neuschaefer at gmx.net>
---
 src/arch/riscv/trap_handler.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/src/arch/riscv/trap_handler.c b/src/arch/riscv/trap_handler.c
index 29d5a0b..8120b66 100644
--- a/src/arch/riscv/trap_handler.c
+++ b/src/arch/riscv/trap_handler.c
@@ -35,6 +35,7 @@ void handle_supervisor_call(trapframe *tf) {
 			/* TODO: parse the hardware-supplied config string and
 			   return the correct value */
 			returnValue = 1;
+			break;
 		case SBI_ECALL_CONSOLE_PUT:
 			returnValue = mcall_console_putchar(arg0);
 			break;