[coreboot-gerrit] Patch set updated for coreboot: mainboard/google/reef: set SLP_S3_L assertion width to 28ms

[Aaron Durbin (adurbin@chromium.org)]

Aaron Durbin (adurbin at chromium.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16327

-gerrit

commit ddc0a77ffe46642fe4e8da4dc65541b2e1bbd819
Author: Aaron Durbin <adurbin at chromium.org>
Date:   Thu Aug 25 15:44:39 2016 -0500

    mainboard/google/reef: set SLP_S3_L assertion width to 28ms
    
    The reef board needs at least ~28ms for its S0 rails to discharge
    when S3 is entered. Because of the granularity in the chipset the
    effective SLP_S3_L assertion width is 50ms.
    
    BUG=chrome-os-partner:56581
    
    Change-Id: I20514eb0825cd4bc2ee9276b648204b7bfd6a7b0
    Signed-off-by: Aaron Durbin <adurbin at chromium.org>
---
 src/mainboard/google/reef/devicetree.cb | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/src/mainboard/google/reef/devicetree.cb b/src/mainboard/google/reef/devicetree.cb
index a877e86..4d08fae 100644
--- a/src/mainboard/google/reef/devicetree.cb
+++ b/src/mainboard/google/reef/devicetree.cb
@@ -50,6 +50,9 @@ chip soc/intel/apollolake
 	# Enable I2C2 bus early for TPM access
 	register "i2c[2].early_init" = "1"
 
+	# Minimum SLP S3 assertion width 28ms.
+	register "slp_s3_assertion_width_usecs" = "28000"
+
 	device domain 0 on
 		device pci 00.0 on  end	# - Host Bridge
 		device pci 00.1 on  end	# - DPTF