[coreboot-gerrit] Patch merged into coreboot/master: skylake: Add initial FSP2.0 support

[gerrit at coreboot.org]

the following patch was just integrated into master:
commit 1222a73205bd3a0faba988411b4aec6ea8de1059
Author: Rizwan Qureshi <rizwan.qureshi at intel.com>
Date:   Tue Aug 23 14:31:23 2016 +0530

    skylake: Add initial FSP2.0 support
    
    Add Initial pieces of code to support fsp2.0 in skylake keeping
    the fsp1.1 flow intact.
    
    The soc/romstage.h and soc/ramstage.h have a reference to
    fsp driver includes, so split these header files for
    each version of FSP driver.
    
    Add the below files,
    car_stage.S:
    	Add romstage entry point (car_stage_entry).
    	This calls into romstage_fsp20.c and aslo handles
    	the car teardown.
    romstage_fsp20.c:
    	Call fsp_memory_init() and also has the callback
    	for filling memory init parameters.
    
    Also add monotonic_timer.c to verstage.
    
    With this patchset and relevant change in kunimitsu mainboard,
    we are able to boot to romstage.
    
    TEST= Build and Boot Kunimitsu with PLATFORM_USES_FSP1_1
    Build and Boot Kunimitsu to romstage with PLATFORM_USES_FSP2_0
    
    Change-Id: I4309c8d4369c84d2bd1b13e8ab7bfeaaec645520
    Signed-off-by: Rizwan Qureshi <rizwan.qureshi at intel.com>
    Reviewed-on: https://review.coreboot.org/16267
    Reviewed-by: Aaron Durbin <adurbin at chromium.org>
    Tested-by: build bot (Jenkins)


See https://review.coreboot.org/16267 for details.

-gerrit