[coreboot-gerrit] Patch set updated for coreboot: src/southbridge: Code formating
HAOUAS Elyes (ehaouas@noos.fr)
gerrit at coreboot.org
Wed Aug 31 20:16:11 CEST 2016
HAOUAS Elyes (ehaouas at noos.fr) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16291
-gerrit
commit a52e9e0ba7f451056f3afc3b93921b3dad27ff22
Author: Elyes HAOUAS <ehaouas at noos.fr>
Date: Wed Aug 31 19:22:16 2016 +0200
src/southbridge: Code formating
Change-Id: Icfc35b73bacb60b1f21e71e70ad4418ec3e644f6
Signed-off-by: Elyes HAOUAS <ehaouas at noos.fr>
---
src/southbridge/amd/agesa/hudson/acpi/fch.asl | 4 +-
src/southbridge/amd/amd8111/acpi.c | 2 +-
src/southbridge/amd/amd8111/amd8111_smbus.h | 12 +-
src/southbridge/amd/amd8111/early_ctrl.c | 40 ++--
src/southbridge/amd/amd8111/ide.c | 4 +-
src/southbridge/amd/amd8111/reset.c | 22 +-
src/southbridge/amd/amd8131/bridge.c | 65 +++---
src/southbridge/amd/amd8132/bridge.c | 157 +++++++------
src/southbridge/amd/amd8151/agp3.c | 2 +-
src/southbridge/amd/cimx/sb700/Platform.h | 2 +-
src/southbridge/amd/cimx/sb700/reset.c | 2 +-
src/southbridge/amd/cimx/sb800/early.c | 4 +-
src/southbridge/amd/cimx/sb800/late.c | 54 ++---
src/southbridge/amd/cimx/sb800/reset.c | 2 +-
src/southbridge/amd/cimx/sb800/smbus.c | 8 +-
src/southbridge/amd/cimx/sb900/cfg.c | 4 +-
src/southbridge/amd/cimx/sb900/early.c | 2 +-
src/southbridge/amd/cimx/sb900/late.c | 98 ++++----
src/southbridge/amd/cimx/sb900/reset.c | 2 +-
src/southbridge/amd/cimx/sb900/smbus.c | 8 +-
src/southbridge/amd/common/amd_pci_util.c | 2 +-
src/southbridge/amd/cs5535/chipsetinit.c | 4 +-
src/southbridge/amd/cs5535/cs5535.c | 14 +-
src/southbridge/amd/cs5535/early_setup.c | 4 +-
src/southbridge/amd/cs5536/early_setup.c | 4 +-
src/southbridge/amd/pi/hudson/acpi/fch.asl | 4 +-
src/southbridge/amd/rs690/gfx.c | 62 ++---
src/southbridge/amd/rs690/ht.c | 8 +-
src/southbridge/amd/rs690/pcie.c | 2 +-
src/southbridge/amd/rs780/early_setup.c | 4 +-
src/southbridge/amd/rs780/gfx.c | 121 ++++------
src/southbridge/amd/rs780/rs780.h | 2 +-
src/southbridge/amd/sb600/early_setup.c | 2 +-
src/southbridge/amd/sb600/hda.c | 4 +-
src/southbridge/amd/sb600/sata.c | 2 +-
src/southbridge/amd/sb700/Kconfig | 10 -
src/southbridge/amd/sb700/bootblock.c | 34 ---
src/southbridge/amd/sb700/hda.c | 4 +-
src/southbridge/amd/sb700/reset.c | 2 +-
src/southbridge/amd/sb700/sm.c | 24 +-
src/southbridge/amd/sb800/hda.c | 4 +-
src/southbridge/amd/sb800/sata.c | 2 +-
src/southbridge/amd/sr5650/early_setup.c | 34 +--
src/southbridge/amd/sr5650/sr5650.c | 4 +-
src/southbridge/broadcom/bcm21000/pcie.c | 2 +-
src/southbridge/broadcom/bcm5780/nic.c | 12 +-
src/southbridge/broadcom/bcm5780/pcie.c | 16 +-
src/southbridge/broadcom/bcm5780/pcix.c | 20 +-
src/southbridge/broadcom/bcm5785/bcm5785.c | 14 +-
src/southbridge/broadcom/bcm5785/chip.h | 8 +-
src/southbridge/broadcom/bcm5785/early_setup.c | 236 +++++++++----------
src/southbridge/broadcom/bcm5785/early_smbus.c | 8 +-
src/southbridge/broadcom/bcm5785/ide.c | 16 +-
src/southbridge/broadcom/bcm5785/lpc.c | 30 +--
src/southbridge/broadcom/bcm5785/reset.c | 24 +-
src/southbridge/broadcom/bcm5785/sata.c | 32 +--
src/southbridge/broadcom/bcm5785/sb_pci_main.c | 98 ++++----
src/southbridge/broadcom/bcm5785/smbus.h | 110 ++++-----
src/southbridge/broadcom/bcm5785/usb.c | 8 +-
src/southbridge/intel/bd82x6x/azalia.c | 4 +-
src/southbridge/intel/bd82x6x/lpc.c | 2 +-
src/southbridge/intel/bd82x6x/me.c | 2 +-
src/southbridge/intel/bd82x6x/me_8.x.c | 8 +-
src/southbridge/intel/bd82x6x/reset.c | 4 +-
src/southbridge/intel/bd82x6x/smihandler.c | 64 +++---
src/southbridge/intel/fsp_bd82x6x/azalia.c | 4 +-
src/southbridge/intel/fsp_bd82x6x/lpc.c | 2 +-
src/southbridge/intel/fsp_bd82x6x/me.c | 2 +-
src/southbridge/intel/fsp_bd82x6x/me_8.x.c | 13 +-
src/southbridge/intel/fsp_bd82x6x/reset.c | 4 +-
src/southbridge/intel/fsp_bd82x6x/smihandler.c | 64 +++---
src/southbridge/intel/fsp_i89xx/lpc.c | 2 +-
src/southbridge/intel/fsp_i89xx/me.c | 2 +-
src/southbridge/intel/fsp_i89xx/me_8.x.c | 8 +-
src/southbridge/intel/fsp_i89xx/romstage.c | 2 +-
src/southbridge/intel/fsp_i89xx/smihandler.c | 64 +++---
src/southbridge/intel/fsp_rangeley/gpio.c | 4 +-
src/southbridge/intel/fsp_rangeley/lpc.c | 4 +-
src/southbridge/intel/i3100/early_smbus.c | 2 +-
src/southbridge/intel/i3100/lpc.c | 28 +--
src/southbridge/intel/i3100/sata.c | 2 +-
src/southbridge/intel/i82371eb/acpi_tables.c | 2 +-
src/southbridge/intel/i82371eb/smbus.h | 6 +-
src/southbridge/intel/i82801dx/smihandler.c | 64 +++---
src/southbridge/intel/i82801ex/early_smbus.c | 6 +-
src/southbridge/intel/i82801ex/lpc.c | 18 +-
src/southbridge/intel/i82801ex/reset.c | 4 +-
src/southbridge/intel/i82801ex/smbus.h | 6 +-
src/southbridge/intel/i82801ex/watchdog.c | 34 +--
src/southbridge/intel/i82801gx/azalia.c | 4 +-
src/southbridge/intel/i82801gx/bootblock.c | 16 +-
src/southbridge/intel/i82801gx/lpc.c | 2 +-
src/southbridge/intel/i82801gx/reset.c | 6 +-
src/southbridge/intel/i82801gx/smbus.c | 8 +-
src/southbridge/intel/i82801gx/smihandler.c | 64 +++---
src/southbridge/intel/i82801ix/bootblock.c | 16 +-
src/southbridge/intel/i82801ix/hdaudio.c | 4 +-
src/southbridge/intel/i82801ix/lpc.c | 2 +-
src/southbridge/intel/i82801ix/smihandler.c | 2 +-
src/southbridge/intel/i82870/ioapic.c | 97 ++++----
src/southbridge/intel/i82870/pci_parity.c | 24 +-
src/southbridge/intel/i82870/pcibridge.c | 16 +-
src/southbridge/intel/ibexpeak/azalia.c | 4 +-
src/southbridge/intel/ibexpeak/lpc.c | 2 +-
src/southbridge/intel/ibexpeak/sata.c | 2 +-
src/southbridge/intel/ibexpeak/smbus.h | 8 +-
src/southbridge/intel/ibexpeak/smihandler.c | 64 +++---
src/southbridge/intel/lynxpoint/hda_verb.c | 4 +-
src/southbridge/intel/lynxpoint/lpc.c | 4 +-
src/southbridge/intel/lynxpoint/me_9.x.c | 4 +-
src/southbridge/intel/lynxpoint/reset.c | 4 +-
src/southbridge/intel/lynxpoint/smihandler.c | 64 +++---
src/southbridge/nvidia/ck804/early_setup_car.c | 4 +-
src/southbridge/nvidia/mcp55/early_setup_car.c | 2 +-
src/southbridge/nvidia/mcp55/nic.c | 16 +-
src/southbridge/nvidia/mcp55/sata.c | 2 +-
src/southbridge/nvidia/mcp55/smbus.h | 2 +-
src/southbridge/ricoh/rl5c476/rl5c476.c | 6 +-
src/southbridge/sis/sis966/aza.c | 74 +++---
src/southbridge/sis/sis966/early_setup_car.c | 2 +-
src/southbridge/sis/sis966/early_smbus.c | 171 +++++++-------
src/southbridge/sis/sis966/ide.c | 35 ++-
src/southbridge/sis/sis966/lpc.c | 68 +++---
src/southbridge/sis/sis966/nic.c | 302 ++++++++++++-------------
src/southbridge/sis/sis966/sata.c | 53 ++---
src/southbridge/sis/sis966/sis966.c | 22 +-
src/southbridge/sis/sis966/usb.c | 40 ++--
src/southbridge/sis/sis966/usb2.c | 61 +++--
src/southbridge/via/k8t890/dram.c | 2 +-
src/southbridge/via/vt8237r/smihandler.c | 2 +-
130 files changed, 1548 insertions(+), 1653 deletions(-)
diff --git a/src/southbridge/amd/agesa/hudson/acpi/fch.asl b/src/southbridge/amd/agesa/hudson/acpi/fch.asl
index d7cee4a..7b0232a 100644
--- a/src/southbridge/amd/agesa/hudson/acpi/fch.asl
+++ b/src/southbridge/amd/agesa/hudson/acpi/fch.asl
@@ -183,9 +183,9 @@ Method(_INI, 0) {
Method(OSFL, 0){
- if(LNotEqual(OSVR, Ones)) {Return(OSVR)} /* OS version was already detected */
+ if (LNotEqual(OSVR, Ones)) {Return(OSVR)} /* OS version was already detected */
- if(CondRefOf(\_OSI))
+ if (CondRefOf(\_OSI))
{
Store(1, OSVR) /* Assume some form of XP */
if (\_OSI("Windows 2006")) /* Vista */
diff --git a/src/southbridge/amd/amd8111/acpi.c b/src/southbridge/amd/amd8111/acpi.c
index 396b7c4..2a6cf8d 100644
--- a/src/southbridge/amd/amd8111/acpi.c
+++ b/src/southbridge/amd/amd8111/acpi.c
@@ -152,7 +152,7 @@ static void acpi_init(struct device *dev)
/* Throttle the CPU speed down for testing */
on = SLOW_CPU_OFF;
get_option(&on, "slow_cpu");
- if(on) {
+ if (on) {
pm10_bar = (pci_read_config16(dev, 0x58)&0xff00);
outl(((on<<1)+0x10) ,(pm10_bar + 0x10));
inl(pm10_bar + 0x10);
diff --git a/src/southbridge/amd/amd8111/amd8111_smbus.h b/src/southbridge/amd/amd8111/amd8111_smbus.h
index 00f8f50..bf0b037 100644
--- a/src/southbridge/amd/amd8111/amd8111_smbus.h
+++ b/src/southbridge/amd/amd8111/amd8111_smbus.h
@@ -26,11 +26,11 @@ static int smbus_wait_until_ready(unsigned smbus_io_base)
if ((val & 0x800) == 0) {
break;
}
- if(loops == (SMBUS_TIMEOUT / 2)) {
+ if (loops == (SMBUS_TIMEOUT / 2)) {
outw(inw(smbus_io_base + SMBGSTATUS),
smbus_io_base + SMBGSTATUS);
}
- } while(--loops);
+ } while (--loops);
return loops?0:SMBUS_WAIT_UNTIL_READY_TIMEOUT;
}
@@ -46,7 +46,7 @@ static int smbus_wait_until_done(unsigned smbus_io_base)
if (((val & 0x8) == 0) | ((val & 0x0037) != 0)) {
break;
}
- } while(--loops);
+ } while (--loops);
return loops?0:SMBUS_WAIT_UNTIL_DONE_TIMEOUT;
}
@@ -267,11 +267,11 @@ static int do_smbus_block_read(unsigned smbus_io_base, unsigned device, unsigned
}
/* read data block */
- for(i=0; i<msglen && i<bytes; i++) {
+ for (i=0; i<msglen && i<bytes; i++) {
buf[i] = inw(smbus_io_base + SMBHSTFIFO) & 0xff;
}
/* empty fifo */
- while(bytes++<msglen) {
+ while (bytes++<msglen) {
inw(smbus_io_base + SMBHSTFIFO);
}
@@ -305,7 +305,7 @@ static int do_smbus_block_write(unsigned smbus_io_base, unsigned device, unsigne
outw(bytes, smbus_io_base + SMBHSTDAT);
/* set the data block */
- for(i=0; i<bytes; i++) {
+ for (i=0; i<bytes; i++) {
outw(buf[i], smbus_io_base + SMBHSTFIFO);
}
diff --git a/src/southbridge/amd/amd8111/early_ctrl.c b/src/southbridge/amd/amd8111/early_ctrl.c
index ece99ed..d84ef18 100644
--- a/src/southbridge/amd/amd8111/early_ctrl.c
+++ b/src/southbridge/amd/amd8111/early_ctrl.c
@@ -4,16 +4,16 @@
/* by yhlu 2005.10 */
static unsigned get_sbdn(unsigned bus)
{
- device_t dev;
+ device_t dev;
- /* Find the device.
- * There can only be one 8111 on a hypertransport chain/bus.
- */
- dev = pci_locate_device_on_bus(
- PCI_ID(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8111_PCI),
- bus);
+ /* Find the device.
+ * There can only be one 8111 on a hypertransport chain/bus.
+ */
+ dev = pci_locate_device_on_bus(
+ PCI_ID(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8111_PCI),
+ bus);
- return (dev>>15) & 0x1f;
+ return (dev>>15) & 0x1f;
}
@@ -40,34 +40,34 @@ static void enable_cf9(void)
void hard_reset(void)
{
- set_bios_reset();
- /* reset */
- enable_cf9();
- outb(0x0e, 0x0cf9); // make sure cf9 is enabled
+ set_bios_reset();
+ /* reset */
+ enable_cf9();
+ outb(0x0e, 0x0cf9); // make sure cf9 is enabled
}
void enable_fid_change_on_sb(unsigned sbbusn, unsigned sbdn)
{
- device_t dev;
+ device_t dev;
dev = PCI_DEV(sbbusn, sbdn+1, 3); // ACPI
- pci_write_config8(dev, 0x74, 4);
+ pci_write_config8(dev, 0x74, 4);
- /* set VFSMAF ( VID/FID System Management Action Field) to 2 */
- pci_write_config32(dev, 0x70, 2<<12);
+ /* set VFSMAF ( VID/FID System Management Action Field) to 2 */
+ pci_write_config32(dev, 0x70, 2<<12);
}
static void soft_reset_x(unsigned sbbusn, unsigned sbdn)
{
- device_t dev;
+ device_t dev;
dev = PCI_DEV(sbbusn, sbdn+1, 0); //ISA
- /* Reset */
- set_bios_reset();
- pci_write_config8(dev, 0x47, 1);
+ /* Reset */
+ set_bios_reset();
+ pci_write_config8(dev, 0x47, 1);
}
diff --git a/src/southbridge/amd/amd8111/ide.c b/src/southbridge/amd/amd8111/ide.c
index ef0cee1..a7eee35 100644
--- a/src/southbridge/amd/amd8111/ide.c
+++ b/src/southbridge/amd/amd8111/ide.c
@@ -33,8 +33,8 @@ static void ide_init(struct device *dev)
pci_write_config16(dev, 0x40, word);
- byte = 0x20 ; // Latency: 64-->32
- pci_write_config8(dev, 0xd, byte);
+ byte = 0x20 ; // Latency: 64-->32
+ pci_write_config8(dev, 0xd, byte);
word = 0x0f;
pci_write_config16(dev, 0x42, word);
diff --git a/src/southbridge/amd/amd8111/reset.c b/src/southbridge/amd/amd8111/reset.c
index 8824550..3cc1a0a 100644
--- a/src/southbridge/amd/amd8111/reset.c
+++ b/src/southbridge/amd/amd8111/reset.c
@@ -12,26 +12,26 @@
static void pci_write_config8(pci_devfn_t dev, unsigned where, unsigned char value)
{
- unsigned addr;
- addr = (dev>>4) | where;
- outl(0x80000000 | (addr & ~3), 0xCF8);
- outb(value, 0xCFC + (addr & 3));
+ unsigned addr;
+ addr = (dev>>4) | where;
+ outl(0x80000000 | (addr & ~3), 0xCF8);
+ outb(value, 0xCFC + (addr & 3));
}
static void pci_write_config32(pci_devfn_t dev, unsigned where, unsigned value)
{
unsigned addr;
- addr = (dev>>4) | where;
- outl(0x80000000 | (addr & ~3), 0xCF8);
- outl(value, 0xCFC);
+ addr = (dev>>4) | where;
+ outl(0x80000000 | (addr & ~3), 0xCF8);
+ outl(value, 0xCFC);
}
static unsigned pci_read_config32(pci_devfn_t dev, unsigned where)
{
unsigned addr;
- addr = (dev>>4) | where;
- outl(0x80000000 | (addr & ~3), 0xCF8);
- return inl(0xCFC);
+ addr = (dev>>4) | where;
+ outl(0x80000000 | (addr & ~3), 0xCF8);
+ return inl(0xCFC);
}
#define PCI_DEV_INVALID (0xffffffffU)
@@ -40,7 +40,7 @@ static pci_devfn_t pci_locate_device_on_bus(unsigned pci_id, unsigned bus)
pci_devfn_t dev, last;
dev = PCI_DEV(bus, 0, 0);
last = PCI_DEV(bus, 31, 7);
- for(; dev <= last; dev += PCI_DEV(0,0,1)) {
+ for (; dev <= last; dev += PCI_DEV(0,0,1)) {
unsigned int id;
id = pci_read_config32(dev, 0);
if (id == pci_id) {
diff --git a/src/southbridge/amd/amd8131/bridge.c b/src/southbridge/amd/amd8131/bridge.c
index 1587268..07f4a6a 100644
--- a/src/southbridge/amd/amd8131/bridge.c
+++ b/src/southbridge/amd/amd8131/bridge.c
@@ -19,8 +19,7 @@ static void amd8131_walk_children(struct bus *bus,
void (*visit)(device_t dev, void *ptr), void *ptr)
{
device_t child;
- for(child = bus->children; child; child = child->sibling)
- {
+ for (child = bus->children; child; child = child->sibling) {
if (child->path.type != DEVICE_PATH_PCI) {
continue;
}
@@ -72,7 +71,7 @@ static void amd8131_pcix_tune_dev(device_t dev, void *ptr)
sibs = info->master_devices - 1;
/* Count how many sibling functions this device has */
sib_funcs = 0;
- for(sib = dev->bus->children; sib; sib = sib->sibling) {
+ for (sib = dev->bus->children; sib; sib = sib->sibling) {
if (sib == dev) {
continue;
}
@@ -258,7 +257,7 @@ static void amd8131_scan_bus(struct bus *bus,
/* Don't allow the 8131 or any of it's parent busses to
* implement relaxed ordering. Errata #58
*/
- for(pbus = bus; !pbus->disable_relaxed_ordering; pbus = pbus->dev->bus) {
+ for (pbus = bus; !pbus->disable_relaxed_ordering; pbus = pbus->dev->bus) {
printk(BIOS_SPEW, "%s disabling relaxed ordering\n",
bus_path(pbus));
pbus->disable_relaxed_ordering = 1;
@@ -280,57 +279,57 @@ static void amd8131_pcix_init(device_t dev)
/* Enable memory write and invalidate ??? */
byte = pci_read_config8(dev, 0x04);
- byte |= 0x10;
- pci_write_config8(dev, 0x04, byte);
+ byte |= 0x10;
+ pci_write_config8(dev, 0x04, byte);
/* Set drive strength */
word = pci_read_config16(dev, 0xe0);
- word = 0x0404;
- pci_write_config16(dev, 0xe0, word);
+ word = 0x0404;
+ pci_write_config16(dev, 0xe0, word);
word = pci_read_config16(dev, 0xe4);
- word = 0x0404;
- pci_write_config16(dev, 0xe4, word);
+ word = 0x0404;
+ pci_write_config16(dev, 0xe4, word);
/* Set impedance */
word = pci_read_config16(dev, 0xe8);
- word = 0x0404;
- pci_write_config16(dev, 0xe8, word);
+ word = 0x0404;
+ pci_write_config16(dev, 0xe8, word);
/* Set discard unrequested prefetch data */
/* Errata #51 */
word = pci_read_config16(dev, 0x4c);
- word |= 1;
- pci_write_config16(dev, 0x4c, word);
+ word |= 1;
+ pci_write_config16(dev, 0x4c, word);
/* Set split transaction limits */
word = pci_read_config16(dev, 0xa8);
- pci_write_config16(dev, 0xaa, word);
+ pci_write_config16(dev, 0xaa, word);
word = pci_read_config16(dev, 0xac);
- pci_write_config16(dev, 0xae, word);
+ pci_write_config16(dev, 0xae, word);
/* Set up error reporting, enable all */
/* system error enable */
dword = pci_read_config32(dev, 0x04);
- dword |= (1<<8);
- pci_write_config32(dev, 0x04, dword);
+ dword |= (1<<8);
+ pci_write_config32(dev, 0x04, dword);
/* system and error parity enable */
dword = pci_read_config32(dev, 0x3c);
- dword |= (3<<16);
- pci_write_config32(dev, 0x3c, dword);
+ dword |= (3<<16);
+ pci_write_config32(dev, 0x3c, dword);
/* NMI enable */
nmi_option = NMI_OFF;
get_option(&nmi_option, "nmi");
- if(nmi_option) {
+ if (nmi_option) {
dword = pci_read_config32(dev, 0x44);
- dword |= (1<<0);
- pci_write_config32(dev, 0x44, dword);
+ dword |= (1<<0);
+ pci_write_config32(dev, 0x44, dword);
}
/* Set up CRC flood enable */
dword = pci_read_config32(dev, 0xc0);
- if(dword) { /* do device A only */
+ if (dword) { /* do device A only */
dword = pci_read_config32(dev, 0xc4);
dword |= (1<<1);
pci_write_config32(dev, 0xc4, dword);
@@ -377,22 +376,22 @@ static void bridge_set_resources(struct device *dev)
static struct device_operations pcix_ops = {
#if BRIDGE_40_BIT_SUPPORT
- .read_resources = bridge_read_resources,
- .set_resources = bridge_set_resources,
+ .read_resources = bridge_read_resources,
+ .set_resources = bridge_set_resources,
#else
- .read_resources = pci_bus_read_resources,
- .set_resources = pci_dev_set_resources,
+ .read_resources = pci_bus_read_resources,
+ .set_resources = pci_dev_set_resources,
#endif
.enable_resources = pci_bus_enable_resources,
- .init = amd8131_pcix_init,
- .scan_bus = amd8131_scan_bridge,
+ .init = amd8131_pcix_init,
+ .scan_bus = amd8131_scan_bridge,
.reset_bus = pci_bus_reset,
};
static const struct pci_driver pcix_driver __pci_driver = {
- .ops = &pcix_ops,
- .vendor = PCI_VENDOR_ID_AMD,
- .device = 0x7450,
+ .ops = &pcix_ops,
+ .vendor = PCI_VENDOR_ID_AMD,
+ .device = 0x7450,
};
diff --git a/src/southbridge/amd/amd8132/bridge.c b/src/southbridge/amd/amd8132/bridge.c
index 6979a1e..b546ef3 100644
--- a/src/southbridge/amd/amd8132/bridge.c
+++ b/src/southbridge/amd/amd8132/bridge.c
@@ -32,8 +32,7 @@ static void amd8132_walk_children(struct bus *bus,
void (*visit)(device_t dev, void *ptr), void *ptr)
{
device_t child;
- for(child = bus->children; child; child = child->sibling)
- {
+ for (child = bus->children; child; child = child->sibling) {
if (child->path.type != DEVICE_PATH_PCI) {
continue;
}
@@ -126,11 +125,11 @@ static void amd8132_pcix_tune_dev(device_t dev, void *ptr)
cmd |= max_tran << 4;
}
- /* Don't attempt to handle PCI-X errors */
- cmd &= ~PCI_X_CMD_DPERR_E;
- if (orig_cmd != cmd) {
- pci_write_config16(dev, cap + PCI_X_CMD, cmd);
- }
+ /* Don't attempt to handle PCI-X errors */
+ cmd &= ~PCI_X_CMD_DPERR_E;
+ if (orig_cmd != cmd) {
+ pci_write_config16(dev, cap + PCI_X_CMD, cmd);
+ }
}
@@ -203,18 +202,18 @@ static void amd8132_pcix_init(device_t dev)
unsigned chip_rev;
/* Find the revision of the 8132 */
- chip_rev = pci_read_config8(dev, PCI_CLASS_REVISION);
+ chip_rev = pci_read_config8(dev, PCI_CLASS_REVISION);
/* Enable memory write and invalidate ??? */
dword = pci_read_config32(dev, 0x04);
- dword |= 0x10;
+ dword |= 0x10;
dword &= ~(1<<6); // PERSP Parity Error Response
- pci_write_config32(dev, 0x04, dword);
+ pci_write_config32(dev, 0x04, dword);
if (chip_rev == 0x01) {
/* Errata #37 */
byte = pci_read_config8(dev, 0x0c);
- if(byte == 0x08 )
+ if (byte == 0x08 )
pci_write_config8(dev, 0x0c, 0x10);
#if 0
@@ -229,58 +228,58 @@ static void amd8132_pcix_init(device_t dev)
/* Set up error reporting, enable all */
/* system error enable */
dword = pci_read_config32(dev, 0x04);
- dword |= (1<<8);
- pci_write_config32(dev, 0x04, dword);
+ dword |= (1<<8);
+ pci_write_config32(dev, 0x04, dword);
/* system and error parity enable */
dword = pci_read_config32(dev, 0x3c);
- dword |= (3<<16);
- pci_write_config32(dev, 0x3c, dword);
+ dword |= (3<<16);
+ pci_write_config32(dev, 0x3c, dword);
- dword = pci_read_config32(dev, 0x40);
-// dword &= ~(1<<31); /* WriteChainEnable */
+ dword = pci_read_config32(dev, 0x40);
+// dword &= ~(1<<31); /* WriteChainEnable */
dword |= (1<<31);
dword |= (1<<7);// must set to 1
dword |= (3<<21); //PCIErrorSerrDisable
- pci_write_config32(dev, 0x40, dword);
+ pci_write_config32(dev, 0x40, dword);
- /* EXTARB = 1, COMPAT = 0 */
- dword = pci_read_config32(dev, 0x48);
- dword |= (1<<3);
+ /* EXTARB = 1, COMPAT = 0 */
+ dword = pci_read_config32(dev, 0x48);
+ dword |= (1<<3);
dword &= ~(1<<0);
dword |= (1<<15); //CLEARPCILOG_L
dword |= (1<<19); //PERR FATAL Enable
dword |= (1<<22); // SERR FATAL Enable
dword |= (1<<23); // LPMARBENABLE
dword |= (0x61<<24); //LPMARBCOUNT
- pci_write_config32(dev, 0x48, dword);
+ pci_write_config32(dev, 0x48, dword);
- dword = pci_read_config32(dev, 0x4c);
- dword |= (1<<6); //Initial prefetch for memory read line request
+ dword = pci_read_config32(dev, 0x4c);
+ dword |= (1<<6); //Initial prefetch for memory read line request
dword |= (1<<9); //continuous prefetch Enable for memory read line request
- pci_write_config32(dev, 0x4c, dword);
+ pci_write_config32(dev, 0x4c, dword);
- /* Disable Single-Bit-Error Correction [30] = 0 */
- dword = pci_read_config32(dev, 0x70);
- dword &= ~(1<<30);
- pci_write_config32(dev, 0x70, dword);
+ /* Disable Single-Bit-Error Correction [30] = 0 */
+ dword = pci_read_config32(dev, 0x70);
+ dword &= ~(1<<30);
+ pci_write_config32(dev, 0x70, dword);
//link
- dword = pci_read_config32(dev, 0xd4);
- dword |= (0x5c<<16);
- pci_write_config32(dev, 0xd4, dword);
+ dword = pci_read_config32(dev, 0xd4);
+ dword |= (0x5c<<16);
+ pci_write_config32(dev, 0xd4, dword);
- /* TxSlack0 [16:17] = 0, RxHwLookahdEn0 [18] = 1, TxSlack1 [24:25] = 0, RxHwLookahdEn1 [26] = 1 */
- dword = pci_read_config32(dev, 0xdc);
+ /* TxSlack0 [16:17] = 0, RxHwLookahdEn0 [18] = 1, TxSlack1 [24:25] = 0, RxHwLookahdEn1 [26] = 1 */
+ dword = pci_read_config32(dev, 0xdc);
dword |= (1<<1) | (1<<4); // stream disable 1 to 0 , DBLINSRATE
- dword |= (1<<18)|(1<<26);
- dword &= ~((3<<16)|(3<<24));
- pci_write_config32(dev, 0xdc, dword);
+ dword |= (1<<18)|(1<<26);
+ dword &= ~((3<<16)|(3<<24));
+ pci_write_config32(dev, 0xdc, dword);
/* Set up CRC flood enable */
dword = pci_read_config32(dev, 0xc0);
- if(dword) { /* do device A only */
+ if (dword) { /* do device A only */
#if 0
dword = pci_read_config32(dev, 0xc4);
dword |= (1<<1);
@@ -290,12 +289,12 @@ static void amd8132_pcix_init(device_t dev)
pci_write_config32(dev, 0xc8, dword);
#endif
- if (chip_rev == 0x11) {
- /* [18] Clock Gate Enable = 1 */
- dword = pci_read_config32(dev, 0xf0);
- dword |= 0x00040008;
- pci_write_config32(dev, 0xf0, dword);
- }
+ if (chip_rev == 0x11) {
+ /* [18] Clock Gate Enable = 1 */
+ dword = pci_read_config32(dev, 0xf0);
+ dword |= 0x00040008;
+ pci_write_config32(dev, 0xf0, dword);
+ }
}
return;
@@ -337,22 +336,22 @@ static void bridge_set_resources(struct device *dev)
static struct device_operations pcix_ops = {
#if BRIDGE_40_BIT_SUPPORT
- .read_resources = bridge_read_resources,
- .set_resources = bridge_set_resources,
+ .read_resources = bridge_read_resources,
+ .set_resources = bridge_set_resources,
#else
- .read_resources = pci_bus_read_resources,
- .set_resources = pci_dev_set_resources,
+ .read_resources = pci_bus_read_resources,
+ .set_resources = pci_dev_set_resources,
#endif
.enable_resources = pci_bus_enable_resources,
- .init = amd8132_pcix_init,
- .scan_bus = amd8132_scan_bridge,
+ .init = amd8132_pcix_init,
+ .scan_bus = amd8132_scan_bridge,
.reset_bus = pci_bus_reset,
};
static const struct pci_driver pcix_driver __pci_driver = {
- .ops = &pcix_ops,
- .vendor = PCI_VENDOR_ID_AMD,
- .device = 0x7458,
+ .ops = &pcix_ops,
+ .vendor = PCI_VENDOR_ID_AMD,
+ .device = 0x7458,
};
static void ioapic_enable(device_t dev)
@@ -369,39 +368,39 @@ static void ioapic_enable(device_t dev)
}
static void amd8132_ioapic_init(device_t dev)
{
- uint32_t dword;
- unsigned chip_rev;
+ uint32_t dword;
+ unsigned chip_rev;
- /* Find the revision of the 8132 */
- chip_rev = pci_read_config8(dev, PCI_CLASS_REVISION);
+ /* Find the revision of the 8132 */
+ chip_rev = pci_read_config8(dev, PCI_CLASS_REVISION);
- if (chip_rev == 0x01) {
+ if (chip_rev == 0x01) {
#if 0
- /* Errata #43 */
- dword = pci_read_config32(dev, 0xc8);
+ /* Errata #43 */
+ dword = pci_read_config32(dev, 0xc8);
dword |= (0x3<<23);
pci_write_config32(dev, 0xc8, dword);
#endif
- }
-
-
- if ( (chip_rev == 0x11) ||(chip_rev == 0x12) ) {
- //for b1 b2
- /* Errata #73 */
- dword = pci_read_config32(dev, 0x80);
- dword |= (0x1f<<5);
- pci_write_config32(dev, 0x80, dword);
- dword = pci_read_config32(dev, 0x88);
- dword |= (0x1f<<5);
- pci_write_config32(dev, 0x88, dword);
-
- /* Errata #74 */
- dword = pci_read_config32(dev, 0x7c);
- dword &= ~(0x3<<30);
- dword |= (0x01<<30);
- pci_write_config32(dev, 0x7c, dword);
- }
+ }
+
+
+ if ( (chip_rev == 0x11) ||(chip_rev == 0x12) ) {
+ //for b1 b2
+ /* Errata #73 */
+ dword = pci_read_config32(dev, 0x80);
+ dword |= (0x1f<<5);
+ pci_write_config32(dev, 0x80, dword);
+ dword = pci_read_config32(dev, 0x88);
+ dword |= (0x1f<<5);
+ pci_write_config32(dev, 0x88, dword);
+
+ /* Errata #74 */
+ dword = pci_read_config32(dev, 0x7c);
+ dword &= ~(0x3<<30);
+ dword |= (0x01<<30);
+ pci_write_config32(dev, 0x7c, dword);
+ }
}
diff --git a/src/southbridge/amd/amd8151/agp3.c b/src/southbridge/amd/amd8151/agp3.c
index 57699ff..18dd6d5 100644
--- a/src/southbridge/amd/amd8151/agp3.c
+++ b/src/southbridge/amd/amd8151/agp3.c
@@ -66,7 +66,7 @@ static void agp3dev_enable(device_t dev)
}
static struct pci_operations pci_ops_pci_dev = {
- .set_subsystem = pci_dev_set_subsystem,
+ .set_subsystem = pci_dev_set_subsystem,
};
static struct device_operations agp3dev_ops = {
diff --git a/src/southbridge/amd/cimx/sb700/Platform.h b/src/southbridge/amd/cimx/sb700/Platform.h
index 7562417..7476cb9 100644
--- a/src/southbridge/amd/cimx/sb700/Platform.h
+++ b/src/southbridge/amd/cimx/sb700/Platform.h
@@ -62,7 +62,7 @@ void TraceCode ( UINT32 Level, UINT32 Code);
#if CONFIG_REDIRECT_SBCIMX_TRACE_TO_SERIAL
#define TRACE(Arguments) printk Arguments
#else
- #define TRACE(Arguments) do {} while(0)
+ #define TRACE(Arguments) do {} while (0)
#endif
#define TRACECODE(Arguments)
#endif
diff --git a/src/southbridge/amd/cimx/sb700/reset.c b/src/southbridge/amd/cimx/sb700/reset.c
index 9a98760..a5c42b7 100644
--- a/src/southbridge/amd/cimx/sb700/reset.c
+++ b/src/southbridge/amd/cimx/sb700/reset.c
@@ -32,7 +32,7 @@ static inline void set_bios_reset(void)
int i;
nodes = ((pci_read_config32(PCI_DEV(CONFIG_CBB, CONFIG_CDB, 0), 0x60) >> 4) & 7) + 1;
- for(i = 0; i < nodes; i++) {
+ for (i = 0; i < nodes; i++) {
dev = NODE_PCI(i, 0);
htic = pci_read_config32(dev, HT_INIT_CONTROL);
htic &= ~HTIC_BIOSR_Detect;
diff --git a/src/southbridge/amd/cimx/sb800/early.c b/src/southbridge/amd/cimx/sb800/early.c
index 2a10c0e..866353d 100644
--- a/src/southbridge/amd/cimx/sb800/early.c
+++ b/src/southbridge/amd/cimx/sb800/early.c
@@ -66,6 +66,6 @@ void sb800_clk_output_48Mhz(void)
/* AcpiMMioDecodeEn */
RWPMIO(SB_PMIOA_REG24, AccWidthUint8, ~(BIT0 + BIT1), BIT0);
- *(volatile u32 *)(ACPI_MMIO_BASE + MISC_BASE + 0x40) &= ~((1 << 0) | (1 << 2)); /* 48Mhz */
- *(volatile u32 *)(ACPI_MMIO_BASE + MISC_BASE + 0x40) |= 1 << 1; /* 48Mhz */
+ *(volatile u32 *)(ACPI_MMIO_BASE + MISC_BASE + 0x40) &= ~((1 << 0) | (1 << 2)); /* 48Mhz */
+ *(volatile u32 *)(ACPI_MMIO_BASE + MISC_BASE + 0x40) |= 1 << 1; /* 48Mhz */
}
diff --git a/src/southbridge/amd/cimx/sb800/late.c b/src/southbridge/amd/cimx/sb800/late.c
index 693190f..fa47a96 100644
--- a/src/southbridge/amd/cimx/sb800/late.c
+++ b/src/southbridge/amd/cimx/sb800/late.c
@@ -151,21 +151,21 @@ unsigned long acpi_fill_mcfg(unsigned long current)
}
static struct device_operations lpc_ops = {
- .read_resources = lpc_read_resources,
- .set_resources = lpc_set_resources,
- .enable_resources = pci_dev_enable_resources,
+ .read_resources = lpc_read_resources,
+ .set_resources = lpc_set_resources,
+ .enable_resources = pci_dev_enable_resources,
#if IS_ENABLED(CONFIG_HAVE_ACPI_TABLES)
.write_acpi_tables = acpi_write_hpet,
#endif
- .init = lpc_init,
- .scan_bus = scan_lpc_bus,
- .ops_pci = &lops_pci,
+ .init = lpc_init,
+ .scan_bus = scan_lpc_bus,
+ .ops_pci = &lops_pci,
};
static const struct pci_driver lpc_driver __pci_driver = {
- .ops = &lpc_ops,
- .vendor = PCI_VENDOR_ID_ATI,
- .device = PCI_DEVICE_ID_ATI_SB800_LPC,
+ .ops = &lpc_ops,
+ .vendor = PCI_VENDOR_ID_ATI,
+ .device = PCI_DEVICE_ID_ATI_SB800_LPC,
};
static struct device_operations sata_ops = {
@@ -226,34 +226,34 @@ static const struct pci_driver usb_ohci4_driver __pci_driver = {
static struct device_operations azalia_ops = {
- .read_resources = pci_dev_read_resources,
- .set_resources = pci_dev_set_resources,
- .enable_resources = pci_dev_enable_resources,
- .init = 0,
- .scan_bus = 0,
- .ops_pci = &lops_pci,
+ .read_resources = pci_dev_read_resources,
+ .set_resources = pci_dev_set_resources,
+ .enable_resources = pci_dev_enable_resources,
+ .init = 0,
+ .scan_bus = 0,
+ .ops_pci = &lops_pci,
};
static const struct pci_driver azalia_driver __pci_driver = {
- .ops = &azalia_ops,
- .vendor = PCI_VENDOR_ID_ATI,
- .device = PCI_DEVICE_ID_ATI_SB800_HDA,
+ .ops = &azalia_ops,
+ .vendor = PCI_VENDOR_ID_ATI,
+ .device = PCI_DEVICE_ID_ATI_SB800_HDA,
};
static struct device_operations gec_ops = {
- .read_resources = pci_dev_read_resources,
- .set_resources = pci_dev_set_resources,
- .enable_resources = pci_dev_enable_resources,
- .init = 0,
- .scan_bus = 0,
- .ops_pci = &lops_pci,
+ .read_resources = pci_dev_read_resources,
+ .set_resources = pci_dev_set_resources,
+ .enable_resources = pci_dev_enable_resources,
+ .init = 0,
+ .scan_bus = 0,
+ .ops_pci = &lops_pci,
};
static const struct pci_driver gec_driver __pci_driver = {
- .ops = &gec_ops,
- .vendor = PCI_VENDOR_ID_ATI,
- .device = PCI_DEVICE_ID_ATI_SB800_GEC,
+ .ops = &gec_ops,
+ .vendor = PCI_VENDOR_ID_ATI,
+ .device = PCI_DEVICE_ID_ATI_SB800_GEC,
};
/**
diff --git a/src/southbridge/amd/cimx/sb800/reset.c b/src/southbridge/amd/cimx/sb800/reset.c
index 9a98760..a5c42b7 100644
--- a/src/southbridge/amd/cimx/sb800/reset.c
+++ b/src/southbridge/amd/cimx/sb800/reset.c
@@ -32,7 +32,7 @@ static inline void set_bios_reset(void)
int i;
nodes = ((pci_read_config32(PCI_DEV(CONFIG_CBB, CONFIG_CDB, 0), 0x60) >> 4) & 7) + 1;
- for(i = 0; i < nodes; i++) {
+ for (i = 0; i < nodes; i++) {
dev = NODE_PCI(i, 0);
htic = pci_read_config32(dev, HT_INIT_CONTROL);
htic &= ~HTIC_BIOSR_Detect;
diff --git a/src/southbridge/amd/cimx/sb800/smbus.c b/src/southbridge/amd/cimx/sb800/smbus.c
index 93ac0aa..80395f1 100644
--- a/src/southbridge/amd/cimx/sb800/smbus.c
+++ b/src/southbridge/amd/cimx/sb800/smbus.c
@@ -63,7 +63,7 @@ int do_smbus_recv_byte(u32 smbus_io_base, u32 device)
u8 byte;
if (smbus_wait_until_ready(smbus_io_base) < 0) {
- printk(BIOS_DEBUG, "SB800 - Smbus.c - do_smbus_recv_byte - smbus not ready.\n");
+ printk(BIOS_DEBUG, "SB800 - Smbus.c - do_smbus_recv_byte - smbus not ready.\n");
return -2; /* not ready */
}
@@ -93,7 +93,7 @@ int do_smbus_send_byte(u32 smbus_io_base, u32 device, u8 val)
u8 byte;
if (smbus_wait_until_ready(smbus_io_base) < 0) {
- printk(BIOS_DEBUG, "SB800 - Smbus.c - do_smbus_send_byte - smbus not ready.\n");
+ printk(BIOS_DEBUG, "SB800 - Smbus.c - do_smbus_send_byte - smbus not ready.\n");
return -2; /* not ready */
}
@@ -123,7 +123,7 @@ int do_smbus_read_byte(u32 smbus_io_base, u32 device, u32 address)
u8 byte;
if (smbus_wait_until_ready(smbus_io_base) < 0) {
- printk(BIOS_DEBUG, "SB800 - Smbus.c - do_smbus_read_byte - smbus not ready.\n");
+ printk(BIOS_DEBUG, "SB800 - Smbus.c - do_smbus_read_byte - smbus not ready.\n");
return -2; /* not ready */
}
@@ -156,7 +156,7 @@ int do_smbus_write_byte(u32 smbus_io_base, u32 device, u32 address, u8 val)
u8 byte;
if (smbus_wait_until_ready(smbus_io_base) < 0) {
- printk(BIOS_DEBUG, "SB800 - Smbus.c - do_smbus_write_byte - smbus not ready.\n");
+ printk(BIOS_DEBUG, "SB800 - Smbus.c - do_smbus_write_byte - smbus not ready.\n");
return -2; /* not ready */
}
diff --git a/src/southbridge/amd/cimx/sb900/cfg.c b/src/southbridge/amd/cimx/sb900/cfg.c
index be54197..bc7e742 100644
--- a/src/southbridge/amd/cimx/sb900/cfg.c
+++ b/src/southbridge/amd/cimx/sb900/cfg.c
@@ -28,7 +28,7 @@
void sb900_cimx_config(AMDSBCFG *sb_config)
{
if (!sb_config) {
- printk(BIOS_INFO, "SB900 - Cfg.c - sb900_cimx_config - No sb_config.\n");
+ printk(BIOS_INFO, "SB900 - Cfg.c - sb900_cimx_config - No sb_config.\n");
return;
}
printk(BIOS_INFO, "SB900 - Cfg.c - sb900_cimx_config - Start.\n");
@@ -257,7 +257,7 @@ void sb900_cimx_config(AMDSBCFG *sb_config)
void SbPowerOnInit_Config(AMDSBCFG *sb_config)
{
if (!sb_config) {
- printk(BIOS_INFO, "SB900 - Cfg.c - SbPowerOnInit_Config - No sb_config.\n");
+ printk(BIOS_INFO, "SB900 - Cfg.c - SbPowerOnInit_Config - No sb_config.\n");
return;
}
printk(BIOS_INFO, "SB900 - Cfg.c - SbPowerOnInit_Config - Start.\n");
diff --git a/src/southbridge/amd/cimx/sb900/early.c b/src/southbridge/amd/cimx/sb900/early.c
index 10645e1..d39de4b 100644
--- a/src/southbridge/amd/cimx/sb900/early.c
+++ b/src/southbridge/amd/cimx/sb900/early.c
@@ -60,7 +60,7 @@ void sb_poweron_init(void)
outb(0xEA, 0xCD6);
data = inb(0xCD7);
data &= !BIT0;
- if(!CONFIG_PCIB_ENABLE) {
+ if (!CONFIG_PCIB_ENABLE) {
data |= BIT0;
}
outb(data, 0xCD7);
diff --git a/src/southbridge/amd/cimx/sb900/late.c b/src/southbridge/amd/cimx/sb900/late.c
index f078c51..65c2446 100644
--- a/src/southbridge/amd/cimx/sb900/late.c
+++ b/src/southbridge/amd/cimx/sb900/late.c
@@ -121,21 +121,21 @@ unsigned long acpi_fill_mcfg(unsigned long current)
}
static struct device_operations lpc_ops = {
- .read_resources = lpc_read_resources,
- .set_resources = lpc_set_resources,
- .enable_resources = lpc_enable_resources,
- .init = lpc_init,
+ .read_resources = lpc_read_resources,
+ .set_resources = lpc_set_resources,
+ .enable_resources = lpc_enable_resources,
+ .init = lpc_init,
#if IS_ENABLED(CONFIG_HAVE_ACPI_TABLES)
.write_acpi_tables = acpi_write_hpet,
#endif
- .scan_bus = scan_lpc_bus,
- .ops_pci = &lops_pci,
+ .scan_bus = scan_lpc_bus,
+ .ops_pci = &lops_pci,
};
static const struct pci_driver lpc_driver __pci_driver = {
- .ops = &lpc_ops,
- .vendor = PCI_VENDOR_ID_AMD,
- .device = PCI_DEVICE_ID_ATI_SB900_LPC,
+ .ops = &lpc_ops,
+ .vendor = PCI_VENDOR_ID_AMD,
+ .device = PCI_DEVICE_ID_ATI_SB900_LPC,
};
@@ -239,18 +239,18 @@ static void azalia_init(struct device *dev)
}
static struct device_operations azalia_ops = {
- .read_resources = pci_dev_read_resources,
- .set_resources = pci_dev_set_resources,
- .enable_resources = pci_dev_enable_resources,
- .init = azalia_init,
- .scan_bus = 0,
- .ops_pci = &lops_pci,
+ .read_resources = pci_dev_read_resources,
+ .set_resources = pci_dev_set_resources,
+ .enable_resources = pci_dev_enable_resources,
+ .init = azalia_init,
+ .scan_bus = 0,
+ .ops_pci = &lops_pci,
};
static const struct pci_driver azalia_driver __pci_driver = {
- .ops = &azalia_ops,
- .vendor = PCI_VENDOR_ID_AMD,
- .device = PCI_DEVICE_ID_ATI_SB900_HDA,
+ .ops = &azalia_ops,
+ .vendor = PCI_VENDOR_ID_AMD,
+ .device = PCI_DEVICE_ID_ATI_SB900_HDA,
};
@@ -263,18 +263,18 @@ static void gec_init(struct device *dev)
}
static struct device_operations gec_ops = {
- .read_resources = pci_dev_read_resources,
- .set_resources = pci_dev_set_resources,
- .enable_resources = pci_dev_enable_resources,
- .init = gec_init,
- .scan_bus = 0,
- .ops_pci = &lops_pci,
+ .read_resources = pci_dev_read_resources,
+ .set_resources = pci_dev_set_resources,
+ .enable_resources = pci_dev_enable_resources,
+ .init = gec_init,
+ .scan_bus = 0,
+ .ops_pci = &lops_pci,
};
static const struct pci_driver gec_driver __pci_driver = {
- .ops = &gec_ops,
- .vendor = PCI_VENDOR_ID_AMD,
- .device = PCI_DEVICE_ID_ATI_SB900_GEC,
+ .ops = &gec_ops,
+ .vendor = PCI_VENDOR_ID_AMD,
+ .device = PCI_DEVICE_ID_ATI_SB900_GEC,
};
@@ -286,19 +286,19 @@ static void pcie_init(device_t dev)
}
static struct device_operations pci_ops = {
- .read_resources = pci_bus_read_resources,
- .set_resources = pci_dev_set_resources,
- .enable_resources = pci_bus_enable_resources,
- .init = pcie_init,
- .scan_bus = pci_scan_bridge,
- .reset_bus = pci_bus_reset,
- .ops_pci = &lops_pci,
+ .read_resources = pci_bus_read_resources,
+ .set_resources = pci_dev_set_resources,
+ .enable_resources = pci_bus_enable_resources,
+ .init = pcie_init,
+ .scan_bus = pci_scan_bridge,
+ .reset_bus = pci_bus_reset,
+ .ops_pci = &lops_pci,
};
static const struct pci_driver pci_driver __pci_driver = {
- .ops = &pci_ops,
- .vendor = PCI_VENDOR_ID_AMD,
- .device = PCI_DEVICE_ID_ATI_SB900_PCI,
+ .ops = &pci_ops,
+ .vendor = PCI_VENDOR_ID_AMD,
+ .device = PCI_DEVICE_ID_ATI_SB900_PCI,
};
@@ -315,30 +315,30 @@ struct device_operations bridge_ops = {
/* 0:15:0 PCIe PortA */
static const struct pci_driver PORTA_driver __pci_driver = {
- .ops = &bridge_ops,
- .vendor = PCI_VENDOR_ID_AMD,
- .device = PCI_DEVICE_ID_ATI_SB900_PCIEA,
+ .ops = &bridge_ops,
+ .vendor = PCI_VENDOR_ID_AMD,
+ .device = PCI_DEVICE_ID_ATI_SB900_PCIEA,
};
/* 0:15:1 PCIe PortB */
static const struct pci_driver PORTB_driver __pci_driver = {
- .ops = &bridge_ops,
- .vendor = PCI_VENDOR_ID_AMD,
- .device = PCI_DEVICE_ID_ATI_SB900_PCIEB,
+ .ops = &bridge_ops,
+ .vendor = PCI_VENDOR_ID_AMD,
+ .device = PCI_DEVICE_ID_ATI_SB900_PCIEB,
};
/* 0:15:2 PCIe PortC */
static const struct pci_driver PORTC_driver __pci_driver = {
- .ops = &bridge_ops,
- .vendor = PCI_VENDOR_ID_AMD,
- .device = PCI_DEVICE_ID_ATI_SB900_PCIEC,
+ .ops = &bridge_ops,
+ .vendor = PCI_VENDOR_ID_AMD,
+ .device = PCI_DEVICE_ID_ATI_SB900_PCIEC,
};
/* 0:15:3 PCIe PortD */
static const struct pci_driver PORTD_driver __pci_driver = {
- .ops = &bridge_ops,
- .vendor = PCI_VENDOR_ID_AMD,
- .device = PCI_DEVICE_ID_ATI_SB900_PCIED,
+ .ops = &bridge_ops,
+ .vendor = PCI_VENDOR_ID_AMD,
+ .device = PCI_DEVICE_ID_ATI_SB900_PCIED,
};
diff --git a/src/southbridge/amd/cimx/sb900/reset.c b/src/southbridge/amd/cimx/sb900/reset.c
index 9a98760..a5c42b7 100644
--- a/src/southbridge/amd/cimx/sb900/reset.c
+++ b/src/southbridge/amd/cimx/sb900/reset.c
@@ -32,7 +32,7 @@ static inline void set_bios_reset(void)
int i;
nodes = ((pci_read_config32(PCI_DEV(CONFIG_CBB, CONFIG_CDB, 0), 0x60) >> 4) & 7) + 1;
- for(i = 0; i < nodes; i++) {
+ for (i = 0; i < nodes; i++) {
dev = NODE_PCI(i, 0);
htic = pci_read_config32(dev, HT_INIT_CONTROL);
htic &= ~HTIC_BIOSR_Detect;
diff --git a/src/southbridge/amd/cimx/sb900/smbus.c b/src/southbridge/amd/cimx/sb900/smbus.c
index 358bd48..7d11898 100644
--- a/src/southbridge/amd/cimx/sb900/smbus.c
+++ b/src/southbridge/amd/cimx/sb900/smbus.c
@@ -63,7 +63,7 @@ int do_smbus_recv_byte(u32 smbus_io_base, u32 device)
u8 byte;
if (smbus_wait_until_ready(smbus_io_base) < 0) {
- printk(BIOS_INFO, "SB900 - Smbus.c - do_smbus_recv_byte - smbus no ready.\n");
+ printk(BIOS_INFO, "SB900 - Smbus.c - do_smbus_recv_byte - smbus no ready.\n");
return -2; /* not ready */
}
@@ -93,7 +93,7 @@ int do_smbus_send_byte(u32 smbus_io_base, u32 device, u8 val)
u8 byte;
if (smbus_wait_until_ready(smbus_io_base) < 0) {
- printk(BIOS_INFO, "SB900 - Smbus.c - do_smbus_send_byte - smbus no ready.\n");
+ printk(BIOS_INFO, "SB900 - Smbus.c - do_smbus_send_byte - smbus no ready.\n");
return -2; /* not ready */
}
@@ -123,7 +123,7 @@ int do_smbus_read_byte(u32 smbus_io_base, u32 device, u32 address)
u8 byte;
if (smbus_wait_until_ready(smbus_io_base) < 0) {
- printk(BIOS_INFO, "SB900 - Smbus.c - do_smbus_read_byte - smbus no ready.\n");
+ printk(BIOS_INFO, "SB900 - Smbus.c - do_smbus_read_byte - smbus no ready.\n");
return -2; /* not ready */
}
@@ -156,7 +156,7 @@ int do_smbus_write_byte(u32 smbus_io_base, u32 device, u32 address, u8 val)
u8 byte;
if (smbus_wait_until_ready(smbus_io_base) < 0) {
- printk(BIOS_INFO, "SB900 - Smbus.c - do_smbus_write_byte - smbus no ready.\n");
+ printk(BIOS_INFO, "SB900 - Smbus.c - do_smbus_write_byte - smbus no ready.\n");
return -2; /* not ready */
}
diff --git a/src/southbridge/amd/common/amd_pci_util.c b/src/southbridge/amd/common/amd_pci_util.c
index 9756483..b6b2bd3 100644
--- a/src/southbridge/amd/common/amd_pci_util.c
+++ b/src/southbridge/amd/common/amd_pci_util.c
@@ -58,7 +58,7 @@ void write_pci_int_table (void)
{
u8 byte;
- if(picr_data_ptr == NULL || intr_data_ptr == NULL){
+ if (picr_data_ptr == NULL || intr_data_ptr == NULL){
printk(BIOS_ERR, "Warning: Can't write PCI_INTR 0xC00/0xC01 registers because\n"
"'mainboard_picr_data' or 'mainboard_intr_data' tables are NULL\n");
return;
diff --git a/src/southbridge/amd/cs5535/chipsetinit.c b/src/southbridge/amd/cs5535/chipsetinit.c
index 05fb6eb..a6c0084 100644
--- a/src/southbridge/amd/cs5535/chipsetinit.c
+++ b/src/southbridge/amd/cs5535/chipsetinit.c
@@ -328,7 +328,7 @@ chipsetinit(void)
i = 0;
csi = &SB_MASTER_CONF_TABLE[i];
- for(; csi->msrnum; csi++){
+ for (; csi->msrnum; csi++){
msr.lo = csi->msr.lo;
msr.hi = csi->msr.hi;
wrmsr(csi->msrnum, msr); // MSR - see table above
@@ -347,7 +347,7 @@ chipsetinit(void)
{
csi = CS5535_CLOCK_GATING_TABLE;
- for(; csi->msrnum; csi++){
+ for (; csi->msrnum; csi++){
msr.lo = csi->msr.lo;
msr.hi = csi->msr.hi;
wrmsr(csi->msrnum, msr); // MSR - see table above
diff --git a/src/southbridge/amd/cs5535/cs5535.c b/src/southbridge/amd/cs5535/cs5535.c
index 70b8386..3f6e48f 100644
--- a/src/southbridge/amd/cs5535/cs5535.c
+++ b/src/southbridge/amd/cs5535/cs5535.c
@@ -56,9 +56,9 @@ static void dump_south(struct device *dev)
{
int i, j;
- for(i=0; i<256; i+=16) {
+ for (i=0; i<256; i+=16) {
printk(BIOS_DEBUG, "0x%02x: ", i);
- for(j=0; j<16; j++)
+ for (j=0; j<16; j++)
printk(BIOS_DEBUG, "%02x ", pci_read_config8(dev, i+j));
printk(BIOS_DEBUG, "\n");
}
@@ -103,9 +103,9 @@ static const struct pci_driver cs5535_pci_driver __pci_driver = {
};
struct chip_operations southbridge_amd_cs5535_ops = {
- CHIP_NAME("AMD Geode CS5535 Southbridge")
- /* This is only called when this device is listed in the
- * static device tree.
- */
- .enable_dev = southbridge_enable,
+ CHIP_NAME("AMD Geode CS5535 Southbridge")
+ /* This is only called when this device is listed in the
+ * static device tree.
+ */
+ .enable_dev = southbridge_enable,
};
diff --git a/src/southbridge/amd/cs5535/early_setup.c b/src/southbridge/amd/cs5535/early_setup.c
index 1030aa0..935153f 100644
--- a/src/southbridge/amd/cs5535/early_setup.c
+++ b/src/southbridge/amd/cs5535/early_setup.c
@@ -34,7 +34,7 @@ static void cs5535_setup_idsel(void)
outl(0x1 << (CS5535_DEV_NUM + 10), 0);
}
-static void cs5535_usb_swapsif(void)
+static void cs5535_usb_swapsif (void)
{
msr_t msr;
@@ -133,7 +133,7 @@ static void cs5535_early_setup(void)
printk(BIOS_DEBUG, "Setup idsel\n");
cs5535_setup_idsel();
printk(BIOS_DEBUG, "Setup iobase\n");
- cs5535_usb_swapsif();
+ cs5535_usb_swapsif ();
cs5535_setup_iobase();
printk(BIOS_DEBUG, "Setup gpio\n");
cs5535_setup_gpio();
diff --git a/src/southbridge/amd/cs5536/early_setup.c b/src/southbridge/amd/cs5536/early_setup.c
index 013607b..cc427b0 100644
--- a/src/southbridge/amd/cs5536/early_setup.c
+++ b/src/southbridge/amd/cs5536/early_setup.c
@@ -42,7 +42,7 @@ static void cs5536_setup_idsel(void)
outl(0x1 << (CS5536_DEV_NUM + 10), 0);
}
-static void cs5536_usb_swapsif(void)
+static void cs5536_usb_swapsif (void)
{
msr_t msr;
@@ -260,7 +260,7 @@ static void cs5536_early_setup(void)
//printk(BIOS_DEBUG, "Setup idsel\n");
cs5536_setup_idsel();
//printk(BIOS_DEBUG, "Setup iobase\n");
- cs5536_usb_swapsif();
+ cs5536_usb_swapsif ();
cs5536_setup_iobase();
//printk(BIOS_DEBUG, "Setup gpio\n");
cs5536_setup_gpio();
diff --git a/src/southbridge/amd/pi/hudson/acpi/fch.asl b/src/southbridge/amd/pi/hudson/acpi/fch.asl
index 5a433e6..0426b00 100644
--- a/src/southbridge/amd/pi/hudson/acpi/fch.asl
+++ b/src/southbridge/amd/pi/hudson/acpi/fch.asl
@@ -165,9 +165,9 @@ Method(_INI, 0) {
Method(OSFL, 0){
- if(LNotEqual(OSVR, Ones)) {Return(OSVR)} /* OS version was already detected */
+ if (LNotEqual(OSVR, Ones)) {Return(OSVR)} /* OS version was already detected */
- if(CondRefOf(\_OSI))
+ if (CondRefOf(\_OSI))
{
Store(1, OSVR) /* Assume some form of XP */
if (\_OSI("Windows 2006")) /* Vista */
diff --git a/src/southbridge/amd/rs690/gfx.c b/src/southbridge/amd/rs690/gfx.c
index 57d6628..bcba435 100644
--- a/src/southbridge/amd/rs690/gfx.c
+++ b/src/southbridge/amd/rs690/gfx.c
@@ -461,48 +461,48 @@ void rs690_gfx_init(device_t nb_dev, device_t dev, u32 port)
/* done by enable_pci_bar3() before */
/* step 6 SBIOS compile flags */
- if (cfg->gfx_tmds) {
- /* step 6.2.2 Clock-Muxing Control */
- /* step 6.2.2.1 */
- set_nbmisc_enable_bits(nb_dev, 0x7, 1 << 16, 1 << 16);
+ if (cfg->gfx_tmds) {
+ /* step 6.2.2 Clock-Muxing Control */
+ /* step 6.2.2.1 */
+ set_nbmisc_enable_bits(nb_dev, 0x7, 1 << 16, 1 << 16);
- /* step 6.2.2.2 */
- set_nbmisc_enable_bits(nb_dev, 0x7, 1 << 8, 1 << 8);
- set_nbmisc_enable_bits(nb_dev, 0x7, 1 << 10, 1 << 10);
+ /* step 6.2.2.2 */
+ set_nbmisc_enable_bits(nb_dev, 0x7, 1 << 8, 1 << 8);
+ set_nbmisc_enable_bits(nb_dev, 0x7, 1 << 10, 1 << 10);
- /* step 6.2.2.3 */
- set_nbmisc_enable_bits(nb_dev, 0x7, 1 << 26, 1 << 26);
+ /* step 6.2.2.3 */
+ set_nbmisc_enable_bits(nb_dev, 0x7, 1 << 26, 1 << 26);
- /* step 6.2.3 Lane-Muxing Control */
- /* step 6.2.3.1 */
- set_nbmisc_enable_bits(nb_dev, 0x37, 0x3 << 8, 0x2 << 8);
+ /* step 6.2.3 Lane-Muxing Control */
+ /* step 6.2.3.1 */
+ set_nbmisc_enable_bits(nb_dev, 0x37, 0x3 << 8, 0x2 << 8);
- /* step 6.2.4 Received Data Control */
- /* step 6.2.4.1 */
- set_pcie_enable_bits(nb_dev, 0x40, 0x3 << 16, 0x2 << 16);
+ /* step 6.2.4 Received Data Control */
+ /* step 6.2.4.1 */
+ set_pcie_enable_bits(nb_dev, 0x40, 0x3 << 16, 0x2 << 16);
- /* step 6.2.4.2 */
- set_pcie_enable_bits(nb_dev, 0x40, 0x3 << 18, 0x3 << 18);
+ /* step 6.2.4.2 */
+ set_pcie_enable_bits(nb_dev, 0x40, 0x3 << 18, 0x3 << 18);
- /* step 6.2.4.3 */
- set_pcie_enable_bits(nb_dev, 0x40, 0x3 << 20, 0x0 << 20);
+ /* step 6.2.4.3 */
+ set_pcie_enable_bits(nb_dev, 0x40, 0x3 << 20, 0x0 << 20);
- /* step 6.2.4.4 */
- set_pcie_enable_bits(nb_dev, 0x40, 0x3 << 22, 0x1 << 22);
+ /* step 6.2.4.4 */
+ set_pcie_enable_bits(nb_dev, 0x40, 0x3 << 22, 0x1 << 22);
- /* step 6.2.5 PLL Power Down Control */
- /* step 6.2.5.1 */
- set_nbmisc_enable_bits(nb_dev, 0x35, 0x3 << 6, 0x0 << 6);
+ /* step 6.2.5 PLL Power Down Control */
+ /* step 6.2.5.1 */
+ set_nbmisc_enable_bits(nb_dev, 0x35, 0x3 << 6, 0x0 << 6);
- /* step 6.2.6 Driving Strength Control */
- /* step 6.2.6.1 */
- set_nbmisc_enable_bits(nb_dev, 0x34, 0x1 << 24, 0x0 << 24);
+ /* step 6.2.6 Driving Strength Control */
+ /* step 6.2.6.1 */
+ set_nbmisc_enable_bits(nb_dev, 0x34, 0x1 << 24, 0x0 << 24);
- /* step 6.2.6.2 */
- set_nbmisc_enable_bits(nb_dev, 0x35, 0x3 << 2, 0x3 << 2);
- }
+ /* step 6.2.6.2 */
+ set_nbmisc_enable_bits(nb_dev, 0x35, 0x3 << 2, 0x3 << 2);
+ }
- printk(BIOS_INFO, "rs690_gfx_init step6.\n");
+ printk(BIOS_INFO, "rs690_gfx_init step6.\n");
/* step 7 compliance state, (only need if CMOS option is enabled) */
/* the compliance state is just for test. refer to 4.2.5.2 of PCIe specification */
diff --git a/src/southbridge/amd/rs690/ht.c b/src/southbridge/amd/rs690/ht.c
index f4bdf99..bbb33ef 100644
--- a/src/southbridge/amd/rs690/ht.c
+++ b/src/southbridge/amd/rs690/ht.c
@@ -52,12 +52,12 @@ static void ht_dev_set_resources(device_t dev)
printk(BIOS_DEBUG,"%s: %s[0x1C] base = %0llx limit = %0llx\n", __func__, dev_path(dev), rbase, rend);
k8_f1 = dev_find_slot(0,PCI_DEVFN(0x18,1));
// find a not assigned resource
- for( reg = 0xb8; reg >= 0x80; reg -= 8 ) {
+ for ( reg = 0xb8; reg >= 0x80; reg -= 8 ) {
base = pci_read_config32(k8_f1,reg);
limit = pci_read_config32(k8_f1,reg+4);
- if( !(base & 3) ) break; // found a not assigned resource
+ if ( !(base & 3) ) break; // found a not assigned resource
}
- if( !(base & 3) ) {
+ if ( !(base & 3) ) {
u32 sblk;
device_t k8_f0 = dev_find_slot(0, PCI_DEVFN(0x18, 0));
/* Remember this resource has been stored. */
@@ -90,7 +90,7 @@ unsigned long acpi_fill_mcfg(unsigned long current)
device_t dev = dev_find_slot(0,PCI_DEVFN(0,0));
// we report mmconf base
res = probe_resource(dev, 0x1C);
- if( res )
+ if ( res )
mmconf_base = res->base;
current += acpi_create_mcfg_mmconfig((acpi_mcfg_mmconfig_t *)current, mmconf_base, 0x0, 0x0, 0x1f); // Fix me: should i reserve 255 busses ?
diff --git a/src/southbridge/amd/rs690/pcie.c b/src/southbridge/amd/rs690/pcie.c
index bcf4f4d..043c2ee 100644
--- a/src/southbridge/amd/rs690/pcie.c
+++ b/src/southbridge/amd/rs690/pcie.c
@@ -84,7 +84,7 @@ static void PciePowerOffGppPorts(device_t nb_dev, device_t dev, u32 port)
PCIE_GFX_COMPLIANCE))) {
}
- if (!cfg->gfx_tmds){
+ if (!cfg->gfx_tmds){
/* step 3 Power Down Control for Southbridge */
reg = nbpcie_p_read_index(dev, 0xa2);
diff --git a/src/southbridge/amd/rs780/early_setup.c b/src/southbridge/amd/rs780/early_setup.c
index da98d51..c61493d 100644
--- a/src/southbridge/amd/rs780/early_setup.c
+++ b/src/southbridge/amd/rs780/early_setup.c
@@ -335,7 +335,7 @@ static void k8_optimization(void)
wrmsr(0xC001001F, msr);
}
#else
-#define k8_optimization() do{}while(0)
+#define k8_optimization() do {} while (0)
#endif /* !CONFIG_NORTHBRIDGE_AMD_AMDFAM10 */
#if CONFIG_NORTHBRIDGE_AMD_AMDFAM10
@@ -400,7 +400,7 @@ static void fam10_optimization(void)
}
}
#else
-#define fam10_optimization() do{}while(0)
+#define fam10_optimization() do {} while (0)
#endif /* CONFIG_NORTHBRIDGE_AMD_AMDFAM10 */
/*****************************************
diff --git a/src/southbridge/amd/rs780/gfx.c b/src/southbridge/amd/rs780/gfx.c
index 6d27d56..78cb837 100644
--- a/src/southbridge/amd/rs780/gfx.c
+++ b/src/southbridge/amd/rs780/gfx.c
@@ -127,12 +127,10 @@ static u32 SetMMIO(u32 Base, u32 Limit, u8 Attribute, MMIORANGE *pMMIO)
{
int i;
MMIORANGE * TempRange;
- for(i=0; i<8; i++)
- {
- if(pMMIO[i].Attribute != Attribute && Base >= pMMIO[i].Base && Limit <= pMMIO[i].Limit)
- {
+ for (i=0; i<8; i++) {
+ if (pMMIO[i].Attribute != Attribute && Base >= pMMIO[i].Base && Limit <= pMMIO[i].Limit) {
TempRange = AllocMMIO(pMMIO);
- if(TempRange == 0) return 0x80000000;
+ if (TempRange == 0) return 0x80000000;
TempRange->Base = Limit;
TempRange->Limit = pMMIO[i].Limit;
TempRange->Attribute = pMMIO[i].Attribute;
@@ -140,7 +138,7 @@ static u32 SetMMIO(u32 Base, u32 Limit, u8 Attribute, MMIORANGE *pMMIO)
}
}
TempRange = AllocMMIO(pMMIO);
- if(TempRange == 0) return 0x80000000;
+ if (TempRange == 0) return 0x80000000;
TempRange->Base = Base;
TempRange->Limit = Limit;
TempRange->Attribute = Attribute;
@@ -150,32 +148,25 @@ static u32 SetMMIO(u32 Base, u32 Limit, u8 Attribute, MMIORANGE *pMMIO)
static u8 FinalizeMMIO(MMIORANGE *pMMIO)
{
int i, j, n = 0;
- for(i=0; i<8; i++)
- {
- if (pMMIO[i].Base == pMMIO[i].Limit)
- {
+ for (i=0; i<8; i++) {
+ if (pMMIO[i].Base == pMMIO[i].Limit) {
FreeMMIO(&pMMIO[i]);
continue;
}
- for(j=0; j<i; j++)
- {
- if (i!=j && pMMIO[i].Attribute == pMMIO[j].Attribute)
- {
- if (pMMIO[i].Base == pMMIO[j].Limit)
- {
+ for (j=0; j<i; j++) {
+ if (i!=j && pMMIO[i].Attribute == pMMIO[j].Attribute) {
+ if (pMMIO[i].Base == pMMIO[j].Limit) {
pMMIO[j].Limit = pMMIO[i].Limit;
FreeMMIO(&pMMIO[i]);
}
- if (pMMIO[i].Limit == pMMIO[j].Base)
- {
+ if (pMMIO[i].Limit == pMMIO[j].Base) {
pMMIO[j].Base = pMMIO[i].Base;
FreeMMIO(&pMMIO[i]);
}
}
}
}
- for (i=0; i<8; i++)
- {
+ for (i=0; i<8; i++) {
if (pMMIO[i].Limit != 0) n++;
}
return n;
@@ -191,29 +182,23 @@ static CIM_STATUS GetCreativeMMIO(MMIORANGE *pMMIO)
Value = pci_read_config32(dev0x14, 0x18);
BusStart = (Value >> 8) & 0xFF;
BusEnd = (Value >> 16) & 0xFF;
- for(Bus = BusStart; Bus <= BusEnd; Bus++)
- {
- for(Dev = 0; Dev <= 0x1f; Dev++)
- {
+ for (Bus = BusStart; Bus <= BusEnd; Bus++) {
+ for (Dev = 0; Dev <= 0x1f; Dev++) {
tempdev = dev_find_slot(Bus, Dev << 3);
Value = pci_read_config32(tempdev, 0);
printk(BIOS_DEBUG, "Dev ID %x\n", Value);
- if((Value & 0xffff) == 0x1102)
- {//Creative
+ if ((Value & 0xffff) == 0x1102) {//Creative
//Found Creative SB
u32 MMIOStart = 0xffffffff;
u32 MMIOLimit = 0;
- for(Reg = 0x10; Reg < 0x20; Reg+=4)
- {
+ for (Reg = 0x10; Reg < 0x20; Reg+=4) {
u32 BaseA, LimitA;
BaseA = pci_read_config32(tempdev, Reg);
Value = BaseA;
- if(!(Value & 0x01))
- {
+ if (!(Value & 0x01)) {
Value = Value & 0xffffff00;
- if(Value != 0)
- {
- if(MMIOStart > Value)
+ if (Value != 0) {
+ if (MMIOStart > Value)
MMIOStart = Value;
LimitA = 0xffffffff;
//WritePCI(PciAddress,AccWidthUint32,&LimitA);
@@ -232,16 +217,14 @@ static CIM_STATUS GetCreativeMMIO(MMIORANGE *pMMIO)
if (MMIOStart < MMIOLimit)
{
Status = SetMMIO(MMIOStart>>8, MMIOLimit>>8, 0x80, pMMIO);
- if(Status == CIM_ERROR) return Status;
+ if (Status == CIM_ERROR) return Status;
}
}
}
}
- if(Status == CIM_SUCCESS)
- {
+ if (Status == CIM_SUCCESS) {
//Lets optimize MMIO
- if(FinalizeMMIO(pMMIO) > 4)
- {
+ if (FinalizeMMIO(pMMIO) > 4) {
Status = CIM_ERROR;
}
}
@@ -256,23 +239,18 @@ static void ProgramMMIO(MMIORANGE *pMMIO, u8 LinkID, u8 Attribute)
k8_f1 = dev_find_slot(0, PCI_DEVFN(0x18, 1));
- for(i = 0; i < 8; i++)
- {
+ for (i = 0; i < 8; i++) {
int k = 0, MmioReg;
u32 Base = 0;
u32 Limit = 0;
- for(j = 0; j < 8; j++)
- {
- if (Base < pMMIO[j].Base)
- {
+ for (j = 0; j < 8; j++) {
+ if (Base < pMMIO[j].Base) {
Base = pMMIO[j].Base;
k = j;
}
}
- if(pMMIO[k].Limit != 0)
- {
- if(Attribute & MMIO_ATTRIB_NP_ONLY && pMMIO[k].Attribute == 0 )
- {
+ if (pMMIO[k].Limit != 0) {
+ if (Attribute & MMIO_ATTRIB_NP_ONLY && pMMIO[k].Attribute == 0 ) {
Base = 0;
}
else
@@ -366,8 +344,7 @@ static void internal_gfx_pci_dev_init(struct device *dev)
/* Clear vgainfo. */
bpointer = (unsigned char *) &vgainfo;
- for(i=0; i<sizeof(ATOM_INTEGRATED_SYSTEM_INFO_V2); i++)
- {
+ for (i=0; i<sizeof(ATOM_INTEGRATED_SYSTEM_INFO_V2); i++) {
*bpointer = 0;
bpointer++;
}
@@ -651,8 +628,7 @@ static void internal_gfx_pci_dev_init(struct device *dev)
/* Transfer the Table to VBIOS. */
pointer = (u32 *)&vgainfo;
- for(i=0; i<sizeof(ATOM_INTEGRATED_SYSTEM_INFO_V2); i+=4)
- {
+ for (i=0; i<sizeof(ATOM_INTEGRATED_SYSTEM_INFO_V2); i+=4) {
#if CONFIG_GFXUMA
*GpuF0MMReg = 0x80000000 + uma_memory_size - 512 + i;
#else
@@ -686,14 +662,12 @@ static void internal_gfx_pci_dev_init(struct device *dev)
/* clear MMIO and CreativeMMIO. */
bpointer = (unsigned char *)MMIO;
- for(i=0; i<sizeof(MMIO); i++)
- {
+ for (i=0; i<sizeof(MMIO); i++) {
*bpointer = 0;
bpointer++;
}
bpointer = (unsigned char *)CreativeMMIO;
- for(i=0; i<sizeof(CreativeMMIO); i++)
- {
+ for (i=0; i<sizeof(CreativeMMIO); i++) {
*bpointer = 0;
bpointer++;
}
@@ -708,20 +682,18 @@ static void internal_gfx_pci_dev_init(struct device *dev)
temp = pci_read_config32(dev0x14, 0x20);
Base32 = (temp & 0x0fff0) << 8;
Limit32 = ((temp & 0x0fff00000) + 0x100000) >> 8;
- if(Base32 < Limit32)
- {
+ if (Base32 < Limit32) {
Status = GetCreativeMMIO(&CreativeMMIO[0]);
- if(Status != CIM_ERROR)
+ if (Status != CIM_ERROR)
SetMMIO(Base32, Limit32, 0x0, &MMIO[0]);
}
/* Set MMIO for prefetchable P2P. */
- if(Status != CIM_ERROR)
- {
+ if (Status != CIM_ERROR) {
temp = pci_read_config32(dev0x14, 0x24);
Base32 = (temp & 0x0fff0) <<8;
Limit32 = ((temp & 0x0fff00000) + 0x100000) >> 8;
- if(Base32 < Limit32)
+ if (Base32 < Limit32)
SetMMIO(Base32, Limit32, 0x0, &MMIO[0]);
}
@@ -835,8 +807,7 @@ static void rs780_internal_gfx_enable(device_t dev)
device_t k8_f1 = dev_find_slot(0, PCI_DEVFN(0x18, 1));
device_t k8_f2 = dev_find_slot(0, PCI_DEVFN(0x18, 2));
device_t k8_f4 = dev_find_slot(0, PCI_DEVFN(0x18, 4));
- for (i = 0; i < 12; i++)
- {
+ for (i = 0; i < 12; i++) {
l_dword = pci_read_config32(k8_f2, 0x40 + i * 4);
nbmc_write_index(nb_dev, 0x30 + i, l_dword);
}
@@ -848,10 +819,8 @@ static void rs780_internal_gfx_enable(device_t dev)
set_nbmc_enable_bits(nb_dev, 0x3c, 0, !!(l_dword & (1<< 8))<<17);
l_dword = pci_read_config32(k8_f2, 0x90);
set_nbmc_enable_bits(nb_dev, 0x3c, 0, !!(l_dword & (1<<10))<<18);
- if (is_family10h())
- {
- for (i = 0; i < 12; i++)
- {
+ if (is_family10h()) {
+ for (i = 0; i < 12; i++) {
l_dword = pci_read_config32(k8_f2, 0x140 + i * 4);
nbmc_write_index(nb_dev, 0x3d + i, l_dword);
}
@@ -974,13 +943,11 @@ static void rs780_internal_gfx_enable(device_t dev)
/* set_nbmc_enable_bits(nb_dev, 0xac, ~(0xfffffff0), 0x0b); */
/* Init PM timing. */
- for(i=0; i<4; i++)
- {
+ for (i=0; i<4; i++) {
l_dword = nbmc_read_index(nb_dev, 0xa0+i);
nbmc_write_index(nb_dev, 0xc8+i, l_dword);
}
- for(i=0; i<4; i++)
- {
+ for (i=0; i<4; i++) {
l_dword = nbmc_read_index(nb_dev, 0xa8+i);
nbmc_write_index(nb_dev, 0xcc+i, l_dword);
}
@@ -1538,7 +1505,7 @@ void rs780_gfx_init(device_t nb_dev, device_t dev, u32 port)
printk(BIOS_DEBUG, "rs780_gfx_init step1.\n");
printk(BIOS_DEBUG, "device = %x\n", dev->path.pci.devfn >> 3);
- if((dev->path.pci.devfn >> 3) == 2) {
+ if ((dev->path.pci.devfn >> 3) == 2) {
single_port_configuration(nb_dev, dev);
} else {
set_nbmisc_enable_bits(nb_dev, 0xc, 0, 0x2 << 2); /* hide the GFX bridge. */
@@ -1565,7 +1532,7 @@ void rs780_gfx_init(device_t nb_dev, device_t dev, u32 port)
break;
case 2:
- if(is_dev3_present()){
+ if (is_dev3_present()) {
/* step 1, lane reversal (only need if CMOS option is enabled) */
if (cfg->gfx_lane_reversal) {
set_nbmisc_enable_bits(nb_dev, 0x36, 1 << 31, 1 << 31);
@@ -1583,7 +1550,7 @@ void rs780_gfx_init(device_t nb_dev, device_t dev, u32 port)
printk(BIOS_DEBUG, "device = %x\n", dev->path.pci.devfn >> 3);
dual_port_configuration(nb_dev, dev);
- }else{
+ } else {
if (cfg->gfx_lane_reversal) {
set_nbmisc_enable_bits(nb_dev, 0x36, 1 << 31, 1 << 31);
set_nbmisc_enable_bits(nb_dev, 0x33, 1 << 2, 1 << 2);
@@ -1591,9 +1558,9 @@ void rs780_gfx_init(device_t nb_dev, device_t dev, u32 port)
}
printk(BIOS_DEBUG, "rs780_gfx_init step1.\n");
- if((dev->path.pci.devfn >> 3) == 2)
+ if ((dev->path.pci.devfn >> 3) == 2)
single_port_configuration(nb_dev, dev);
- else{
+ else {
set_nbmisc_enable_bits(nb_dev, 0xc, 0, 0x2 << 2); /* hide the GFX bridge. */
printk(BIOS_DEBUG, "If dev3.., single port. Do nothing.\n");
}
diff --git a/src/southbridge/amd/rs780/rs780.h b/src/southbridge/amd/rs780/rs780.h
index ffd0e15..31bec9a 100644
--- a/src/southbridge/amd/rs780/rs780.h
+++ b/src/southbridge/amd/rs780/rs780.h
@@ -101,7 +101,7 @@ typedef struct _ATOM_INTEGRATED_SYSTEM_INFO_V2
ULONG ulDockingPinCFGInfo;
ULONG ulCPUCapInfo;
USHORT usNumberOfCyclesInPeriod; //usNumberOfCyclesInPeriod[15] = 0 - invert waveform
- // 1 - non inverted waveform
+ // 1 - non inverted waveform
USHORT usMaxNBVoltage;
USHORT usMinNBVoltage;
USHORT usBootUpNBVoltage;
diff --git a/src/southbridge/amd/sb600/early_setup.c b/src/southbridge/amd/sb600/early_setup.c
index b0e3424..cbe8b0c 100644
--- a/src/southbridge/amd/sb600/early_setup.c
+++ b/src/southbridge/amd/sb600/early_setup.c
@@ -137,7 +137,7 @@ static void enable_fid_change_on_sb(u32 sbbusn, u32 sbdn)
pmio_write(0x8b, 0x01);
pmio_write(0x8a, 0x90);
- if(get_sb600_revision() > 0x13)
+ if (get_sb600_revision() > 0x13)
pmio_write(0x88, 0x10);
else
pmio_write(0x88, 0x06);
diff --git a/src/southbridge/amd/sb600/hda.c b/src/southbridge/amd/sb600/hda.c
index b97bdec..748610c 100644
--- a/src/southbridge/amd/sb600/hda.c
+++ b/src/southbridge/amd/sb600/hda.c
@@ -175,7 +175,7 @@ static int wait_for_ready(void *base)
int timeout = 50;
- while(timeout--) {
+ while (timeout--) {
u32 dword=read32(base + HDA_ICII_REG);
if (!(dword & HDA_ICII_BUSY))
return 0;
@@ -196,7 +196,7 @@ static int wait_for_valid(void *base)
* same duration */
int timeout = 50;
- while(timeout--) {
+ while (timeout--) {
u32 dword = read32(base + HDA_ICII_REG);
if ((dword & (HDA_ICII_VALID | HDA_ICII_BUSY)) ==
HDA_ICII_VALID)
diff --git a/src/southbridge/amd/sb600/sata.c b/src/southbridge/amd/sb600/sata.c
index 6b35ba1..dbb4ec5 100644
--- a/src/southbridge/amd/sb600/sata.c
+++ b/src/southbridge/amd/sb600/sata.c
@@ -182,7 +182,7 @@ static void sata_init(struct device *dev)
printk(BIOS_SPEW, "SATA port %i status = %x\n", i, byte);
byte &= 0xF;
- if( byte == 0x1 ) {
+ if ( byte == 0x1 ) {
/* If the drive status is 0x1 then we see it but we aren't talking to it. */
/* Try to do something about it. */
printk(BIOS_SPEW, "SATA device detected but not talking. Trying lower speed.\n");
diff --git a/src/southbridge/amd/sb700/Kconfig b/src/southbridge/amd/sb700/Kconfig
index 353c2a4..9a988a9 100644
--- a/src/southbridge/amd/sb700/Kconfig
+++ b/src/southbridge/amd/sb700/Kconfig
@@ -25,16 +25,6 @@ config SOUTHBRIDGE_SPECIFIC_OPTIONS # dummy
select HAVE_HARD_RESET
select SMBUS_HAS_AUX_CHANNELS
-config SOUTHBRIDGE_AMD_SB700_33MHZ_SPI
- bool "Enable high speed SPI clock"
- default n
- help
- When set, the SPI clock will run at 33MHz instead
- of the compatibility mode 16.5MHz. Note that not
- all ROMs are capable of 33MHz operation, so you
- will need to verify this option is appropriate for
- the ROM you are using.
-
# Set for southbridge SP5100 which also uses SB700 driver
config SOUTHBRIDGE_AMD_SUBTYPE_SP5100
bool
diff --git a/src/southbridge/amd/sb700/bootblock.c b/src/southbridge/amd/sb700/bootblock.c
index dfa4102..97e749c 100644
--- a/src/southbridge/amd/sb700/bootblock.c
+++ b/src/southbridge/amd/sb700/bootblock.c
@@ -20,10 +20,6 @@
#define IO_MEM_PORT_DECODE_ENABLE_5 0x48
#define IO_MEM_PORT_DECODE_ENABLE_6 0x4a
-#define SPI_BASE_ADDRESS 0xa0
-
-#define SPI_CONTROL_1 0xc
-#define TEMPORARY_SPI_BASE_ADDRESS 0xfec10000
/*
* Enable 4MB (LPC) ROM access at 0xFFC00000 - 0xFFFFFFFF.
@@ -96,37 +92,7 @@ static void sb700_enable_rom(void)
pci_io_write_config8(dev, IO_MEM_PORT_DECODE_ENABLE_6, reg8);
}
-static void sb700_configure_rom(void)
-{
- pci_devfn_t dev;
- uint32_t dword;
-
- dev = PCI_DEV(0, 0x14, 3);
-
- if (IS_ENABLED(CONFIG_SOUTHBRIDGE_AMD_SB700_33MHZ_SPI)) {
- uint32_t prev_spi_cfg;
- volatile uint32_t *spi_mmio;
-
- /* Temporarily set up SPI access to change SPI speed */
- prev_spi_cfg = dword = pci_io_read_config32(dev, SPI_BASE_ADDRESS);
- dword &= ~(0x7ffffff << 5); /* SPI_BaseAddr */
- dword |= TEMPORARY_SPI_BASE_ADDRESS & (0x7ffffff << 5);
- dword |= (0x1 << 1); /* SpiRomEnable = 1 */
- pci_io_write_config32(dev, SPI_BASE_ADDRESS, dword);
-
- spi_mmio = (void *)(TEMPORARY_SPI_BASE_ADDRESS + SPI_CONTROL_1);
- dword = *spi_mmio;
- dword &= ~(0x3 << 12); /* NormSpeed = 0x1 */
- dword |= (0x1 << 12);
- *spi_mmio = dword;
-
- /* Restore previous SPI access */
- pci_io_write_config32(dev, SPI_BASE_ADDRESS, prev_spi_cfg);
- }
-}
-
static void bootblock_southbridge_init(void)
{
sb700_enable_rom();
- sb700_configure_rom();
}
diff --git a/src/southbridge/amd/sb700/hda.c b/src/southbridge/amd/sb700/hda.c
index c87ab6a..8497cc5 100644
--- a/src/southbridge/amd/sb700/hda.c
+++ b/src/southbridge/amd/sb700/hda.c
@@ -97,7 +97,7 @@ static int wait_for_ready(void *base)
int timeout = 50;
- while(timeout--) {
+ while (timeout--) {
u32 dword=read32(base + HDA_ICII_REG);
if (!(dword & HDA_ICII_BUSY))
return 0;
@@ -118,7 +118,7 @@ static int wait_for_valid(void *base)
* same duration */
int timeout = 50;
- while(timeout--) {
+ while (timeout--) {
u32 dword = read32(base + HDA_ICII_REG);
if ((dword & (HDA_ICII_VALID | HDA_ICII_BUSY)) ==
HDA_ICII_VALID)
diff --git a/src/southbridge/amd/sb700/reset.c b/src/southbridge/amd/sb700/reset.c
index 98429f3..d0cd4a4 100644
--- a/src/southbridge/amd/sb700/reset.c
+++ b/src/southbridge/amd/sb700/reset.c
@@ -36,7 +36,7 @@ static void set_bios_reset(void)
int i;
nodes = ((pci_read_config32(PCI_DEV(CONFIG_CBB, CONFIG_CDB, 0), 0x60) >> 4) & 7) + 1;
- for(i = 0; i < nodes; i++) {
+ for (i = 0; i < nodes; i++) {
dev = NODE_PCI(i, 0);
htic = pci_read_config32(dev, HT_INIT_CONTROL);
htic &= ~HTIC_BIOSR_Detect;
diff --git a/src/southbridge/amd/sb700/sm.c b/src/southbridge/amd/sb700/sm.c
index 6d93b17..77ec722 100644
--- a/src/southbridge/amd/sb700/sm.c
+++ b/src/southbridge/amd/sb700/sm.c
@@ -213,7 +213,7 @@ static void sm_init(device_t dev)
}
/*rpr v2.13 2.22 SMBUS PCI Config */
- byte = pci_read_config8(dev, 0xE1);
+ byte = pci_read_config8(dev, 0xE1);
if ((REV_SB700_A11 == rev) || REV_SB700_A12 == rev) {
byte |= 1 << 0;
}
@@ -222,7 +222,7 @@ static void sm_init(device_t dev)
*/
//byte |= 1 << 2 | 1 << 3 | 1 << 4;
byte |= 1 << 3 | 1 << 4;
- pci_write_config8(dev, 0xE1, byte);
+ pci_write_config8(dev, 0xE1, byte);
/* 2.5 Enabling Non-Posted Memory Write */
axindxc_reg(0x10, 1 << 9, 1 << 9);
@@ -278,7 +278,7 @@ static void sm_init(device_t dev)
u16 word;
/* rpr v2.13 4.18 Enabling Posted Pass Non-Posted Downstream */
- axindxc_reg(0x02, 1 << 9, 1 << 9);
+ axindxc_reg(0x02, 1 << 9, 1 << 9);
abcfg_reg(0x9C, 0x00007CC0, 0x00007CC0);
abcfg_reg(0x1009C, 0x00000030, 0x00000030);
abcfg_reg(0x10090, 0x00001E00, 0x00001E00);
@@ -287,19 +287,19 @@ static void sm_init(device_t dev)
abcfg_reg(0x58, 0x0000F800, 0x0000E800);
/* rpr v2.13 4.20 64 bit Non-Posted Memory Write Support */
- axindxc_reg(0x02, 1 << 10, 1 << 10);
+ axindxc_reg(0x02, 1 << 10, 1 << 10);
/* rpr v2.13 2.38 Unconditional Shutdown */
- byte = pci_read_config8(dev, 0x43);
+ byte = pci_read_config8(dev, 0x43);
byte &= ~(1 << 3);
- pci_write_config8(dev, 0x43, byte);
+ pci_write_config8(dev, 0x43, byte);
word = pci_read_config16(dev, 0x38);
word |= 1 << 12;
- pci_write_config16(dev, 0x38, word);
+ pci_write_config16(dev, 0x38, word);
byte |= 1 << 3;
- pci_write_config8(dev, 0x43, byte);
+ pci_write_config8(dev, 0x43, byte);
/* Enable southbridge MMIO decode */
dword = pci_read_config32(dev, SB_MMIO_CFG_REG);
@@ -308,12 +308,12 @@ static void sm_init(device_t dev)
dword |= 0x1;
pci_write_config32(dev, SB_MMIO_CFG_REG, dword);
}
- byte = pci_read_config8(dev, 0xAE);
- if (IS_ENABLED(CONFIG_ENABLE_APIC_EXT_ID))
- byte |= 1 << 4;
+ byte = pci_read_config8(dev, 0xAE);
+ if (IS_ENABLED(CONFIG_ENABLE_APIC_EXT_ID))
+ byte |= 1 << 4;
byte |= 1 << 5; /* ACPI_DISABLE_TIMER_IRQ_ENHANCEMENT_FOR_8254_TIMER */
byte |= 1 << 6; /* Enable arbiter between APIC and PIC interrupts */
- pci_write_config8(dev, 0xAE, byte);
+ pci_write_config8(dev, 0xAE, byte);
/* 4.11:Programming Cycle Delay for AB and BIF Clock Gating */
/* 4.12: Enabling AB and BIF Clock Gating */
diff --git a/src/southbridge/amd/sb800/hda.c b/src/southbridge/amd/sb800/hda.c
index 0b68850..2d0852e 100644
--- a/src/southbridge/amd/sb800/hda.c
+++ b/src/southbridge/amd/sb800/hda.c
@@ -99,7 +99,7 @@ static int wait_for_ready(void *base)
int timeout = 50;
- while(timeout--) {
+ while (timeout--) {
u32 dword=read32(base + HDA_ICII_REG);
if (!(dword & HDA_ICII_BUSY))
return 0;
@@ -120,7 +120,7 @@ static int wait_for_valid(void *base)
* same duration */
int timeout = 50;
- while(timeout--) {
+ while (timeout--) {
u32 dword = read32(base + HDA_ICII_REG);
if ((dword & (HDA_ICII_VALID | HDA_ICII_BUSY)) ==
HDA_ICII_VALID)
diff --git a/src/southbridge/amd/sb800/sata.c b/src/southbridge/amd/sb800/sata.c
index 56a2a52..978ccec 100644
--- a/src/southbridge/amd/sb800/sata.c
+++ b/src/southbridge/amd/sb800/sata.c
@@ -177,7 +177,7 @@ static void sata_init(struct device *dev)
byte = read8(sata_bar5 + 0x128 + 0x80 * i);
printk(BIOS_SPEW, "SATA port %i status = %x\n", i, byte);
byte &= 0xF;
- if( byte == 0x1 ) {
+ if ( byte == 0x1 ) {
/* If the drive status is 0x1 then we see it but we aren't talking to it. */
/* Try to do something about it. */
printk(BIOS_SPEW, "SATA device detected but not talking. Trying lower speed.\n");
diff --git a/src/southbridge/amd/sr5650/early_setup.c b/src/southbridge/amd/sr5650/early_setup.c
index a96b127..fce25ab 100644
--- a/src/southbridge/amd/sr5650/early_setup.c
+++ b/src/southbridge/amd/sr5650/early_setup.c
@@ -30,22 +30,22 @@
*/
static void alink_ax_indx(u32 space, u32 axindc, u32 mask, u32 val)
{
- u32 tmp;
-
- /* read axindc to tmp */
- outl(space << 30 | space << 3 | 0x30, AB_INDX);
- outl(axindc, AB_DATA);
- outl(space << 30 | space << 3 | 0x34, AB_INDX);
- tmp = inl(AB_DATA);
-
- tmp &= ~mask;
- tmp |= val;
-
- /* write tmp */
- outl(space << 30 | space << 3 | 0x30, AB_INDX);
- outl(axindc, AB_DATA);
- outl(space << 30 | space << 3 | 0x34, AB_INDX);
- outl(tmp, AB_DATA);
+ u32 tmp;
+
+ /* read axindc to tmp */
+ outl(space << 30 | space << 3 | 0x30, AB_INDX);
+ outl(axindc, AB_DATA);
+ outl(space << 30 | space << 3 | 0x34, AB_INDX);
+ tmp = inl(AB_DATA);
+
+ tmp &= ~mask;
+ tmp |= val;
+
+ /* write tmp */
+ outl(space << 30 | space << 3 | 0x30, AB_INDX);
+ outl(axindc, AB_DATA);
+ outl(space << 30 | space << 3 | 0x34, AB_INDX);
+ outl(tmp, AB_DATA);
}
@@ -327,7 +327,7 @@ void fam10_optimization(void)
/* rpr Table 5-11, 5-12 */
}
#else
-#define fam10_optimization() do{}while(0)
+#define fam10_optimization() do {} while (0)
#endif /* CONFIG_NORTHBRIDGE_AMD_AMDFAM10 || CONFIG_NORTHBRIDGE_AMD_AGESA_FAMILY10 */
/*****************************************
diff --git a/src/southbridge/amd/sr5650/sr5650.c b/src/southbridge/amd/sr5650/sr5650.c
index d28adfc..87845c6 100644
--- a/src/southbridge/amd/sr5650/sr5650.c
+++ b/src/southbridge/amd/sr5650/sr5650.c
@@ -817,8 +817,8 @@ unsigned long acpi_fill_mcfg(unsigned long current)
resource_t mmconf_base = EXT_CONF_BASE_ADDRESS;
if (IS_ENABLED(CONFIG_EXT_CONF_SUPPORT)) {
- res = sr5650_retrieve_cpu_mmio_resource();
- if (res)
+ res = sr5650_retrieve_cpu_mmio_resource();
+ if (res)
mmconf_base = res->base;
current += acpi_create_mcfg_mmconfig((acpi_mcfg_mmconfig_t *)current, mmconf_base, 0x0, 0x0, 0x1f);
diff --git a/src/southbridge/broadcom/bcm21000/pcie.c b/src/southbridge/broadcom/bcm21000/pcie.c
index ca9a225..ab52029 100644
--- a/src/southbridge/broadcom/bcm21000/pcie.c
+++ b/src/southbridge/broadcom/bcm21000/pcie.c
@@ -43,7 +43,7 @@ static void pcie_init(struct device *dev)
}
static struct pci_operations lops_pci = {
- .set_subsystem = 0,
+ .set_subsystem = 0,
};
static struct device_operations pcie_ops = {
diff --git a/src/southbridge/broadcom/bcm5780/nic.c b/src/southbridge/broadcom/bcm5780/nic.c
index be23d68..d0ff9ca 100644
--- a/src/southbridge/broadcom/bcm5780/nic.c
+++ b/src/southbridge/broadcom/bcm5780/nic.c
@@ -23,12 +23,12 @@
static void lpci_set_subsystem(device_t dev, unsigned vendor, unsigned device)
{
- pci_write_config32(dev, 0x40,
- ((device & 0xffff) << 16) | (vendor & 0xffff));
+ pci_write_config32(dev, 0x40,
+ ((device & 0xffff) << 16) | (vendor & 0xffff));
}
static struct pci_operations lops_pci = {
- .set_subsystem = lpci_set_subsystem,
+ .set_subsystem = lpci_set_subsystem,
};
static struct device_operations nic_ops = {
@@ -47,7 +47,7 @@ static const struct pci_driver nic_driver __pci_driver = {
};
static const struct pci_driver nic1_driver __pci_driver = {
- .ops = &nic_ops,
- .vendor = PCI_VENDOR_ID_BROADCOM,
- .device = PCI_DEVICE_ID_BROADCOM_BCM5780_NIC1,
+ .ops = &nic_ops,
+ .vendor = PCI_VENDOR_ID_BROADCOM,
+ .device = PCI_DEVICE_ID_BROADCOM_BCM5780_NIC1,
};
diff --git a/src/southbridge/broadcom/bcm5780/pcie.c b/src/southbridge/broadcom/bcm5780/pcie.c
index 6f8493e..2ed6102 100644
--- a/src/southbridge/broadcom/bcm5780/pcie.c
+++ b/src/southbridge/broadcom/bcm5780/pcie.c
@@ -35,17 +35,17 @@ static void pcie_init(struct device *dev)
}
static struct pci_operations lops_pci = {
- .set_subsystem = 0,
+ .set_subsystem = 0,
};
static struct device_operations pcie_ops = {
- .read_resources = pci_bus_read_resources,
- .set_resources = pci_dev_set_resources,
- .enable_resources = pci_bus_enable_resources,
- .init = pcie_init,
- .scan_bus = pci_scan_bridge,
- .reset_bus = pci_bus_reset,
- .ops_pci = &lops_pci,
+ .read_resources = pci_bus_read_resources,
+ .set_resources = pci_dev_set_resources,
+ .enable_resources = pci_bus_enable_resources,
+ .init = pcie_init,
+ .scan_bus = pci_scan_bridge,
+ .reset_bus = pci_bus_reset,
+ .ops_pci = &lops_pci,
};
diff --git a/src/southbridge/broadcom/bcm5780/pcix.c b/src/southbridge/broadcom/bcm5780/pcix.c
index 22dc771..8aa37a6 100644
--- a/src/southbridge/broadcom/bcm5780/pcix.c
+++ b/src/southbridge/broadcom/bcm5780/pcix.c
@@ -22,22 +22,22 @@
static void lpci_set_subsystem(device_t dev, unsigned vendor, unsigned device)
{
- pci_write_config32(dev, 0x40,
- ((device & 0xffff) << 16) | (vendor & 0xffff));
+ pci_write_config32(dev, 0x40,
+ ((device & 0xffff) << 16) | (vendor & 0xffff));
}
static struct pci_operations lops_pci = {
- .set_subsystem = lpci_set_subsystem,
+ .set_subsystem = lpci_set_subsystem,
};
static struct device_operations ht_ops = {
- .read_resources = pci_bus_read_resources,
- .set_resources = pci_dev_set_resources,
- .enable_resources = pci_bus_enable_resources,
- .init = 0 ,
- .scan_bus = pci_scan_bridge,
- .reset_bus = pci_bus_reset,
- .ops_pci = &lops_pci,
+ .read_resources = pci_bus_read_resources,
+ .set_resources = pci_dev_set_resources,
+ .enable_resources = pci_bus_enable_resources,
+ .init = 0 ,
+ .scan_bus = pci_scan_bridge,
+ .reset_bus = pci_bus_reset,
+ .ops_pci = &lops_pci,
};
diff --git a/src/southbridge/broadcom/bcm5785/bcm5785.c b/src/southbridge/broadcom/bcm5785/bcm5785.c
index efe38ab..d9a1268 100644
--- a/src/southbridge/broadcom/bcm5785/bcm5785.c
+++ b/src/southbridge/broadcom/bcm5785/bcm5785.c
@@ -36,17 +36,17 @@ void bcm5785_enable(device_t dev)
sb_pci_main_dev = dev_find_slot(bus_dev->bus->secondary, devfn);
// index = ((dev->path.pci.devfn & ~7) >> 3) + 8;
} else if ((bus_dev->vendor == PCI_VENDOR_ID_SERVERWORKS) &&
- (bus_dev->device == 0x0104)) // device under PCI Bridge( under PCI-X )
- {
- unsigned devfn;
- devfn = bus_dev->bus->dev->path.pci.devfn + (1 << 3);
- sb_pci_main_dev = dev_find_slot(bus_dev->bus->dev->bus->secondary, devfn);
+ (bus_dev->device == 0x0104)) // device under PCI Bridge( under PCI-X )
+ {
+ unsigned devfn;
+ devfn = bus_dev->bus->dev->path.pci.devfn + (1 << 3);
+ sb_pci_main_dev = dev_find_slot(bus_dev->bus->dev->bus->secondary, devfn);
// index = ((dev->path.pci.devfn & ~7) >> 3) + 8;
- }
+ }
else { // same bus
unsigned devfn;
devfn = (dev->path.pci.devfn) & ~7;
- if (dev->vendor == PCI_VENDOR_ID_SERVERWORKS ) {
+ if ( dev->vendor == PCI_VENDOR_ID_SERVERWORKS ) {
if (dev->device == 0x0036) //PCI-X Bridge
{ devfn += (1<<3); }
else if (dev->device == 0x0223) // USB
diff --git a/src/southbridge/broadcom/bcm5785/chip.h b/src/southbridge/broadcom/bcm5785/chip.h
index ac39fd1..2c65734 100644
--- a/src/southbridge/broadcom/bcm5785/chip.h
+++ b/src/southbridge/broadcom/bcm5785/chip.h
@@ -19,10 +19,10 @@
struct southbridge_broadcom_bcm5785_config
{
- unsigned int ide0_enable : 1;
- unsigned int ide1_enable : 1;
- unsigned int sata0_enable : 1;
- unsigned int sata1_enable : 1;
+ unsigned int ide0_enable : 1;
+ unsigned int ide1_enable : 1;
+ unsigned int sata0_enable : 1;
+ unsigned int sata1_enable : 1;
};
#endif /* BCM5785_CHIP_H */
diff --git a/src/southbridge/broadcom/bcm5785/early_setup.c b/src/southbridge/broadcom/bcm5785/early_setup.c
index 3ddc9ca..8aba58c 100644
--- a/src/southbridge/broadcom/bcm5785/early_setup.c
+++ b/src/southbridge/broadcom/bcm5785/early_setup.c
@@ -19,62 +19,62 @@
static void bcm5785_enable_lpc(void)
{
- uint8_t byte;
- device_t dev;
-
- dev = pci_locate_device(PCI_ID(0x1166, 0x0234), 0);
-
- /* LPC Control 0 */
- byte = pci_read_config8(dev, 0x44);
- /* Serial 0 */
- byte |= (1<<6);
- pci_write_config8(dev, 0x44, byte);
-
- /* LPC Control 4 */
- byte = pci_read_config8(dev, 0x48);
- /* superio port 0x2e/4e enable */
- byte |=(1<<1)|(1<<0);
- pci_write_config8(dev, 0x48, byte);
+ uint8_t byte;
+ device_t dev;
+
+ dev = pci_locate_device(PCI_ID(0x1166, 0x0234), 0);
+
+ /* LPC Control 0 */
+ byte = pci_read_config8(dev, 0x44);
+ /* Serial 0 */
+ byte |= (1<<6);
+ pci_write_config8(dev, 0x44, byte);
+
+ /* LPC Control 4 */
+ byte = pci_read_config8(dev, 0x48);
+ /* superio port 0x2e/4e enable */
+ byte |=(1<<1)|(1<<0);
+ pci_write_config8(dev, 0x48, byte);
}
static void bcm5785_enable_wdt_port_cf9(void)
{
- device_t dev;
- uint32_t dword;
- uint32_t dword_old;
+ device_t dev;
+ uint32_t dword;
+ uint32_t dword_old;
- dev = pci_locate_device(PCI_ID(0x1166, 0x0205), 0);
+ dev = pci_locate_device(PCI_ID(0x1166, 0x0205), 0);
- dword_old = pci_read_config32(dev, 0x4c);
- dword = dword_old | (1<<4); //enable Timer Func
- if (dword != dword_old ) {
- pci_write_config32(dev, 0x4c, dword);
- }
+ dword_old = pci_read_config32(dev, 0x4c);
+ dword = dword_old | (1<<4); //enable Timer Func
+ if (dword != dword_old ) {
+ pci_write_config32(dev, 0x4c, dword);
+ }
- dword_old = pci_read_config32(dev, 0x6c);
- dword = dword_old | (1<<9); //unhide Timer Func in pci space
- if (dword != dword_old ) {
- pci_write_config32(dev, 0x6c, dword);
- }
+ dword_old = pci_read_config32(dev, 0x6c);
+ dword = dword_old | (1<<9); //unhide Timer Func in pci space
+ if (dword != dword_old ) {
+ pci_write_config32(dev, 0x6c, dword);
+ }
- dev = pci_locate_device(PCI_ID(0x1166, 0x0238), 0);
+ dev = pci_locate_device(PCI_ID(0x1166, 0x0238), 0);
- /* enable cf9 */
- pci_write_config8(dev, 0x40, (1<<2));
+ /* enable cf9 */
+ pci_write_config8(dev, 0x40, (1<<2));
}
unsigned get_sbdn(unsigned bus)
{
- device_t dev;
+ device_t dev;
- /* Find the device.
- * There can only be one bcm5785 on a hypertransport chain/bus.
- */
- dev = pci_locate_device_on_bus(
- PCI_ID(0x1166, 0x0036),
- bus);
+ /* Find the device.
+ * There can only be one bcm5785 on a hypertransport chain/bus.
+ */
+ dev = pci_locate_device_on_bus(
+ PCI_ID(0x1166, 0x0036),
+ bus);
- return (dev>>15) & 0x1f;
+ return (dev>>15) & 0x1f;
}
@@ -89,8 +89,8 @@ void enable_fid_change_on_sb(unsigned sbbusn, unsigned sbdn)
// set port to 0x2060
outb(0x67, 0xcd6);
outb(0x60, 0xcd7);
- outb(0x68, 0xcd6);
- outb(0x20, 0xcd7);
+ outb(0x68, 0xcd6);
+ outb(0x20, 0xcd7);
outb(0x69, 0xcd6);
outb(7, 0xcd7);
@@ -107,113 +107,113 @@ void ldtstop_sb(void)
void hard_reset(void)
{
- bcm5785_enable_wdt_port_cf9();
+ bcm5785_enable_wdt_port_cf9();
- set_bios_reset();
+ set_bios_reset();
- /* full reset */
- outb(0x0a, 0x0cf9);
- outb(0x0e, 0x0cf9);
+ /* full reset */
+ outb(0x0a, 0x0cf9);
+ outb(0x0e, 0x0cf9);
}
void soft_reset(void)
{
- bcm5785_enable_wdt_port_cf9();
+ bcm5785_enable_wdt_port_cf9();
- set_bios_reset();
+ set_bios_reset();
#if 1
- /* link reset */
-// outb(0x02, 0x0cf9);
- outb(0x06, 0x0cf9);
+ /* link reset */
+// outb(0x02, 0x0cf9);
+ outb(0x06, 0x0cf9);
#endif
}
static void bcm5785_enable_msg(void)
{
- device_t dev;
- uint32_t dword;
- uint32_t dword_old;
- uint8_t byte;
-
- dev = pci_locate_device(PCI_ID(0x1166, 0x0205), 0);
-
- byte = pci_read_config8(dev, 0x42);
- byte = (1<<1); //enable a20
- pci_write_config8(dev, 0x42, byte);
-
- dword_old = pci_read_config32(dev, 0x6c);
- // bit 5: enable A20 Message
- // bit 4: enable interrupt messages
- // bit 3: enable reset init message
- // bit 2: enable keyboard init message
- // bit 1: enable upsteam messages
- // bit 0: enable shutdowm message to init generation
- dword = dword_old | (1<<5) | (1<<3) | (1<<2) | (1<<1) | (1<<0); // bit 1 and bit 4 must be set, otherwise interrupt msg will not be delivered to the processor
- if (dword != dword_old ) {
- pci_write_config32(dev, 0x6c, dword);
- }
+ device_t dev;
+ uint32_t dword;
+ uint32_t dword_old;
+ uint8_t byte;
+
+ dev = pci_locate_device(PCI_ID(0x1166, 0x0205), 0);
+
+ byte = pci_read_config8(dev, 0x42);
+ byte = (1<<1); //enable a20
+ pci_write_config8(dev, 0x42, byte);
+
+ dword_old = pci_read_config32(dev, 0x6c);
+ // bit 5: enable A20 Message
+ // bit 4: enable interrupt messages
+ // bit 3: enable reset init message
+ // bit 2: enable keyboard init message
+ // bit 1: enable upsteam messages
+ // bit 0: enable shutdowm message to init generation
+ dword = dword_old | (1<<5) | (1<<3) | (1<<2) | (1<<1) | (1<<0); // bit 1 and bit 4 must be set, otherwise interrupt msg will not be delivered to the processor
+ if (dword != dword_old ) {
+ pci_write_config32(dev, 0x6c, dword);
+ }
}
static void bcm5785_early_setup(void)
{
- uint8_t byte;
- uint32_t dword;
- device_t dev;
+ uint8_t byte;
+ uint32_t dword;
+ device_t dev;
//F0
- // enable device on bcm5785 at first
- dev = pci_locate_device(PCI_ID(0x1166, 0x0205), 0);
- dword = pci_read_config32(dev, 0x64);
- dword |= (1<<15) | (1<<11) | (1<<3); // ioapci enable
- dword |= (1<<8); // USB enable
- dword |= /* (1<<27)|*/(1<<14); // IDE enable
- pci_write_config32(dev, 0x64, dword);
-
- byte = pci_read_config8(dev, 0x84);
- byte |= (1<<0); // SATA enable
- pci_write_config8(dev, 0x84, byte);
+ // enable device on bcm5785 at first
+ dev = pci_locate_device(PCI_ID(0x1166, 0x0205), 0);
+ dword = pci_read_config32(dev, 0x64);
+ dword |= (1<<15) | (1<<11) | (1<<3); // ioapci enable
+ dword |= (1<<8); // USB enable
+ dword |= /* (1<<27)|*/(1<<14); // IDE enable
+ pci_write_config32(dev, 0x64, dword);
+
+ byte = pci_read_config8(dev, 0x84);
+ byte |= (1<<0); // SATA enable
+ pci_write_config8(dev, 0x84, byte);
// WDT and cf9 for later in ramstage to call hard_reset
- bcm5785_enable_wdt_port_cf9();
+ bcm5785_enable_wdt_port_cf9();
- bcm5785_enable_msg();
+ bcm5785_enable_msg();
// IDE related
//F0
- byte = pci_read_config8(dev, 0x4e);
- byte |= (1<<4); //enable IDE ext regs
- pci_write_config8(dev, 0x4e, byte);
+ byte = pci_read_config8(dev, 0x4e);
+ byte |= (1<<4); //enable IDE ext regs
+ pci_write_config8(dev, 0x4e, byte);
//F1
- dev = pci_locate_device(PCI_ID(0x1166, 0x0214), 0);
- byte = pci_read_config8(dev, 0x48);
- byte &= ~1; // disable pri channel
- pci_write_config8(dev, 0x48, byte);
- pci_write_config8(dev, 0xb0, 0x01);
- pci_write_config8(dev, 0xb2, 0x02);
- byte = pci_read_config8(dev, 0x06);
- byte |= (1<<4); // so b0, b2 can not be changed from now
- pci_write_config8(dev, 0x06, byte);
- byte = pci_read_config8(dev, 0x49);
- byte |= 1; // enable second channel
- pci_write_config8(dev, 0x49, byte);
+ dev = pci_locate_device(PCI_ID(0x1166, 0x0214), 0);
+ byte = pci_read_config8(dev, 0x48);
+ byte &= ~1; // disable pri channel
+ pci_write_config8(dev, 0x48, byte);
+ pci_write_config8(dev, 0xb0, 0x01);
+ pci_write_config8(dev, 0xb2, 0x02);
+ byte = pci_read_config8(dev, 0x06);
+ byte |= (1<<4); // so b0, b2 can not be changed from now
+ pci_write_config8(dev, 0x06, byte);
+ byte = pci_read_config8(dev, 0x49);
+ byte |= 1; // enable second channel
+ pci_write_config8(dev, 0x49, byte);
//F2
- dev = pci_locate_device(PCI_ID(0x1166, 0x0234), 0);
+ dev = pci_locate_device(PCI_ID(0x1166, 0x0234), 0);
- byte = pci_read_config8(dev, 0x40);
- byte |= (1<<3)|(1<<2); // LPC Retry, LPC to PCI DMA enable
- pci_write_config8(dev, 0x40, byte);
+ byte = pci_read_config8(dev, 0x40);
+ byte |= (1<<3)|(1<<2); // LPC Retry, LPC to PCI DMA enable
+ pci_write_config8(dev, 0x40, byte);
- pci_write_config32(dev, 0x60, 0x0000ffff); // LPC Memory hole start and end
+ pci_write_config32(dev, 0x60, 0x0000ffff); // LPC Memory hole start and end
// USB related
- pci_write_config8(dev, 0x90, 0x40);
- pci_write_config8(dev, 0x92, 0x06);
- pci_write_config8(dev, 0x9c, 0x7c); //PHY timinig register
- pci_write_config8(dev, 0xa4, 0x02); //mask reg - low/full speed func
- pci_write_config8(dev, 0xa5, 0x02); //mask reg - low/full speed func
- pci_write_config8(dev, 0xa6, 0x00); //mask reg - high speed func
- pci_write_config8(dev, 0xb4, 0x40);
+ pci_write_config8(dev, 0x90, 0x40);
+ pci_write_config8(dev, 0x92, 0x06);
+ pci_write_config8(dev, 0x9c, 0x7c); //PHY timinig register
+ pci_write_config8(dev, 0xa4, 0x02); //mask reg - low/full speed func
+ pci_write_config8(dev, 0xa5, 0x02); //mask reg - low/full speed func
+ pci_write_config8(dev, 0xa6, 0x00); //mask reg - high speed func
+ pci_write_config8(dev, 0xb4, 0x40);
}
diff --git a/src/southbridge/broadcom/bcm5785/early_smbus.c b/src/southbridge/broadcom/bcm5785/early_smbus.c
index 9d3d3e8..f37aed9 100644
--- a/src/southbridge/broadcom/bcm5785/early_smbus.c
+++ b/src/southbridge/broadcom/bcm5785/early_smbus.c
@@ -38,20 +38,20 @@ static void enable_smbus(void)
static inline int smbus_recv_byte(unsigned device)
{
- return do_smbus_recv_byte(SMBUS_IO_BASE, device);
+ return do_smbus_recv_byte(SMBUS_IO_BASE, device);
}
static inline int smbus_send_byte(unsigned device, unsigned char val)
{
- return do_smbus_send_byte(SMBUS_IO_BASE, device, val);
+ return do_smbus_send_byte(SMBUS_IO_BASE, device, val);
}
static inline int smbus_read_byte(unsigned device, unsigned address)
{
- return do_smbus_read_byte(SMBUS_IO_BASE, device, address);
+ return do_smbus_read_byte(SMBUS_IO_BASE, device, address);
}
static inline int smbus_write_byte(unsigned device, unsigned address, unsigned char val)
{
- return do_smbus_write_byte(SMBUS_IO_BASE, device, address, val);
+ return do_smbus_write_byte(SMBUS_IO_BASE, device, address, val);
}
diff --git a/src/southbridge/broadcom/bcm5785/ide.c b/src/southbridge/broadcom/bcm5785/ide.c
index 868586c..a6bb204 100644
--- a/src/southbridge/broadcom/bcm5785/ide.c
+++ b/src/southbridge/broadcom/bcm5785/ide.c
@@ -23,13 +23,13 @@
static void bcm5785_ide_read_resources(device_t dev)
{
- /* Get the normal pci resources of this device */
- pci_dev_read_resources(dev);
+ /* Get the normal pci resources of this device */
+ pci_dev_read_resources(dev);
- /* BAR */
- pci_get_resource(dev, 0x64);
+ /* BAR */
+ pci_get_resource(dev, 0x64);
- compact_resources(dev);
+ compact_resources(dev);
}
static void ide_init(struct device *dev)
@@ -38,12 +38,12 @@ static void ide_init(struct device *dev)
static void lpci_set_subsystem(device_t dev, unsigned vendor, unsigned device)
{
- pci_write_config32(dev, 0x40,
- ((device & 0xffff) << 16) | (vendor & 0xffff));
+ pci_write_config32(dev, 0x40,
+ ((device & 0xffff) << 16) | (vendor & 0xffff));
}
static struct pci_operations lops_pci = {
- .set_subsystem = lpci_set_subsystem,
+ .set_subsystem = lpci_set_subsystem,
};
static struct device_operations ide_ops = {
diff --git a/src/southbridge/broadcom/bcm5785/lpc.c b/src/southbridge/broadcom/bcm5785/lpc.c
index f0d7416..59ba798 100644
--- a/src/southbridge/broadcom/bcm5785/lpc.c
+++ b/src/southbridge/broadcom/bcm5785/lpc.c
@@ -74,15 +74,15 @@ static void bcm5785_lpc_enable_childrens_resources(device_t dev)
reg = pci_read_config8(dev, 0x44);
for (link = dev->link_list; link; link = link->next) {
- device_t child;
- for (child = link->children; child; child = child->sibling) {
- if(child->enabled && (child->path.type == DEVICE_PATH_PNP)) {
+ device_t child;
+ for (child = link->children; child; child = child->sibling) {
+ if (child->enabled && (child->path.type == DEVICE_PATH_PNP)) {
struct resource *res;
- for(res = child->resource_list; res; res = res->next) {
- unsigned long base, end; // don't need long long
- if(!(res->flags & IORESOURCE_IO)) continue;
- base = res->base;
- end = resource_end(res);
+ for (res = child->resource_list; res; res = res->next) {
+ unsigned long base, end; // don't need long long
+ if (!(res->flags & IORESOURCE_IO)) continue;
+ base = res->base;
+ end = resource_end(res);
printk(BIOS_DEBUG, "bcm5785lpc decode:%s, base=0x%08lx, end=0x%08lx\n",dev_path(child),base, end);
switch(base) {
case 0x60: //KBC
@@ -103,8 +103,8 @@ static void bcm5785_lpc_enable_childrens_resources(device_t dev)
}
}
}
- }
- }
+ }
+ }
pci_write_config32(dev, 0x44, reg);
@@ -112,18 +112,18 @@ static void bcm5785_lpc_enable_childrens_resources(device_t dev)
static void bcm5785_lpc_enable_resources(device_t dev)
{
- pci_dev_enable_resources(dev);
- bcm5785_lpc_enable_childrens_resources(dev);
+ pci_dev_enable_resources(dev);
+ bcm5785_lpc_enable_childrens_resources(dev);
}
static void lpci_set_subsystem(device_t dev, unsigned vendor, unsigned device)
{
- pci_write_config32(dev, 0x40,
- ((device & 0xffff) << 16) | (vendor & 0xffff));
+ pci_write_config32(dev, 0x40,
+ ((device & 0xffff) << 16) | (vendor & 0xffff));
}
static struct pci_operations lops_pci = {
- .set_subsystem = lpci_set_subsystem,
+ .set_subsystem = lpci_set_subsystem,
};
static struct device_operations lpc_ops = {
diff --git a/src/southbridge/broadcom/bcm5785/reset.c b/src/southbridge/broadcom/bcm5785/reset.c
index 7064b19..8140e01 100644
--- a/src/southbridge/broadcom/bcm5785/reset.c
+++ b/src/southbridge/broadcom/bcm5785/reset.c
@@ -18,24 +18,24 @@
#include <reset.h>
#define PCI_DEV(BUS, DEV, FN) ( \
- (((BUS) & 0xFFF) << 20) | \
- (((DEV) & 0x1F) << 15) | \
- (((FN) & 0x7) << 12))
+ (((BUS) & 0xFFF) << 20) | \
+ (((DEV) & 0x1F) << 15) | \
+ (((FN) & 0x7) << 12))
static void pci_write_config32(pci_devfn_t dev, unsigned where, unsigned value)
{
- unsigned addr;
- addr = (dev>>4) | where;
- outl(0x80000000 | (addr & ~3), 0xCF8);
- outl(value, 0xCFC);
+ unsigned addr;
+ addr = (dev>>4) | where;
+ outl(0x80000000 | (addr & ~3), 0xCF8);
+ outl(value, 0xCFC);
}
static unsigned pci_read_config32(pci_devfn_t dev, unsigned where)
{
- unsigned addr;
- addr = (dev>>4) | where;
- outl(0x80000000 | (addr & ~3), 0xCF8);
- return inl(0xCFC);
+ unsigned addr;
+ addr = (dev>>4) | where;
+ outl(0x80000000 | (addr & ~3), 0xCF8);
+ return inl(0xCFC);
}
#include "../../../northbridge/amd/amdk8/reset_test.c"
@@ -43,7 +43,7 @@ static unsigned pci_read_config32(pci_devfn_t dev, unsigned where)
void hard_reset(void)
{
set_bios_reset();
- /* Try rebooting through port 0xcf9 */
+ /* Try rebooting through port 0xcf9 */
/* Actually it is not a real hard_reset --- it only reset coherent link table, but not reset link freq and width */
outb((0 <<3)|(0<<2)|(1<<1), 0xcf9);
outb((0 <<3)|(1<<2)|(1<<1), 0xcf9);
diff --git a/src/southbridge/broadcom/bcm5785/sata.c b/src/southbridge/broadcom/bcm5785/sata.c
index 75f2d46..02331d9 100644
--- a/src/southbridge/broadcom/bcm5785/sata.c
+++ b/src/southbridge/broadcom/bcm5785/sata.c
@@ -28,41 +28,41 @@ static void sata_init(struct device *dev)
uint8_t byte;
u8 *mmio;
- struct resource *res;
- u8 *mmio_base;
+ struct resource *res;
+ u8 *mmio_base;
int i;
- if(!(dev->path.pci.devfn & 7)) { // only set it in Func0
+ if (!(dev->path.pci.devfn & 7)) { // only set it in Func0
byte = pci_read_config8(dev, 0x78);
byte |= (1<<7);
- pci_write_config8(dev, 0x78, byte);
+ pci_write_config8(dev, 0x78, byte);
res = find_resource(dev, 0x24);
- mmio_base = res2mmio(res, 0, 3);
+ mmio_base = res2mmio(res, 0, 3);
write32(mmio_base + 0x10f0, 0x40000001);
write32(mmio_base + 0x8c, 0x00ff2007);
- mdelay( 10 );
+ mdelay( 10 );
write32(mmio_base + 0x8c, 0x78592009);
- mdelay( 10 );
+ mdelay( 10 );
write32(mmio_base + 0x8c, 0x00082004);
- mdelay( 10 );
+ mdelay( 10 );
write32(mmio_base + 0x8c, 0x00002004);
- mdelay( 10 );
+ mdelay( 10 );
//init PHY
printk(BIOS_DEBUG, "init PHY...\n");
- for(i=0; i<4; i++) {
+ for (i=0; i<4; i++) {
mmio = (u8 *)(uintptr_t)(res->base + 0x100 * i);
byte = read8(mmio + 0x40);
printk(BIOS_DEBUG, "port %d PHY status = %02x\n", i, byte);
- if(byte & 0x4) {// bit 2 is set
+ if (byte & 0x4) {// bit 2 is set
byte = read8(mmio+0x48);
write8(mmio + 0x48, byte | 1);
write8(mmio + 0x48, byte & (~1));
- byte = read8(mmio + 0x40);
- printk(BIOS_DEBUG, "after reset port %d PHY status = %02x\n", i, byte);
+ byte = read8(mmio + 0x40);
+ printk(BIOS_DEBUG, "after reset port %d PHY status = %02x\n", i, byte);
}
}
}
@@ -70,12 +70,12 @@ static void sata_init(struct device *dev)
static void lpci_set_subsystem(device_t dev, unsigned vendor, unsigned device)
{
- pci_write_config32(dev, 0x40,
- ((device & 0xffff) << 16) | (vendor & 0xffff));
+ pci_write_config32(dev, 0x40,
+ ((device & 0xffff) << 16) | (vendor & 0xffff));
}
static struct pci_operations lops_pci = {
- .set_subsystem = lpci_set_subsystem,
+ .set_subsystem = lpci_set_subsystem,
};
static struct device_operations sata_ops = {
diff --git a/src/southbridge/broadcom/bcm5785/sb_pci_main.c b/src/southbridge/broadcom/bcm5785/sb_pci_main.c
index 1898ca6..ab0cd05 100644
--- a/src/southbridge/broadcom/bcm5785/sb_pci_main.c
+++ b/src/southbridge/broadcom/bcm5785/sb_pci_main.c
@@ -45,7 +45,7 @@ static void sb_init(device_t dev)
} else {
byte |= ( 1 << 7); // Can not mask NMI from PCI-E and NMI_NOW
}
- if( byte != byte_old) {
+ if ( byte != byte_old) {
outb(byte, 0x70);
}
@@ -63,101 +63,101 @@ static void bcm5785_sb_read_resources(device_t dev)
compact_resources(dev);
- /* Add an extra subtractive resource for both memory and I/O */
- res = new_resource(dev, IOINDEX_SUBTRACTIVE(0, 0));
- res->flags = IORESOURCE_IO | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED;
+ /* Add an extra subtractive resource for both memory and I/O */
+ res = new_resource(dev, IOINDEX_SUBTRACTIVE(0, 0));
+ res->flags = IORESOURCE_IO | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED;
- res = new_resource(dev, IOINDEX_SUBTRACTIVE(1, 0));
- res->flags = IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED;
+ res = new_resource(dev, IOINDEX_SUBTRACTIVE(1, 0));
+ res->flags = IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED;
}
static int lsmbus_recv_byte(device_t dev)
{
- unsigned device;
- struct resource *res;
+ unsigned device;
+ struct resource *res;
struct bus *pbus;
- device = dev->path.i2c.device;
+ device = dev->path.i2c.device;
pbus = get_pbus_smbus(dev);
- res = find_resource(pbus->dev, 0x90);
+ res = find_resource(pbus->dev, 0x90);
- return do_smbus_recv_byte(res->base, device);
+ return do_smbus_recv_byte(res->base, device);
}
static int lsmbus_send_byte(device_t dev, uint8_t val)
{
- unsigned device;
- struct resource *res;
- struct bus *pbus;
+ unsigned device;
+ struct resource *res;
+ struct bus *pbus;
- device = dev->path.i2c.device;
- pbus = get_pbus_smbus(dev);
+ device = dev->path.i2c.device;
+ pbus = get_pbus_smbus(dev);
- res = find_resource(pbus->dev, 0x90);
+ res = find_resource(pbus->dev, 0x90);
- return do_smbus_send_byte(res->base, device, val);
+ return do_smbus_send_byte(res->base, device, val);
}
static int lsmbus_read_byte(device_t dev, uint8_t address)
{
- unsigned device;
- struct resource *res;
- struct bus *pbus;
+ unsigned device;
+ struct resource *res;
+ struct bus *pbus;
- device = dev->path.i2c.device;
- pbus = get_pbus_smbus(dev);
+ device = dev->path.i2c.device;
+ pbus = get_pbus_smbus(dev);
- res = find_resource(pbus->dev, 0x90);
+ res = find_resource(pbus->dev, 0x90);
- return do_smbus_read_byte(res->base, device, address);
+ return do_smbus_read_byte(res->base, device, address);
}
static int lsmbus_write_byte(device_t dev, uint8_t address, uint8_t val)
{
- unsigned device;
- struct resource *res;
- struct bus *pbus;
+ unsigned device;
+ struct resource *res;
+ struct bus *pbus;
- device = dev->path.i2c.device;
- pbus = get_pbus_smbus(dev);
+ device = dev->path.i2c.device;
+ pbus = get_pbus_smbus(dev);
- res = find_resource(pbus->dev, 0x90);
+ res = find_resource(pbus->dev, 0x90);
- return do_smbus_write_byte(res->base, device, address, val);
+ return do_smbus_write_byte(res->base, device, address, val);
}
static struct smbus_bus_operations lops_smbus_bus = {
- .recv_byte = lsmbus_recv_byte,
- .send_byte = lsmbus_send_byte,
- .read_byte = lsmbus_read_byte,
- .write_byte = lsmbus_write_byte,
+ .recv_byte = lsmbus_recv_byte,
+ .send_byte = lsmbus_send_byte,
+ .read_byte = lsmbus_read_byte,
+ .write_byte = lsmbus_write_byte,
};
static void lpci_set_subsystem(device_t dev, unsigned vendor, unsigned device)
{
- pci_write_config32(dev, 0x2c,
- ((device & 0xffff) << 16) | (vendor & 0xffff));
+ pci_write_config32(dev, 0x2c,
+ ((device & 0xffff) << 16) | (vendor & 0xffff));
}
static struct pci_operations lops_pci = {
- .set_subsystem = lpci_set_subsystem,
+ .set_subsystem = lpci_set_subsystem,
};
static struct device_operations sb_ops = {
- .read_resources = bcm5785_sb_read_resources,
- .set_resources = pci_dev_set_resources,
- .enable_resources = pci_dev_enable_resources,
- .init = sb_init,
- .scan_bus = scan_smbus,
+ .read_resources = bcm5785_sb_read_resources,
+ .set_resources = pci_dev_set_resources,
+ .enable_resources = pci_dev_enable_resources,
+ .init = sb_init,
+ .scan_bus = scan_smbus,
// .enable = bcm5785_enable,
- .ops_pci = &lops_pci,
- .ops_smbus_bus = &lops_smbus_bus,
+ .ops_pci = &lops_pci,
+ .ops_smbus_bus = &lops_smbus_bus,
};
static const struct pci_driver sb_driver __pci_driver = {
- .ops = &sb_ops,
- .vendor = PCI_VENDOR_ID_SERVERWORKS,
- .device = PCI_DEVICE_ID_SERVERWORKS_BCM5785_SB_PCI_MAIN,
+ .ops = &sb_ops,
+ .vendor = PCI_VENDOR_ID_SERVERWORKS,
+ .device = PCI_DEVICE_ID_SERVERWORKS_BCM5785_SB_PCI_MAIN,
};
diff --git a/src/southbridge/broadcom/bcm5785/smbus.h b/src/southbridge/broadcom/bcm5785/smbus.h
index bb43269..76c593b 100644
--- a/src/southbridge/broadcom/bcm5785/smbus.h
+++ b/src/southbridge/broadcom/bcm5785/smbus.h
@@ -53,7 +53,7 @@ static int smbus_wait_until_ready(unsigned smbus_io_base)
return 0;
}
outb(val, smbus_io_base + SMBHSTSTAT);
- } while(--loops);
+ } while (--loops);
return -2; // time out
}
@@ -73,7 +73,7 @@ static int smbus_wait_until_done(unsigned smbus_io_base)
outb(val, smbus_io_base + SMBHSTSTAT); // clear status
return 0; //
}
- } while(--loops);
+ } while (--loops);
return -3; // timeout
}
@@ -81,54 +81,54 @@ static int do_smbus_recv_byte(unsigned smbus_io_base, unsigned device)
{
uint8_t byte;
- if (smbus_wait_until_ready(smbus_io_base) < 0) {
- return -2; // not ready
- }
+ if (smbus_wait_until_ready(smbus_io_base) < 0) {
+ return -2; // not ready
+ }
- /* set the device I'm talking too */
- outb(((device & 0x7f) << 1)|1 , smbus_io_base + SMBHSTADDR);
+ /* set the device I'm talking too */
+ outb(((device & 0x7f) << 1)|1 , smbus_io_base + SMBHSTADDR);
- byte = inb(smbus_io_base + SMBHSTCTRL);
- byte &= 0xe3; // Clear [4:2]
- byte |= (1<<2) | (1<<6); // Byte data read/write command, start the command
- outb(byte, smbus_io_base + SMBHSTCTRL);
+ byte = inb(smbus_io_base + SMBHSTCTRL);
+ byte &= 0xe3; // Clear [4:2]
+ byte |= (1<<2) | (1<<6); // Byte data read/write command, start the command
+ outb(byte, smbus_io_base + SMBHSTCTRL);
- /* poll for transaction completion */
- if (smbus_wait_until_done(smbus_io_base) < 0) {
- return -3; // timeout or error
- }
+ /* poll for transaction completion */
+ if (smbus_wait_until_done(smbus_io_base) < 0) {
+ return -3; // timeout or error
+ }
- /* read results of transaction */
- byte = inb(smbus_io_base + SMBHSTCMD);
+ /* read results of transaction */
+ byte = inb(smbus_io_base + SMBHSTCMD);
return byte;
}
static int do_smbus_send_byte(unsigned smbus_io_base, unsigned device, unsigned char val)
{
- uint8_t byte;
+ uint8_t byte;
- if (smbus_wait_until_ready(smbus_io_base) < 0) {
- return -2; // not ready
- }
+ if (smbus_wait_until_ready(smbus_io_base) < 0) {
+ return -2; // not ready
+ }
- /* set the command... */
- outb(val, smbus_io_base + SMBHSTCMD);
+ /* set the command... */
+ outb(val, smbus_io_base + SMBHSTCMD);
- /* set the device I'm talking too */
- outb(((device & 0x7f) << 1)|0 , smbus_io_base + SMBHSTADDR);
+ /* set the device I'm talking too */
+ outb(((device & 0x7f) << 1)|0 , smbus_io_base + SMBHSTADDR);
- byte = inb(smbus_io_base + SMBHSTCTRL);
- byte &= 0xe3; // Clear [4:2]
- byte |= (1<<2) | (1<<6); // Byte data read/write command, start the command
- outb(byte, smbus_io_base + SMBHSTCTRL);
+ byte = inb(smbus_io_base + SMBHSTCTRL);
+ byte &= 0xe3; // Clear [4:2]
+ byte |= (1<<2) | (1<<6); // Byte data read/write command, start the command
+ outb(byte, smbus_io_base + SMBHSTCTRL);
- /* poll for transaction completion */
- if (smbus_wait_until_done(smbus_io_base) < 0) {
- return -3; // timeout or error
- }
+ /* poll for transaction completion */
+ if (smbus_wait_until_done(smbus_io_base) < 0) {
+ return -3; // timeout or error
+ }
- return 0;
+ return 0;
}
static int do_smbus_read_byte(unsigned smbus_io_base, unsigned device, unsigned address)
@@ -142,8 +142,8 @@ static int do_smbus_read_byte(unsigned smbus_io_base, unsigned device, unsigned
/* set the command/address... */
outb(address & 0xff, smbus_io_base + SMBHSTCMD);
- /* set the device I'm talking too */
- outb(((device & 0x7f) << 1)|1 , smbus_io_base + SMBHSTADDR);
+ /* set the device I'm talking too */
+ outb(((device & 0x7f) << 1)|1 , smbus_io_base + SMBHSTADDR);
byte = inb(smbus_io_base + SMBHSTCTRL);
byte &= 0xe3; // Clear [4:2]
@@ -163,30 +163,30 @@ static int do_smbus_read_byte(unsigned smbus_io_base, unsigned device, unsigned
static int do_smbus_write_byte(unsigned smbus_io_base, unsigned device, unsigned address, unsigned char val)
{
- uint8_t byte;
+ uint8_t byte;
- if (smbus_wait_until_ready(smbus_io_base) < 0) {
- return -2; // not ready
- }
+ if (smbus_wait_until_ready(smbus_io_base) < 0) {
+ return -2; // not ready
+ }
- /* set the command/address... */
- outb(address & 0xff, smbus_io_base + SMBHSTCMD);
+ /* set the command/address... */
+ outb(address & 0xff, smbus_io_base + SMBHSTCMD);
- /* set the device I'm talking too */
- outb(((device & 0x7f) << 1)|0 , smbus_io_base + SMBHSTADDR);
+ /* set the device I'm talking too */
+ outb(((device & 0x7f) << 1)|0 , smbus_io_base + SMBHSTADDR);
- /* output value */
- outb(val, smbus_io_base + SMBHSTDAT0);
+ /* output value */
+ outb(val, smbus_io_base + SMBHSTDAT0);
- byte = inb(smbus_io_base + SMBHSTCTRL);
- byte &= 0xe3; // Clear [4:2]
- byte |= (1<<3) | (1<<6); // Byte data read/write command, start the command
- outb(byte, smbus_io_base + SMBHSTCTRL);
+ byte = inb(smbus_io_base + SMBHSTCTRL);
+ byte &= 0xe3; // Clear [4:2]
+ byte |= (1<<3) | (1<<6); // Byte data read/write command, start the command
+ outb(byte, smbus_io_base + SMBHSTCTRL);
- /* poll for transaction completion */
- if (smbus_wait_until_done(smbus_io_base) < 0) {
- return -3; // timeout or error
- }
+ /* poll for transaction completion */
+ if (smbus_wait_until_done(smbus_io_base) < 0) {
+ return -3; // timeout or error
+ }
- return 0;
+ return 0;
}
diff --git a/src/southbridge/broadcom/bcm5785/usb.c b/src/southbridge/broadcom/bcm5785/usb.c
index fa73b2f..9aa64df 100644
--- a/src/southbridge/broadcom/bcm5785/usb.c
+++ b/src/southbridge/broadcom/bcm5785/usb.c
@@ -23,7 +23,7 @@
static void usb_init(struct device *dev)
{
- uint32_t dword;
+ uint32_t dword;
dword = pci_read_config32(dev, 0x04);
dword |= (1<<2)|(1<<1)|(1<<0);
@@ -35,12 +35,12 @@ static void usb_init(struct device *dev)
static void lpci_set_subsystem(device_t dev, unsigned vendor, unsigned device)
{
- pci_write_config32(dev, 0x40,
- ((device & 0xffff) << 16) | (vendor & 0xffff));
+ pci_write_config32(dev, 0x40,
+ ((device & 0xffff) << 16) | (vendor & 0xffff));
}
static struct pci_operations lops_pci = {
- .set_subsystem = lpci_set_subsystem,
+ .set_subsystem = lpci_set_subsystem,
};
static struct device_operations usb_ops = {
diff --git a/src/southbridge/intel/bd82x6x/azalia.c b/src/southbridge/intel/bd82x6x/azalia.c
index d5dcde0..c122d2a 100644
--- a/src/southbridge/intel/bd82x6x/azalia.c
+++ b/src/southbridge/intel/bd82x6x/azalia.c
@@ -117,7 +117,7 @@ static int wait_for_ready(u8 *base)
int timeout = 1000;
- while(timeout--) {
+ while (timeout--) {
u32 reg32 = read32(base + HDA_ICII_REG);
if (!(reg32 & HDA_ICII_BUSY))
return 0;
@@ -145,7 +145,7 @@ static int wait_for_valid(u8 *base)
/* Use a 1msec timeout */
int timeout = 1000;
- while(timeout--) {
+ while (timeout--) {
reg32 = read32(base + HDA_ICII_REG);
if ((reg32 & (HDA_ICII_VALID | HDA_ICII_BUSY)) ==
HDA_ICII_VALID)
diff --git a/src/southbridge/intel/bd82x6x/lpc.c b/src/southbridge/intel/bd82x6x/lpc.c
index 1106912..9041816 100644
--- a/src/southbridge/intel/bd82x6x/lpc.c
+++ b/src/southbridge/intel/bd82x6x/lpc.c
@@ -125,7 +125,7 @@ static void pch_pirq_init(device_t dev)
pci_write_config8(dev, PIRQG_ROUT, pirq_routing);
pci_write_config8(dev, PIRQH_ROUT, pirq_routing);
- for(irq_dev = all_devices; irq_dev; irq_dev = irq_dev->next) {
+ for (irq_dev = all_devices; irq_dev; irq_dev = irq_dev->next) {
u8 int_pin=0;
if (!irq_dev->enabled || irq_dev->path.type != DEVICE_PATH_PCI)
diff --git a/src/southbridge/intel/bd82x6x/me.c b/src/southbridge/intel/bd82x6x/me.c
index 83c99e0..23915c3 100644
--- a/src/southbridge/intel/bd82x6x/me.c
+++ b/src/southbridge/intel/bd82x6x/me.c
@@ -445,7 +445,7 @@ static int mkhi_get_fwcaps(void)
print_cap("IntelR Power Sharing Technology (MPC)",
cap.caps_sku.intel_mpc);
print_cap("ICC Over Clocking", cap.caps_sku.icc_over_clocking);
- print_cap("Protected Audio Video Path (PAVP)", cap.caps_sku.pavp);
+ print_cap("Protected Audio Video Path (PAVP)", cap.caps_sku.pavp);
print_cap("IPV6", cap.caps_sku.ipv6);
print_cap("KVM Remote Control (KVM)", cap.caps_sku.kvm);
print_cap("Outbreak Containment Heuristic (OCH)", cap.caps_sku.och);
diff --git a/src/southbridge/intel/bd82x6x/me_8.x.c b/src/southbridge/intel/bd82x6x/me_8.x.c
index 4dbe8ed..220a176 100644
--- a/src/southbridge/intel/bd82x6x/me_8.x.c
+++ b/src/southbridge/intel/bd82x6x/me_8.x.c
@@ -703,7 +703,7 @@ static void intel_me_init(device_t dev)
if (intel_mei_setup(dev) < 0)
break;
- if(intel_me_read_mbp(&mbp_data))
+ if (intel_me_read_mbp(&mbp_data))
break;
#if CONFIG_CHROMEOS && 0 /* DISABLED */
@@ -893,7 +893,7 @@ static int intel_me_read_mbp(me_bios_payload *mbp_data)
default:
printk(BIOS_ERR, "ME: unknown mbp item id 0x%x! Skipping\n",
mbp_item_id);
- while(copy_size--)
+ while (copy_size--)
read_cb();
continue;
}
@@ -904,7 +904,7 @@ static int intel_me_read_mbp(me_bios_payload *mbp_data)
buffer_room, copy_size, mbp_item_id);
return -1;
}
- while(copy_size--)
+ while (copy_size--)
*copy_addr++ = read_cb();
}
@@ -914,7 +914,7 @@ static int intel_me_read_mbp(me_bios_payload *mbp_data)
{
int cntr = 0;
- while(host.interrupt_generate) {
+ while (host.interrupt_generate) {
read_host_csr(&host);
cntr++;
}
diff --git a/src/southbridge/intel/bd82x6x/reset.c b/src/southbridge/intel/bd82x6x/reset.c
index daabbbc..804fb81 100644
--- a/src/southbridge/intel/bd82x6x/reset.c
+++ b/src/southbridge/intel/bd82x6x/reset.c
@@ -19,10 +19,10 @@
void soft_reset(void)
{
- outb(0x04, 0xcf9);
+ outb(0x04, 0xcf9);
}
void hard_reset(void)
{
- outb(0x06, 0xcf9);
+ outb(0x06, 0xcf9);
}
diff --git a/src/southbridge/intel/bd82x6x/smihandler.c b/src/southbridge/intel/bd82x6x/smihandler.c
index bc19b78..0478285 100644
--- a/src/southbridge/intel/bd82x6x/smihandler.c
+++ b/src/southbridge/intel/bd82x6x/smihandler.c
@@ -271,37 +271,37 @@ void southbridge_smi_set_eos(void)
static void busmaster_disable_on_bus(int bus)
{
- int slot, func;
- unsigned int val;
- unsigned char hdr;
-
- for (slot = 0; slot < 0x20; slot++) {
- for (func = 0; func < 8; func++) {
- u32 reg32;
- device_t dev = PCI_DEV(bus, slot, func);
-
- val = pci_read_config32(dev, PCI_VENDOR_ID);
-
- if (val == 0xffffffff || val == 0x00000000 ||
- val == 0x0000ffff || val == 0xffff0000)
- continue;
-
- /* Disable Bus Mastering for this one device */
- reg32 = pci_read_config32(dev, PCI_COMMAND);
- reg32 &= ~PCI_COMMAND_MASTER;
- pci_write_config32(dev, PCI_COMMAND, reg32);
-
- /* If this is a bridge, then follow it. */
- hdr = pci_read_config8(dev, PCI_HEADER_TYPE);
- hdr &= 0x7f;
- if (hdr == PCI_HEADER_TYPE_BRIDGE ||
- hdr == PCI_HEADER_TYPE_CARDBUS) {
- unsigned int buses;
- buses = pci_read_config32(dev, PCI_PRIMARY_BUS);
- busmaster_disable_on_bus((buses >> 8) & 0xff);
- }
- }
- }
+ int slot, func;
+ unsigned int val;
+ unsigned char hdr;
+
+ for (slot = 0; slot < 0x20; slot++) {
+ for (func = 0; func < 8; func++) {
+ u32 reg32;
+ device_t dev = PCI_DEV(bus, slot, func);
+
+ val = pci_read_config32(dev, PCI_VENDOR_ID);
+
+ if (val == 0xffffffff || val == 0x00000000 ||
+ val == 0x0000ffff || val == 0xffff0000)
+ continue;
+
+ /* Disable Bus Mastering for this one device */
+ reg32 = pci_read_config32(dev, PCI_COMMAND);
+ reg32 &= ~PCI_COMMAND_MASTER;
+ pci_write_config32(dev, PCI_COMMAND, reg32);
+
+ /* If this is a bridge, then follow it. */
+ hdr = pci_read_config8(dev, PCI_HEADER_TYPE);
+ hdr &= 0x7f;
+ if (hdr == PCI_HEADER_TYPE_BRIDGE ||
+ hdr == PCI_HEADER_TYPE_CARDBUS) {
+ unsigned int buses;
+ buses = pci_read_config32(dev, PCI_PRIMARY_BUS);
+ busmaster_disable_on_bus((buses >> 8) & 0xff);
+ }
+ }
+ }
}
static void southbridge_gate_memory_reset_real(int offset,
@@ -863,7 +863,7 @@ void southbridge_smi_handler(void)
}
}
- if(dump) {
+ if (dump) {
dump_smi_status(smi_sts);
}
diff --git a/src/southbridge/intel/fsp_bd82x6x/azalia.c b/src/southbridge/intel/fsp_bd82x6x/azalia.c
index 5ec708e..b64d923 100644
--- a/src/southbridge/intel/fsp_bd82x6x/azalia.c
+++ b/src/southbridge/intel/fsp_bd82x6x/azalia.c
@@ -118,7 +118,7 @@ static int wait_for_ready(u8 *base)
int timeout = 50;
- while(timeout--) {
+ while (timeout--) {
u32 reg32 = read32(base + HDA_ICII_REG);
if (!(reg32 & HDA_ICII_BUSY))
return 0;
@@ -147,7 +147,7 @@ static int wait_for_valid(u8 *base)
* same duration */
int timeout = 50;
- while(timeout--) {
+ while (timeout--) {
reg32 = read32(base + HDA_ICII_REG);
if ((reg32 & (HDA_ICII_VALID | HDA_ICII_BUSY)) ==
HDA_ICII_VALID)
diff --git a/src/southbridge/intel/fsp_bd82x6x/lpc.c b/src/southbridge/intel/fsp_bd82x6x/lpc.c
index d12cd4e..faec69a 100644
--- a/src/southbridge/intel/fsp_bd82x6x/lpc.c
+++ b/src/southbridge/intel/fsp_bd82x6x/lpc.c
@@ -132,7 +132,7 @@ static void pch_pirq_init(device_t dev)
* I am not so sure anymore he was right.
*/
- for(irq_dev = all_devices; irq_dev; irq_dev = irq_dev->next) {
+ for (irq_dev = all_devices; irq_dev; irq_dev = irq_dev->next) {
u8 int_pin=0, int_line=0;
if (!irq_dev->enabled || irq_dev->path.type != DEVICE_PATH_PCI)
diff --git a/src/southbridge/intel/fsp_bd82x6x/me.c b/src/southbridge/intel/fsp_bd82x6x/me.c
index 68a9ee5..a951f9f 100644
--- a/src/southbridge/intel/fsp_bd82x6x/me.c
+++ b/src/southbridge/intel/fsp_bd82x6x/me.c
@@ -444,7 +444,7 @@ static int mkhi_get_fwcaps(void)
print_cap("IntelR Power Sharing Technology (MPC)",
cap.caps_sku.intel_mpc);
print_cap("ICC Over Clocking", cap.caps_sku.icc_over_clocking);
- print_cap("Protected Audio Video Path (PAVP)", cap.caps_sku.pavp);
+ print_cap("Protected Audio Video Path (PAVP)", cap.caps_sku.pavp);
print_cap("IPV6", cap.caps_sku.ipv6);
print_cap("KVM Remote Control (KVM)", cap.caps_sku.kvm);
print_cap("Outbreak Containment Heuristic (OCH)", cap.caps_sku.och);
diff --git a/src/southbridge/intel/fsp_bd82x6x/me_8.x.c b/src/southbridge/intel/fsp_bd82x6x/me_8.x.c
index e29d86b..0d3a01e 100644
--- a/src/southbridge/intel/fsp_bd82x6x/me_8.x.c
+++ b/src/southbridge/intel/fsp_bd82x6x/me_8.x.c
@@ -385,11 +385,10 @@ static int mkhi_get_fwcaps(mefwcaps_sku *cap)
};
/* Send request and wait for response */
- if (mei_sendrecv(&mei, &mkhi, &rule_id, &cap_msg, sizeof(cap_msg))
- < 0) {
+ if (mei_sendrecv(&mei, &mkhi, &rule_id, &cap_msg, sizeof(cap_msg)) < 0) {
printk(BIOS_ERR, "ME: GET FWCAPS message failed\n");
return -1;
- }
+ }
*cap = cap_msg.caps_sku;
return 0;
}
@@ -413,7 +412,7 @@ static void me_print_fwcaps(mbp_fw_caps *caps_section)
print_cap("IntelR Capability Licensing Service (CLS)", cap->intel_cls);
print_cap("IntelR Power Sharing Technology (MPC)", cap->intel_mpc);
print_cap("ICC Over Clocking", cap->icc_over_clocking);
- print_cap("Protected Audio Video Path (PAVP)", cap->pavp);
+ print_cap("Protected Audio Video Path (PAVP)", cap->pavp);
print_cap("IPV6", cap->ipv6);
print_cap("KVM Remote Control (KVM)", cap->kvm);
print_cap("Outbreak Containment Heuristic (OCH)", cap->och);
@@ -702,7 +701,7 @@ static void intel_me_init(device_t dev)
if (intel_mei_setup(dev) < 0)
break;
- if(intel_me_read_mbp(&mbp_data))
+ if (intel_me_read_mbp(&mbp_data))
break;
#if CONFIG_CHROMEOS && 0 /* DISABLED */
@@ -901,7 +900,7 @@ static int intel_me_read_mbp(me_bios_payload *mbp_data)
buffer_room, copy_size, mbp_item_id);
return -1;
}
- while(copy_size--)
+ while (copy_size--)
*copy_addr++ = read_cb();
}
@@ -911,7 +910,7 @@ static int intel_me_read_mbp(me_bios_payload *mbp_data)
{
int cntr = 0;
- while(host.interrupt_generate) {
+ while (host.interrupt_generate) {
read_host_csr(&host);
cntr++;
}
diff --git a/src/southbridge/intel/fsp_bd82x6x/reset.c b/src/southbridge/intel/fsp_bd82x6x/reset.c
index c2e76d5..a2e8236 100644
--- a/src/southbridge/intel/fsp_bd82x6x/reset.c
+++ b/src/southbridge/intel/fsp_bd82x6x/reset.c
@@ -20,10 +20,10 @@
void soft_reset(void)
{
- outb(0x04, 0xcf9);
+ outb(0x04, 0xcf9);
}
void hard_reset(void)
{
- outb(0x06, 0xcf9);
+ outb(0x06, 0xcf9);
}
diff --git a/src/southbridge/intel/fsp_bd82x6x/smihandler.c b/src/southbridge/intel/fsp_bd82x6x/smihandler.c
index 77ada10..01ace59 100644
--- a/src/southbridge/intel/fsp_bd82x6x/smihandler.c
+++ b/src/southbridge/intel/fsp_bd82x6x/smihandler.c
@@ -235,37 +235,37 @@ void southbridge_smi_set_eos(void)
static void busmaster_disable_on_bus(int bus)
{
- int slot, func;
- unsigned int val;
- unsigned char hdr;
-
- for (slot = 0; slot < 0x20; slot++) {
- for (func = 0; func < 8; func++) {
- u32 reg32;
- device_t dev = PCI_DEV(bus, slot, func);
-
- val = pci_read_config32(dev, PCI_VENDOR_ID);
-
- if (val == 0xffffffff || val == 0x00000000 ||
- val == 0x0000ffff || val == 0xffff0000)
- continue;
-
- /* Disable Bus Mastering for this one device */
- reg32 = pci_read_config32(dev, PCI_COMMAND);
- reg32 &= ~PCI_COMMAND_MASTER;
- pci_write_config32(dev, PCI_COMMAND, reg32);
-
- /* If this is a bridge, then follow it. */
- hdr = pci_read_config8(dev, PCI_HEADER_TYPE);
- hdr &= 0x7f;
- if (hdr == PCI_HEADER_TYPE_BRIDGE ||
- hdr == PCI_HEADER_TYPE_CARDBUS) {
- unsigned int buses;
- buses = pci_read_config32(dev, PCI_PRIMARY_BUS);
- busmaster_disable_on_bus((buses >> 8) & 0xff);
- }
- }
- }
+ int slot, func;
+ unsigned int val;
+ unsigned char hdr;
+
+ for (slot = 0; slot < 0x20; slot++) {
+ for (func = 0; func < 8; func++) {
+ u32 reg32;
+ device_t dev = PCI_DEV(bus, slot, func);
+
+ val = pci_read_config32(dev, PCI_VENDOR_ID);
+
+ if (val == 0xffffffff || val == 0x00000000 ||
+ val == 0x0000ffff || val == 0xffff0000)
+ continue;
+
+ /* Disable Bus Mastering for this one device */
+ reg32 = pci_read_config32(dev, PCI_COMMAND);
+ reg32 &= ~PCI_COMMAND_MASTER;
+ pci_write_config32(dev, PCI_COMMAND, reg32);
+
+ /* If this is a bridge, then follow it. */
+ hdr = pci_read_config8(dev, PCI_HEADER_TYPE);
+ hdr &= 0x7f;
+ if (hdr == PCI_HEADER_TYPE_BRIDGE ||
+ hdr == PCI_HEADER_TYPE_CARDBUS) {
+ unsigned int buses;
+ buses = pci_read_config32(dev, PCI_PRIMARY_BUS);
+ busmaster_disable_on_bus((buses >> 8) & 0xff);
+ }
+ }
+ }
}
/*
@@ -749,7 +749,7 @@ void southbridge_smi_handler(void)
}
}
- if(dump) {
+ if (dump) {
dump_smi_status(smi_sts);
}
diff --git a/src/southbridge/intel/fsp_i89xx/lpc.c b/src/southbridge/intel/fsp_i89xx/lpc.c
index 5b8fdbc..1514500 100644
--- a/src/southbridge/intel/fsp_i89xx/lpc.c
+++ b/src/southbridge/intel/fsp_i89xx/lpc.c
@@ -132,7 +132,7 @@ static void pch_pirq_init(device_t dev)
* I am not so sure anymore he was right.
*/
- for(irq_dev = all_devices; irq_dev; irq_dev = irq_dev->next) {
+ for (irq_dev = all_devices; irq_dev; irq_dev = irq_dev->next) {
u8 int_pin=0, int_line=0;
if (!irq_dev->enabled || irq_dev->path.type != DEVICE_PATH_PCI)
diff --git a/src/southbridge/intel/fsp_i89xx/me.c b/src/southbridge/intel/fsp_i89xx/me.c
index caf24e3..7ea42d4 100644
--- a/src/southbridge/intel/fsp_i89xx/me.c
+++ b/src/southbridge/intel/fsp_i89xx/me.c
@@ -444,7 +444,7 @@ static int mkhi_get_fwcaps(void)
print_cap("IntelR Power Sharing Technology (MPC)",
cap.caps_sku.intel_mpc);
print_cap("ICC Over Clocking", cap.caps_sku.icc_over_clocking);
- print_cap("Protected Audio Video Path (PAVP)", cap.caps_sku.pavp);
+ print_cap("Protected Audio Video Path (PAVP)", cap.caps_sku.pavp);
print_cap("IPV6", cap.caps_sku.ipv6);
print_cap("KVM Remote Control (KVM)", cap.caps_sku.kvm);
print_cap("Outbreak Containment Heuristic (OCH)", cap.caps_sku.och);
diff --git a/src/southbridge/intel/fsp_i89xx/me_8.x.c b/src/southbridge/intel/fsp_i89xx/me_8.x.c
index 090d8d0..f25843e 100644
--- a/src/southbridge/intel/fsp_i89xx/me_8.x.c
+++ b/src/southbridge/intel/fsp_i89xx/me_8.x.c
@@ -413,7 +413,7 @@ static void me_print_fwcaps(mbp_fw_caps *caps_section)
print_cap("IntelR Capability Licensing Service (CLS)", cap->intel_cls);
print_cap("IntelR Power Sharing Technology (MPC)", cap->intel_mpc);
print_cap("ICC Over Clocking", cap->icc_over_clocking);
- print_cap("Protected Audio Video Path (PAVP)", cap->pavp);
+ print_cap("Protected Audio Video Path (PAVP)", cap->pavp);
print_cap("IPV6", cap->ipv6);
print_cap("KVM Remote Control (KVM)", cap->kvm);
print_cap("Outbreak Containment Heuristic (OCH)", cap->och);
@@ -670,7 +670,7 @@ static void intel_me_init(device_t dev)
if (intel_mei_setup(dev) < 0)
break;
- if(intel_me_read_mbp(&mbp_data))
+ if (intel_me_read_mbp(&mbp_data))
break;
#if (CONFIG_DEFAULT_CONSOLE_LOGLEVEL >= BIOS_DEBUG)
@@ -855,7 +855,7 @@ static int intel_me_read_mbp(me_bios_payload *mbp_data)
buffer_room, copy_size, mbp_item_id);
return -1;
}
- while(copy_size--)
+ while (copy_size--)
*copy_addr++ = read_cb();
}
@@ -865,7 +865,7 @@ static int intel_me_read_mbp(me_bios_payload *mbp_data)
{
int cntr = 0;
- while(host.interrupt_generate) {
+ while (host.interrupt_generate) {
read_host_csr(&host);
cntr++;
}
diff --git a/src/southbridge/intel/fsp_i89xx/romstage.c b/src/southbridge/intel/fsp_i89xx/romstage.c
index c5c1136..09cce59 100644
--- a/src/southbridge/intel/fsp_i89xx/romstage.c
+++ b/src/southbridge/intel/fsp_i89xx/romstage.c
@@ -203,7 +203,7 @@ void romstage_main_continue(EFI_STATUS status, VOID *HobListPtr) {
cbmem_was_initted = !cbmem_recovery(0);
- if(cbmem_was_initted) {
+ if (cbmem_was_initted) {
reset_system();
}
diff --git a/src/southbridge/intel/fsp_i89xx/smihandler.c b/src/southbridge/intel/fsp_i89xx/smihandler.c
index 27b8166..d4dbb22 100644
--- a/src/southbridge/intel/fsp_i89xx/smihandler.c
+++ b/src/southbridge/intel/fsp_i89xx/smihandler.c
@@ -235,37 +235,37 @@ void southbridge_smi_set_eos(void)
static void busmaster_disable_on_bus(int bus)
{
- int slot, func;
- unsigned int val;
- unsigned char hdr;
-
- for (slot = 0; slot < 0x20; slot++) {
- for (func = 0; func < 8; func++) {
- u32 reg32;
- device_t dev = PCI_DEV(bus, slot, func);
-
- val = pci_read_config32(dev, PCI_VENDOR_ID);
-
- if (val == 0xffffffff || val == 0x00000000 ||
- val == 0x0000ffff || val == 0xffff0000)
- continue;
-
- /* Disable Bus Mastering for this one device */
- reg32 = pci_read_config32(dev, PCI_COMMAND);
- reg32 &= ~PCI_COMMAND_MASTER;
- pci_write_config32(dev, PCI_COMMAND, reg32);
-
- /* If this is a bridge, then follow it. */
- hdr = pci_read_config8(dev, PCI_HEADER_TYPE);
- hdr &= 0x7f;
- if (hdr == PCI_HEADER_TYPE_BRIDGE ||
- hdr == PCI_HEADER_TYPE_CARDBUS) {
- unsigned int buses;
- buses = pci_read_config32(dev, PCI_PRIMARY_BUS);
- busmaster_disable_on_bus((buses >> 8) & 0xff);
- }
- }
- }
+ int slot, func;
+ unsigned int val;
+ unsigned char hdr;
+
+ for (slot = 0; slot < 0x20; slot++) {
+ for (func = 0; func < 8; func++) {
+ u32 reg32;
+ device_t dev = PCI_DEV(bus, slot, func);
+
+ val = pci_read_config32(dev, PCI_VENDOR_ID);
+
+ if (val == 0xffffffff || val == 0x00000000 ||
+ val == 0x0000ffff || val == 0xffff0000)
+ continue;
+
+ /* Disable Bus Mastering for this one device */
+ reg32 = pci_read_config32(dev, PCI_COMMAND);
+ reg32 &= ~PCI_COMMAND_MASTER;
+ pci_write_config32(dev, PCI_COMMAND, reg32);
+
+ /* If this is a bridge, then follow it. */
+ hdr = pci_read_config8(dev, PCI_HEADER_TYPE);
+ hdr &= 0x7f;
+ if (hdr == PCI_HEADER_TYPE_BRIDGE ||
+ hdr == PCI_HEADER_TYPE_CARDBUS) {
+ unsigned int buses;
+ buses = pci_read_config32(dev, PCI_PRIMARY_BUS);
+ busmaster_disable_on_bus((buses >> 8) & 0xff);
+ }
+ }
+ }
}
/*
@@ -746,7 +746,7 @@ void southbridge_smi_handler(void)
}
}
- if(dump) {
+ if (dump) {
dump_smi_status(smi_sts);
}
diff --git a/src/southbridge/intel/fsp_rangeley/gpio.c b/src/southbridge/intel/fsp_rangeley/gpio.c
index e57d855..2a2061c 100644
--- a/src/southbridge/intel/fsp_rangeley/gpio.c
+++ b/src/southbridge/intel/fsp_rangeley/gpio.c
@@ -64,7 +64,7 @@ void setup_soc_gpios(const struct soc_gpio_map *gpio)
/* CFIO Core Well Set 1 */
if ((gpio->core.cfio_init != NULL) || (gpio->core.cfio_entrynum != 0)) {
write32(cfiobase + (0x0700 / sizeof(u32)), (u32)0x01001002);
- for(cfio_cnt = 0; cfio_cnt < gpio->core.cfio_entrynum; cfio_cnt++) {
+ for (cfio_cnt = 0; cfio_cnt < gpio->core.cfio_entrynum; cfio_cnt++) {
if (!((u32)gpio->core.cfio_init[cfio_cnt].pad_conf_0))
continue;
write32(cfiobase + ((CFIO_PAD_CONF0 + (16*cfio_cnt))/sizeof(u32)), (u32)gpio->core.cfio_init[cfio_cnt].pad_conf_0);
@@ -78,7 +78,7 @@ void setup_soc_gpios(const struct soc_gpio_map *gpio)
/* CFIO SUS Well Set 1 */
if ((gpio->sus.cfio_init != NULL) || (gpio->sus.cfio_entrynum != 0)) {
write32(cfiobase + (0x1700 / sizeof(u32)), (u32)0x01001002);
- for(cfio_cnt = 0; cfio_cnt < gpio->sus.cfio_entrynum; cfio_cnt++) {
+ for (cfio_cnt = 0; cfio_cnt < gpio->sus.cfio_entrynum; cfio_cnt++) {
if (!((u32)gpio->sus.cfio_init[cfio_cnt].pad_conf_0))
continue;
write32(cfiobase + ((CFIO_PAD_CONF0 + 0x1000 + (16*cfio_cnt))/sizeof(u32)), (u32)gpio->sus.cfio_init[cfio_cnt].pad_conf_0);
diff --git a/src/southbridge/intel/fsp_rangeley/lpc.c b/src/southbridge/intel/fsp_rangeley/lpc.c
index 11aa60d..ab61750 100644
--- a/src/southbridge/intel/fsp_rangeley/lpc.c
+++ b/src/southbridge/intel/fsp_rangeley/lpc.c
@@ -137,7 +137,7 @@ static void write_pci_config_irqs(void)
* the Interrupt Route registers in the ILB
*/
printk(BIOS_DEBUG, "PCI_CFG IRQ: Write PCI config space IRQ assignments\n");
- for(irq_dev = all_devices; irq_dev; irq_dev = irq_dev->next) {
+ for (irq_dev = all_devices; irq_dev; irq_dev = irq_dev->next) {
if ((irq_dev->path.type != DEVICE_PATH_PCI) ||
(!irq_dev->enabled))
@@ -225,7 +225,7 @@ static void soc_pirq_init(device_t dev)
write16(ir_base + i, ir->pcidev[i]);
/* If the entry is more than just 0, print it out */
- if(ir->pcidev[i]) {
+ if (ir->pcidev[i]) {
printk(BIOS_SPEW, " %d: ", i);
for (j = 0; j < 4; j++) {
pirq = (ir->pcidev[i] >> (j * 4)) & 0xF;
diff --git a/src/southbridge/intel/i3100/early_smbus.c b/src/southbridge/intel/i3100/early_smbus.c
index 12a9202..2cb241a 100644
--- a/src/southbridge/intel/i3100/early_smbus.c
+++ b/src/southbridge/intel/i3100/early_smbus.c
@@ -27,7 +27,7 @@ static void enable_smbus(void)
pci_write_config8(dev, 0x40, 1);
pci_write_config8(dev, 0x4, 1);
/* SMBALERT_DIS */
- outb(4, SMBUS_IO_BASE + SMBSLVCMD);
+ outb(4, SMBUS_IO_BASE + SMBSLVCMD);
/* Disable interrupt generation */
outb(0, SMBUS_IO_BASE + SMBHSTCTL);
diff --git a/src/southbridge/intel/i3100/lpc.c b/src/southbridge/intel/i3100/lpc.c
index 77853a8..7b319cf 100644
--- a/src/southbridge/intel/i3100/lpc.c
+++ b/src/southbridge/intel/i3100/lpc.c
@@ -206,19 +206,19 @@ static void i3100_pirq_init(device_t dev)
if (config->pirq_e_h)
pci_write_config32(dev, 0x68, config->pirq_e_h);
- for (irq_dev = all_devices; irq_dev; irq_dev = irq_dev->next) {
- u8 int_pin=0, int_line=0;
+ for (irq_dev = all_devices; irq_dev; irq_dev = irq_dev->next) {
+ u8 int_pin=0, int_line=0;
- if (!irq_dev->enabled || irq_dev->path.type != DEVICE_PATH_PCI)
- continue;
+ if (!irq_dev->enabled || irq_dev->path.type != DEVICE_PATH_PCI)
+ continue;
- int_pin = pci_read_config8(irq_dev, PCI_INTERRUPT_PIN);
- switch (int_pin) {
- case 1: /* INTA# */
+ int_pin = pci_read_config8(irq_dev, PCI_INTERRUPT_PIN);
+ switch (int_pin) {
+ case 1: /* INTA# */
int_line = config->pirq_a_d & 0xff;
break;
- case 2: /* INTB# */
+ case 2: /* INTB# */
int_line = (config->pirq_a_d >> 8) & 0xff;
break;
@@ -226,17 +226,17 @@ static void i3100_pirq_init(device_t dev)
int_line = (config->pirq_a_d >> 16) & 0xff;
break;
- case 4: /* INTD# */
+ case 4: /* INTD# */
int_line = (config->pirq_a_d >> 24) & 0xff;
break;
- }
+ }
- if (!int_line)
- continue;
+ if (!int_line)
+ continue;
printk(BIOS_DEBUG, "%s: irq pin %d, irq line %d\n", dev_path(irq_dev), int_pin, int_line);
- pci_write_config8(irq_dev, PCI_INTERRUPT_LINE, int_line);
- }
+ pci_write_config8(irq_dev, PCI_INTERRUPT_LINE, int_line);
+ }
}
diff --git a/src/southbridge/intel/i3100/sata.c b/src/southbridge/intel/i3100/sata.c
index f4dff8b..27bd2ce 100644
--- a/src/southbridge/intel/i3100/sata.c
+++ b/src/southbridge/intel/i3100/sata.c
@@ -42,7 +42,7 @@ static void sata_init(struct device *dev)
/* Enable SATA devices */
printk(BIOS_INFO, "SATA init (%s mode)\n", ahci ? "AHCI" : "Legacy");
- if(ahci) {
+ if (ahci) {
/* AHCI mode */
pci_write_config8(dev, SATA_MAP, (1 << 6) | (0 << 0));
diff --git a/src/southbridge/intel/i82371eb/acpi_tables.c b/src/southbridge/intel/i82371eb/acpi_tables.c
index 5b8d0ed..59d5dea 100644
--- a/src/southbridge/intel/i82371eb/acpi_tables.c
+++ b/src/southbridge/intel/i82371eb/acpi_tables.c
@@ -28,7 +28,7 @@ static int determine_total_number_of_cores(void)
{
device_t cpu;
int count = 0;
- for(cpu = all_devices; cpu; cpu = cpu->next) {
+ for (cpu = all_devices; cpu; cpu = cpu->next) {
if ((cpu->path.type != DEVICE_PATH_APIC) ||
(cpu->bus->dev->path.type != DEVICE_PATH_CPU_CLUSTER)) {
continue;
diff --git a/src/southbridge/intel/i82371eb/smbus.h b/src/southbridge/intel/i82371eb/smbus.h
index fd02217..de34504 100644
--- a/src/southbridge/intel/i82371eb/smbus.h
+++ b/src/southbridge/intel/i82371eb/smbus.h
@@ -35,12 +35,12 @@ static int smbus_wait_until_ready(unsigned smbus_io_base)
break;
}
#if 0
- if(loops == (SMBUS_TIMEOUT / 2)) {
+ if (loops == (SMBUS_TIMEOUT / 2)) {
outw(inw(smbus_io_base + SMBHST_STATUS),
smbus_io_base + SMBHST_STATUS);
}
#endif
- } while(--loops);
+ } while (--loops);
return loops?0:SMBUS_WAIT_UNTIL_READY_TIMEOUT;
}
@@ -62,7 +62,7 @@ static int smbus_wait_until_done(unsigned smbus_io_base)
if (val & 0xfe) {
break;
}
- } while(--loops);
+ } while (--loops);
return loops?0:SMBUS_WAIT_UNTIL_DONE_TIMEOUT;
}
diff --git a/src/southbridge/intel/i82801dx/smihandler.c b/src/southbridge/intel/i82801dx/smihandler.c
index f4ab2f6..a558169 100644
--- a/src/southbridge/intel/i82801dx/smihandler.c
+++ b/src/southbridge/intel/i82801dx/smihandler.c
@@ -233,37 +233,37 @@ void southbridge_smi_set_eos(void)
static void busmaster_disable_on_bus(int bus)
{
- int slot, func;
- unsigned int val;
- unsigned char hdr;
-
- for (slot = 0; slot < 0x20; slot++) {
- for (func = 0; func < 8; func++) {
- u32 reg32;
- device_t dev = PCI_DEV(bus, slot, func);
-
- val = pci_read_config32(dev, PCI_VENDOR_ID);
-
- if (val == 0xffffffff || val == 0x00000000 ||
- val == 0x0000ffff || val == 0xffff0000)
- continue;
-
- /* Disable Bus Mastering for this one device */
- reg32 = pci_read_config32(dev, PCI_COMMAND);
- reg32 &= ~PCI_COMMAND_MASTER;
- pci_write_config32(dev, PCI_COMMAND, reg32);
-
- /* If this is a bridge, then follow it. */
- hdr = pci_read_config8(dev, PCI_HEADER_TYPE);
- hdr &= 0x7f;
- if (hdr == PCI_HEADER_TYPE_BRIDGE ||
- hdr == PCI_HEADER_TYPE_CARDBUS) {
- unsigned int buses;
- buses = pci_read_config32(dev, PCI_PRIMARY_BUS);
- busmaster_disable_on_bus((buses >> 8) & 0xff);
- }
- }
- }
+ int slot, func;
+ unsigned int val;
+ unsigned char hdr;
+
+ for (slot = 0; slot < 0x20; slot++) {
+ for (func = 0; func < 8; func++) {
+ u32 reg32;
+ device_t dev = PCI_DEV(bus, slot, func);
+
+ val = pci_read_config32(dev, PCI_VENDOR_ID);
+
+ if (val == 0xffffffff || val == 0x00000000 ||
+ val == 0x0000ffff || val == 0xffff0000)
+ continue;
+
+ /* Disable Bus Mastering for this one device */
+ reg32 = pci_read_config32(dev, PCI_COMMAND);
+ reg32 &= ~PCI_COMMAND_MASTER;
+ pci_write_config32(dev, PCI_COMMAND, reg32);
+
+ /* If this is a bridge, then follow it. */
+ hdr = pci_read_config8(dev, PCI_HEADER_TYPE);
+ hdr &= 0x7f;
+ if (hdr == PCI_HEADER_TYPE_BRIDGE ||
+ hdr == PCI_HEADER_TYPE_CARDBUS) {
+ unsigned int buses;
+ buses = pci_read_config32(dev, PCI_PRIMARY_BUS);
+ busmaster_disable_on_bus((buses >> 8) & 0xff);
+ }
+ }
+ }
}
@@ -636,7 +636,7 @@ void southbridge_smi_handler(unsigned int node, smm_state_save_area_t *state_sav
}
}
- if(dump) {
+ if (dump) {
dump_smi_status(smi_sts);
}
diff --git a/src/southbridge/intel/i82801ex/early_smbus.c b/src/southbridge/intel/i82801ex/early_smbus.c
index 979b842..ad543e7 100644
--- a/src/southbridge/intel/i82801ex/early_smbus.c
+++ b/src/southbridge/intel/i82801ex/early_smbus.c
@@ -81,7 +81,7 @@ static int smbus_write_block(unsigned device, unsigned length, unsigned cmd,
/* setup transaction */
/* Obtain ownership */
outb(inb(SMBUS_IO_BASE + SMBHSTSTAT), SMBUS_IO_BASE + SMBHSTSTAT);
- for(stat=0;(stat&0x40)==0;) {
+ for (stat=0;(stat&0x40)==0;) {
stat = inb(SMBUS_IO_BASE + SMBHSTSTAT);
}
/* clear the done bit */
@@ -105,7 +105,7 @@ static int smbus_write_block(unsigned device, unsigned length, unsigned cmd,
outb((inb(SMBUS_IO_BASE + SMBHSTCTL) & 0xE3) | (0x5 << 2) | 0x40,
SMBUS_IO_BASE + SMBHSTCTL);
- for(i=0;i<length;i++) {
+ for (i=0;i<length;i++) {
/* poll for transaction completion */
if (smbus_wait_until_blk_done(SMBUS_IO_BASE) < 0) {
@@ -113,7 +113,7 @@ static int smbus_write_block(unsigned device, unsigned length, unsigned cmd,
}
/* load the next byte */
- if(i>3)
+ if (i>3)
byte=(data2>>(i%4))&0x0ff;
else
byte=(data1>>(i))&0x0ff;
diff --git a/src/southbridge/intel/i82801ex/lpc.c b/src/southbridge/intel/i82801ex/lpc.c
index 630484a..7d01dbc 100644
--- a/src/southbridge/intel/i82801ex/lpc.c
+++ b/src/southbridge/intel/i82801ex/lpc.c
@@ -78,8 +78,8 @@ static void i82801ex_pci_dma_cfg(device_t dev)
#define LPC_EN 0xe6
static void i82801ex_enable_lpc(device_t dev)
{
- /* lpc i/f enable */
- pci_write_config8(dev, LPC_EN, 0x0d);
+ /* lpc i/f enable */
+ pci_write_config8(dev, LPC_EN, 0x0d);
}
typedef struct southbridge_intel_i82801ex_config config_t;
@@ -92,7 +92,7 @@ static void set_i82801ex_gpio_use_sel(
gpio_use_sel = 0x1A003180;
gpio_use_sel2 = 0x00000007;
- for(i = 0; i < 64; i++) {
+ for (i = 0; i < 64; i++) {
int val;
switch(config->gpio[i] & ICH5R_GPIO_USE_MASK) {
case ICH5R_GPIO_USE_AS_NATIVE: val = 0; break;
@@ -121,7 +121,7 @@ static void set_i82801ex_gpio_direction(
gpio_io_sel = 0x0000ffff;
gpio_io_sel2 = 0x00000300;
- for(i = 0; i < 64; i++) {
+ for (i = 0; i < 64; i++) {
int val;
switch(config->gpio[i] & ICH5R_GPIO_SEL_MASK) {
case ICH5R_GPIO_SEL_OUTPUT: val = 0; break;
@@ -152,7 +152,7 @@ static void set_i82801ex_gpio_level(
gpio_lvl = 0x1b3f0000;
gpio_blink = 0x00040000;
gpio_lvl2 = 0x00030207;
- for(i = 0; i < 64; i++) {
+ for (i = 0; i < 64; i++) {
int val, blink;
switch(config->gpio[i] & ICH5R_GPIO_LVL_MASK) {
case ICH5R_GPIO_LVL_LOW: val = 0; blink = 0; break;
@@ -184,7 +184,7 @@ static void set_i82801ex_gpio_inv(
int i;
gpio_inv = 0x00000000;
- for(i = 0; i < 32; i++) {
+ for (i = 0; i < 32; i++) {
int val;
switch(config->gpio[i] & ICH5R_GPIO_INV_MASK) {
case ICH5R_GPIO_INV_OFF: val = 0; break;
@@ -205,10 +205,10 @@ static void i82801ex_pirq_init(device_t dev)
/* Get the chip configuration */
config = dev->chip_info;
- if(config->pirq_a_d) {
+ if (config->pirq_a_d) {
pci_write_config32(dev, 0x60, config->pirq_a_d);
}
- if(config->pirq_e_h) {
+ if (config->pirq_e_h) {
pci_write_config32(dev, 0x68, config->pirq_e_h);
}
}
@@ -292,7 +292,7 @@ static void lpc_init(struct device *dev)
/* Clear SATA to non raid */
pci_write_config8(dev, 0xae, 0x00);
- get_option(&pwr_on, "power_on_after_fail");
+ get_option(&pwr_on, "power_on_after_fail");
byte = pci_read_config8(dev, 0xa4);
byte &= 0xfe;
if (!pwr_on) {
diff --git a/src/southbridge/intel/i82801ex/reset.c b/src/southbridge/intel/i82801ex/reset.c
index 9936892..8036ffd 100644
--- a/src/southbridge/intel/i82801ex/reset.c
+++ b/src/southbridge/intel/i82801ex/reset.c
@@ -3,6 +3,6 @@
void hard_reset(void)
{
- /* Try rebooting through port 0xcf9 */
- outb((0 <<3)|(1<<2)|(1<<1), 0xcf9);
+ /* Try rebooting through port 0xcf9 */
+ outb((0 <<3)|(1<<2)|(1<<1), 0xcf9);
}
diff --git a/src/southbridge/intel/i82801ex/smbus.h b/src/southbridge/intel/i82801ex/smbus.h
index b166797..dbb7b7a 100644
--- a/src/southbridge/intel/i82801ex/smbus.h
+++ b/src/southbridge/intel/i82801ex/smbus.h
@@ -29,7 +29,7 @@ static int smbus_wait_until_ready(unsigned smbus_io_base)
if (--loops == 0)
break;
byte = inb(smbus_io_base + SMBHSTSTAT);
- } while(byte & 1);
+ } while (byte & 1);
return loops?0:-1;
}
@@ -42,7 +42,7 @@ static int smbus_wait_until_done(unsigned smbus_io_base)
if (--loops == 0)
break;
byte = inb(smbus_io_base + SMBHSTSTAT);
- } while((byte & 1) || (byte & ~((1<<6)|(1<<0))) == 0);
+ } while ((byte & 1) || (byte & ~((1<<6)|(1<<0))) == 0);
return loops?0:-1;
}
@@ -55,7 +55,7 @@ static inline int smbus_wait_until_blk_done(unsigned smbus_io_base)
if (--loops == 0)
break;
byte = inb(smbus_io_base + SMBHSTSTAT);
- } while((byte&(1<<7)) == 0);
+ } while ((byte&(1<<7)) == 0);
return loops?0:-1;
}
diff --git a/src/southbridge/intel/i82801ex/watchdog.c b/src/southbridge/intel/i82801ex/watchdog.c
index 28e1f5e..6aba270 100644
--- a/src/southbridge/intel/i82801ex/watchdog.c
+++ b/src/southbridge/intel/i82801ex/watchdog.c
@@ -6,23 +6,23 @@
void watchdog_off(void)
{
- device_t dev;
- unsigned long value,base;
+ device_t dev;
+ unsigned long value,base;
/* turn off the ICH5 watchdog */
- dev = dev_find_slot(0, PCI_DEVFN(0x1f,0));
- /* Enable I/O space */
- value = pci_read_config16(dev, 0x04);
- value |= (1 << 10);
- pci_write_config16(dev, 0x04, value);
- /* Get TCO base */
- base = (pci_read_config32(dev, 0x40) & 0x0fffe) + 0x60;
- /* Disable the watchdog timer */
- value = inw(base + 0x08);
- value |= 1 << 11;
- outw(value, base + 0x08);
- /* Clear TCO timeout status */
- outw(0x0008, base + 0x04);
- outw(0x0002, base + 0x06);
- printk(BIOS_DEBUG, "Watchdog ICH5 disabled\n");
+ dev = dev_find_slot(0, PCI_DEVFN(0x1f,0));
+ /* Enable I/O space */
+ value = pci_read_config16(dev, 0x04);
+ value |= (1 << 10);
+ pci_write_config16(dev, 0x04, value);
+ /* Get TCO base */
+ base = (pci_read_config32(dev, 0x40) & 0x0fffe) + 0x60;
+ /* Disable the watchdog timer */
+ value = inw(base + 0x08);
+ value |= 1 << 11;
+ outw(value, base + 0x08);
+ /* Clear TCO timeout status */
+ outw(0x0008, base + 0x04);
+ outw(0x0002, base + 0x06);
+ printk(BIOS_DEBUG, "Watchdog ICH5 disabled\n");
}
diff --git a/src/southbridge/intel/i82801gx/azalia.c b/src/southbridge/intel/i82801gx/azalia.c
index d28154c..b13d809 100644
--- a/src/southbridge/intel/i82801gx/azalia.c
+++ b/src/southbridge/intel/i82801gx/azalia.c
@@ -117,7 +117,7 @@ static int wait_for_ready(u8 *base)
int timeout = 50;
- while(timeout--) {
+ while (timeout--) {
u32 reg32 = read32(base + HDA_ICII_REG);
if (!(reg32 & HDA_ICII_BUSY))
return 0;
@@ -146,7 +146,7 @@ static int wait_for_valid(u8 *base)
* same duration */
int timeout = 50;
- while(timeout--) {
+ while (timeout--) {
reg32 = read32(base + HDA_ICII_REG);
if ((reg32 & (HDA_ICII_VALID | HDA_ICII_BUSY)) ==
HDA_ICII_VALID)
diff --git a/src/southbridge/intel/i82801gx/bootblock.c b/src/southbridge/intel/i82801gx/bootblock.c
index 50268b6..c9c19a3 100644
--- a/src/southbridge/intel/i82801gx/bootblock.c
+++ b/src/southbridge/intel/i82801gx/bootblock.c
@@ -30,22 +30,22 @@ static void store_initial_timestamp(void)
static void enable_spi_prefetch(void)
{
- u8 reg8;
- pci_devfn_t dev;
+ u8 reg8;
+ pci_devfn_t dev;
- dev = PCI_DEV(0, 0x1f, 0);
+ dev = PCI_DEV(0, 0x1f, 0);
- reg8 = pci_read_config8(dev, 0xdc);
- reg8 &= ~(3 << 2);
- reg8 |= (2 << 2); /* Prefetching and Caching Enabled */
- pci_write_config8(dev, 0xdc, reg8);
+ reg8 = pci_read_config8(dev, 0xdc);
+ reg8 &= ~(3 << 2);
+ reg8 |= (2 << 2); /* Prefetching and Caching Enabled */
+ pci_write_config8(dev, 0xdc, reg8);
}
static void bootblock_southbridge_init(void)
{
store_initial_timestamp();
- enable_spi_prefetch();
+ enable_spi_prefetch();
/* Enable RCBA */
pci_write_config32(PCI_DEV(0, 0x1f, 0), RCBA, (uintptr_t)DEFAULT_RCBA | 1);
diff --git a/src/southbridge/intel/i82801gx/lpc.c b/src/southbridge/intel/i82801gx/lpc.c
index 03df1a3..280e207 100644
--- a/src/southbridge/intel/i82801gx/lpc.c
+++ b/src/southbridge/intel/i82801gx/lpc.c
@@ -108,7 +108,7 @@ static void i82801gx_pirq_init(device_t dev)
* I am not so sure anymore he was right.
*/
- for(irq_dev = all_devices; irq_dev; irq_dev = irq_dev->next) {
+ for (irq_dev = all_devices; irq_dev; irq_dev = irq_dev->next) {
u8 int_pin=0, int_line=0;
if (!irq_dev->enabled || irq_dev->path.type != DEVICE_PATH_PCI)
diff --git a/src/southbridge/intel/i82801gx/reset.c b/src/southbridge/intel/i82801gx/reset.c
index 39c4f31..97b8225 100644
--- a/src/southbridge/intel/i82801gx/reset.c
+++ b/src/southbridge/intel/i82801gx/reset.c
@@ -19,7 +19,7 @@
void soft_reset(void)
{
- outb(0x04, 0xcf9);
+ outb(0x04, 0xcf9);
}
#if 0
@@ -32,6 +32,6 @@ void hard_reset(void)
void hard_reset(void)
{
- outb(0x02, 0xcf9);
- outb(0x06, 0xcf9);
+ outb(0x02, 0xcf9);
+ outb(0x06, 0xcf9);
}
diff --git a/src/southbridge/intel/i82801gx/smbus.c b/src/southbridge/intel/i82801gx/smbus.c
index 913f68f..e6aa018 100644
--- a/src/southbridge/intel/i82801gx/smbus.c
+++ b/src/southbridge/intel/i82801gx/smbus.c
@@ -123,7 +123,7 @@ static int do_smbus_block_write(unsigned smbus_base, unsigned device,
outb((inb(smbus_base + SMBHSTCTL) | 0x40),
smbus_base + SMBHSTCTL);
- while(!(inb(smbus_base + SMBHSTSTAT) & 1));
+ while (!(inb(smbus_base + SMBHSTSTAT) & 1));
/* Poll for transaction completion */
do {
status = inb(smbus_base + SMBHSTSTAT);
@@ -136,7 +136,7 @@ static int do_smbus_block_write(unsigned smbus_base, unsigned device,
outb(*buf++, smbus_base + SMBBLKDAT);
outb(status, smbus_base + SMBHSTSTAT);
}
- } while(status & 0x01);
+ } while (status & 0x01);
return 0;
}
@@ -180,7 +180,7 @@ static int do_smbus_block_read(unsigned smbus_base, unsigned device,
outb((inb(smbus_base + SMBHSTCTL) | 0x40),
smbus_base + SMBHSTCTL);
- while(!(inb(smbus_base + SMBHSTSTAT) & 1));
+ while (!(inb(smbus_base + SMBHSTSTAT) & 1));
/* Poll for transaction completion */
do {
status = inb(smbus_base + SMBHSTSTAT);
@@ -200,7 +200,7 @@ static int do_smbus_block_read(unsigned smbus_base, unsigned device,
smbus_base + SMBHSTCTL);
}
}
- } while(status & 0x01);
+ } while (status & 0x01);
return bytes_read;
}
diff --git a/src/southbridge/intel/i82801gx/smihandler.c b/src/southbridge/intel/i82801gx/smihandler.c
index e76087c..d3867a5 100644
--- a/src/southbridge/intel/i82801gx/smihandler.c
+++ b/src/southbridge/intel/i82801gx/smihandler.c
@@ -269,37 +269,37 @@ void southbridge_smi_set_eos(void)
static void busmaster_disable_on_bus(int bus)
{
- int slot, func;
- unsigned int val;
- unsigned char hdr;
-
- for (slot = 0; slot < 0x20; slot++) {
- for (func = 0; func < 8; func++) {
- u32 reg32;
- device_t dev = PCI_DEV(bus, slot, func);
-
- val = pci_read_config32(dev, PCI_VENDOR_ID);
-
- if (val == 0xffffffff || val == 0x00000000 ||
- val == 0x0000ffff || val == 0xffff0000)
- continue;
-
- /* Disable Bus Mastering for this one device */
- reg32 = pci_read_config32(dev, PCI_COMMAND);
- reg32 &= ~PCI_COMMAND_MASTER;
- pci_write_config32(dev, PCI_COMMAND, reg32);
-
- /* If this is a bridge, then follow it. */
- hdr = pci_read_config8(dev, PCI_HEADER_TYPE);
- hdr &= 0x7f;
- if (hdr == PCI_HEADER_TYPE_BRIDGE ||
- hdr == PCI_HEADER_TYPE_CARDBUS) {
- unsigned int buses;
- buses = pci_read_config32(dev, PCI_PRIMARY_BUS);
- busmaster_disable_on_bus((buses >> 8) & 0xff);
- }
- }
- }
+ int slot, func;
+ unsigned int val;
+ unsigned char hdr;
+
+ for (slot = 0; slot < 0x20; slot++) {
+ for (func = 0; func < 8; func++) {
+ u32 reg32;
+ device_t dev = PCI_DEV(bus, slot, func);
+
+ val = pci_read_config32(dev, PCI_VENDOR_ID);
+
+ if (val == 0xffffffff || val == 0x00000000 ||
+ val == 0x0000ffff || val == 0xffff0000)
+ continue;
+
+ /* Disable Bus Mastering for this one device */
+ reg32 = pci_read_config32(dev, PCI_COMMAND);
+ reg32 &= ~PCI_COMMAND_MASTER;
+ pci_write_config32(dev, PCI_COMMAND, reg32);
+
+ /* If this is a bridge, then follow it. */
+ hdr = pci_read_config8(dev, PCI_HEADER_TYPE);
+ hdr &= 0x7f;
+ if (hdr == PCI_HEADER_TYPE_BRIDGE ||
+ hdr == PCI_HEADER_TYPE_CARDBUS) {
+ unsigned int buses;
+ buses = pci_read_config32(dev, PCI_PRIMARY_BUS);
+ busmaster_disable_on_bus((buses >> 8) & 0xff);
+ }
+ }
+ }
}
@@ -673,7 +673,7 @@ void southbridge_smi_handler(unsigned int node, smm_state_save_area_t *state_sav
}
}
- if(dump) {
+ if (dump) {
dump_smi_status(smi_sts);
}
diff --git a/src/southbridge/intel/i82801ix/bootblock.c b/src/southbridge/intel/i82801ix/bootblock.c
index e222368..6252712 100644
--- a/src/southbridge/intel/i82801ix/bootblock.c
+++ b/src/southbridge/intel/i82801ix/bootblock.c
@@ -17,18 +17,18 @@
static void enable_spi_prefetch(void)
{
- u8 reg8;
- pci_devfn_t dev;
+ u8 reg8;
+ pci_devfn_t dev;
- dev = PCI_DEV(0, 0x1f, 0);
+ dev = PCI_DEV(0, 0x1f, 0);
- reg8 = pci_read_config8(dev, 0xdc);
- reg8 &= ~(3 << 2);
- reg8 |= (2 << 2); /* Prefetching and Caching Enabled */
- pci_write_config8(dev, 0xdc, reg8);
+ reg8 = pci_read_config8(dev, 0xdc);
+ reg8 &= ~(3 << 2);
+ reg8 |= (2 << 2); /* Prefetching and Caching Enabled */
+ pci_write_config8(dev, 0xdc, reg8);
}
static void bootblock_southbridge_init(void)
{
- enable_spi_prefetch();
+ enable_spi_prefetch();
}
diff --git a/src/southbridge/intel/i82801ix/hdaudio.c b/src/southbridge/intel/i82801ix/hdaudio.c
index 4848b94..c3602c4 100644
--- a/src/southbridge/intel/i82801ix/hdaudio.c
+++ b/src/southbridge/intel/i82801ix/hdaudio.c
@@ -118,7 +118,7 @@ static int wait_for_ready(u8 *base)
int timeout = 50;
- while(timeout--) {
+ while (timeout--) {
u32 reg32 = read32(base + HDA_ICII_REG);
if (!(reg32 & HDA_ICII_BUSY))
return 0;
@@ -147,7 +147,7 @@ static int wait_for_valid(u8 *base)
* same duration */
int timeout = 50;
- while(timeout--) {
+ while (timeout--) {
reg32 = read32(base + HDA_ICII_REG);
if ((reg32 & (HDA_ICII_VALID | HDA_ICII_BUSY)) ==
HDA_ICII_VALID)
diff --git a/src/southbridge/intel/i82801ix/lpc.c b/src/southbridge/intel/i82801ix/lpc.c
index 4415f44..e095ad8 100644
--- a/src/southbridge/intel/i82801ix/lpc.c
+++ b/src/southbridge/intel/i82801ix/lpc.c
@@ -110,7 +110,7 @@ static void i82801ix_pirq_init(device_t dev)
* I am not so sure anymore he was right.
*/
- for(irq_dev = all_devices; irq_dev; irq_dev = irq_dev->next) {
+ for (irq_dev = all_devices; irq_dev; irq_dev = irq_dev->next) {
u8 int_pin=0, int_line=0;
if (!irq_dev->enabled || irq_dev->path.type != DEVICE_PATH_PCI)
diff --git a/src/southbridge/intel/i82801ix/smihandler.c b/src/southbridge/intel/i82801ix/smihandler.c
index 5f1a44f..7ad00ed 100644
--- a/src/southbridge/intel/i82801ix/smihandler.c
+++ b/src/southbridge/intel/i82801ix/smihandler.c
@@ -518,7 +518,7 @@ void southbridge_smi_handler(unsigned int node, smm_state_save_area_t *state_sav
}
}
- if(dump) {
+ if (dump) {
dump_smi_status(smi_sts);
}
diff --git a/src/southbridge/intel/i82870/ioapic.c b/src/southbridge/intel/i82870/ioapic.c
index 6a0f0d2..a02a2af 100644
--- a/src/southbridge/intel/i82870/ioapic.c
+++ b/src/southbridge/intel/i82870/ioapic.c
@@ -11,11 +11,10 @@ static int num_p64h2_ioapics = 0;
static void p64h2_ioapic_enable(device_t dev)
{
- /* We have to enable MEM and Bus Master for IOAPIC */
- uint16_t command = PCI_COMMAND_SERR | PCI_COMMAND_PARITY | PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY;
+ /* We have to enable MEM and Bus Master for IOAPIC */
+ uint16_t command = PCI_COMMAND_SERR | PCI_COMMAND_PARITY | PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY;
-
- pci_write_config16(dev, PCI_COMMAND, command);
+ pci_write_config16(dev, PCI_COMMAND, command);
}
/**
@@ -29,70 +28,70 @@ static void p64h2_ioapic_enable(device_t dev)
*/
static void p64h2_ioapic_init(device_t dev)
{
- uint32_t memoryBase;
- int apic_index, apic_id;
+ uint32_t memoryBase;
+ int apic_index, apic_id;
- volatile uint32_t* pIndexRegister; /* io apic io memory space command address */
- volatile uint32_t* pWindowRegister; /* io apic io memory space data address */
+ volatile uint32_t* pIndexRegister; /* io apic io memory space command address */
+ volatile uint32_t* pWindowRegister; /* io apic io memory space data address */
- apic_index = num_p64h2_ioapics;
- num_p64h2_ioapics++;
+ apic_index = num_p64h2_ioapics;
+ num_p64h2_ioapics++;
- // A note on IOAPIC addresses:
- // 0 and 1 are used for the local APICs of the dual virtual
- // (hyper-threaded) CPUs of physical CPU 0 (devicetree.cb).
- // 6 and 7 are used for the local APICs of the dual virtual
- // (hyper-threaded) CPUs of physical CPU 1 (devicetree.cb).
- // 2 is used for the IOAPIC in the 82801 southbridge (hard-coded in i82801xx_lpc.c)
+ // A note on IOAPIC addresses:
+ // 0 and 1 are used for the local APICs of the dual virtual
+ // (hyper-threaded) CPUs of physical CPU 0 (devicetree.cb).
+ // 6 and 7 are used for the local APICs of the dual virtual
+ // (hyper-threaded) CPUs of physical CPU 1 (devicetree.cb).
+ // 2 is used for the IOAPIC in the 82801 southbridge (hard-coded in i82801xx_lpc.c)
- // Map APIC index into APIC ID
- // IDs 3, 4, 5, and 8+ are available (see above note)
+ // Map APIC index into APIC ID
+ // IDs 3, 4, 5, and 8+ are available (see above note)
- if (apic_index < 3)
- apic_id = apic_index + 3;
- else
- apic_id = apic_index + 5;
+ if (apic_index < 3)
+ apic_id = apic_index + 3;
+ else
+ apic_id = apic_index + 5;
- ASSERT(apic_id < 16); // ID is only 4 bits
+ ASSERT(apic_id < 16); // ID is only 4 bits
- // Read the MBAR address for setting up the IOAPIC in memory space
- // NOTE: this address was assigned during enumeration of the bus
+ // Read the MBAR address for setting up the IOAPIC in memory space
+ // NOTE: this address was assigned during enumeration of the bus
- memoryBase = pci_read_config32(dev, PCI_BASE_ADDRESS_0);
- pIndexRegister = (volatile uint32_t*) memoryBase;
- pWindowRegister = (volatile uint32_t*)(memoryBase + 0x10);
+ memoryBase = pci_read_config32(dev, PCI_BASE_ADDRESS_0);
+ pIndexRegister = (volatile uint32_t*) memoryBase;
+ pWindowRegister = (volatile uint32_t*)(memoryBase + 0x10);
- printk(BIOS_DEBUG, "IOAPIC %d at %02x:%02x.%01x MBAR = %p DataAddr = %p\n",
- apic_id, dev->bus->secondary, PCI_SLOT(dev->path.pci.devfn),
- PCI_FUNC(dev->path.pci.devfn), pIndexRegister, pWindowRegister);
+ printk(BIOS_DEBUG, "IOAPIC %d at %02x:%02x.%01x MBAR = %p DataAddr = %p\n",
+ apic_id, dev->bus->secondary, PCI_SLOT(dev->path.pci.devfn),
+ PCI_FUNC(dev->path.pci.devfn), pIndexRegister, pWindowRegister);
- apic_id <<= 24; // Convert ID to bitmask
+ apic_id <<= 24; // Convert ID to bitmask
- *pIndexRegister = 0; // Select APIC ID register
- *pWindowRegister = (*pWindowRegister & ~(0xF<<24)) | apic_id; // Set the ID
+ *pIndexRegister = 0; // Select APIC ID register
+ *pWindowRegister = (*pWindowRegister & ~(0xF<<24)) | apic_id; // Set the ID
- if ((*pWindowRegister & (0xF<<24)) != apic_id)
- die("p64h2_ioapic_init failed");
+ if ((*pWindowRegister & (0xF<<24)) != apic_id)
+ die("p64h2_ioapic_init failed");
- *pIndexRegister = 3; // Select Boot Configuration register
- *pWindowRegister |= 1; // Use Processor System Bus to deliver interrupts
+ *pIndexRegister = 3; // Select Boot Configuration register
+ *pWindowRegister |= 1; // Use Processor System Bus to deliver interrupts
- if (!(*pWindowRegister & 1))
- die("p64h2_ioapic_init failed");
+ if (!(*pWindowRegister & 1))
+ die("p64h2_ioapic_init failed");
}
static struct device_operations ioapic_ops = {
- .read_resources = pci_dev_read_resources,
- .set_resources = pci_dev_set_resources,
- .enable_resources = pci_dev_enable_resources,
- .init = p64h2_ioapic_init,
- .scan_bus = 0,
- .enable = p64h2_ioapic_enable,
+ .read_resources = pci_dev_read_resources,
+ .set_resources = pci_dev_set_resources,
+ .enable_resources = pci_dev_enable_resources,
+ .init = p64h2_ioapic_init,
+ .scan_bus = 0,
+ .enable = p64h2_ioapic_enable,
};
static const struct pci_driver ioapic_driver __pci_driver = {
- .ops = &ioapic_ops,
- .vendor = PCI_VENDOR_ID_INTEL,
- .device = PCI_DEVICE_ID_INTEL_82870_1E0,
+ .ops = &ioapic_ops,
+ .vendor = PCI_VENDOR_ID_INTEL,
+ .device = PCI_DEVICE_ID_INTEL_82870_1E0,
};
diff --git a/src/southbridge/intel/i82870/pci_parity.c b/src/southbridge/intel/i82870/pci_parity.c
index 71d2c53..b886c52 100644
--- a/src/southbridge/intel/i82870/pci_parity.c
+++ b/src/southbridge/intel/i82870/pci_parity.c
@@ -5,19 +5,19 @@
void p64h2_pci_parity_enable(void)
{
- uint8_t reg;
+ uint8_t reg;
- /* 2SERREN - SERR enable for PCI bridge secondary device */
- /* 2PEREN - Parity error for PCI bridge secondary device */
- pcibios_read_config_byte(1, ((29 << 3) + (0 << 0)), 0x3e, ®);
- reg |= ((1 << 1) + (1 << 0));
- pcibios_write_config_byte(1, ((29 << 3) + (0 << 0)), 0x3e, reg);
+ /* 2SERREN - SERR enable for PCI bridge secondary device */
+ /* 2PEREN - Parity error for PCI bridge secondary device */
+ pcibios_read_config_byte(1, ((29 << 3) + (0 << 0)), 0x3e, ®);
+ reg |= ((1 << 1) + (1 << 0));
+ pcibios_write_config_byte(1, ((29 << 3) + (0 << 0)), 0x3e, reg);
- /* 2SERREN - SERR enable for PCI bridge secondary device */
- /* 2PEREN - Parity error for PCI bridge secondary device */
- pcibios_read_config_byte(1, ((31 << 3) + (0 << 0)), 0x3e, ®);
- reg |= ((1 << 1) + (1 << 0));
- pcibios_write_config_byte(1, ((31 << 3) + (0 << 0)), 0x3e, reg);
+ /* 2SERREN - SERR enable for PCI bridge secondary device */
+ /* 2PEREN - Parity error for PCI bridge secondary device */
+ pcibios_read_config_byte(1, ((31 << 3) + (0 << 0)), 0x3e, ®);
+ reg |= ((1 << 1) + (1 << 0));
+ pcibios_write_config_byte(1, ((31 << 3) + (0 << 0)), 0x3e, reg);
- return;
+ return;
}
diff --git a/src/southbridge/intel/i82870/pcibridge.c b/src/southbridge/intel/i82870/pcibridge.c
index b46b338..e8d890a 100644
--- a/src/southbridge/intel/i82870/pcibridge.c
+++ b/src/southbridge/intel/i82870/pcibridge.c
@@ -23,16 +23,16 @@ static void p64h2_pcix_init(device_t dev)
}
static struct device_operations pcix_ops = {
- .read_resources = pci_bus_read_resources,
- .set_resources = pci_dev_set_resources,
- .enable_resources = pci_bus_enable_resources,
- .init = p64h2_pcix_init,
- .scan_bus = pci_scan_bridge,
+ .read_resources = pci_bus_read_resources,
+ .set_resources = pci_dev_set_resources,
+ .enable_resources = pci_bus_enable_resources,
+ .init = p64h2_pcix_init,
+ .scan_bus = pci_scan_bridge,
.reset_bus = pci_bus_reset,
};
static const struct pci_driver pcix_driver __pci_driver = {
- .ops = &pcix_ops,
- .vendor = PCI_VENDOR_ID_INTEL,
- .device = PCI_DEVICE_ID_INTEL_82870_1F0,
+ .ops = &pcix_ops,
+ .vendor = PCI_VENDOR_ID_INTEL,
+ .device = PCI_DEVICE_ID_INTEL_82870_1F0,
};
diff --git a/src/southbridge/intel/ibexpeak/azalia.c b/src/southbridge/intel/ibexpeak/azalia.c
index dfcbcb6..d9f635a 100644
--- a/src/southbridge/intel/ibexpeak/azalia.c
+++ b/src/southbridge/intel/ibexpeak/azalia.c
@@ -115,7 +115,7 @@ static int wait_for_ready(u8 *base)
int timeout = 1000;
- while(timeout--) {
+ while (timeout--) {
u32 reg32 = read32(base + HDA_ICII_REG);
if (!(reg32 & HDA_ICII_BUSY))
return 0;
@@ -143,7 +143,7 @@ static int wait_for_valid(u8 *base)
/* Use a 1msec timeout */
int timeout = 1000;
- while(timeout--) {
+ while (timeout--) {
reg32 = read32(base + HDA_ICII_REG);
if ((reg32 & (HDA_ICII_VALID | HDA_ICII_BUSY)) ==
HDA_ICII_VALID)
diff --git a/src/southbridge/intel/ibexpeak/lpc.c b/src/southbridge/intel/ibexpeak/lpc.c
index 88ec851..23b1925 100644
--- a/src/southbridge/intel/ibexpeak/lpc.c
+++ b/src/southbridge/intel/ibexpeak/lpc.c
@@ -120,7 +120,7 @@ static void pch_pirq_init(device_t dev)
pci_write_config8(dev, PIRQG_ROUT, pirq_routing);
pci_write_config8(dev, PIRQH_ROUT, pirq_routing);
- for(irq_dev = all_devices; irq_dev; irq_dev = irq_dev->next) {
+ for (irq_dev = all_devices; irq_dev; irq_dev = irq_dev->next) {
u8 int_pin=0;
if (!irq_dev->enabled || irq_dev->path.type != DEVICE_PATH_PCI)
diff --git a/src/southbridge/intel/ibexpeak/sata.c b/src/southbridge/intel/ibexpeak/sata.c
index e7681fb..19ef098 100644
--- a/src/southbridge/intel/ibexpeak/sata.c
+++ b/src/southbridge/intel/ibexpeak/sata.c
@@ -126,7 +126,7 @@ static void sata_init(struct device *dev)
reg32 &= ~0x00000005;
write32(abar + 0x28, reg32);
} else {
- /* IDE */
+ /* IDE */
printk(BIOS_DEBUG, "SATA: Controller in plain mode.\n");
/* No AHCI: clear AHCI base */
diff --git a/src/southbridge/intel/ibexpeak/smbus.h b/src/southbridge/intel/ibexpeak/smbus.h
index aeac573..0815bf4 100644
--- a/src/southbridge/intel/ibexpeak/smbus.h
+++ b/src/southbridge/intel/ibexpeak/smbus.h
@@ -171,7 +171,7 @@ static int do_smbus_block_write(unsigned smbus_base, unsigned device,
outb((inb(smbus_base + SMBHSTCTL) | 0x40),
smbus_base + SMBHSTCTL);
- while(!(inb(smbus_base + SMBHSTSTAT) & 1));
+ while (!(inb(smbus_base + SMBHSTSTAT) & 1));
/* Poll for transaction completion */
do {
status = inb(smbus_base + SMBHSTSTAT);
@@ -184,7 +184,7 @@ static int do_smbus_block_write(unsigned smbus_base, unsigned device,
outb(*buf++, smbus_base + SMBBLKDAT);
outb(status, smbus_base + SMBHSTSTAT);
}
- } while(status & 0x01);
+ } while (status & 0x01);
return 0;
}
@@ -214,7 +214,7 @@ static int do_smbus_block_read(unsigned smbus_base, unsigned device,
outb((inb(smbus_base + SMBHSTCTL) | 0x40),
smbus_base + SMBHSTCTL);
- while(!(inb(smbus_base + SMBHSTSTAT) & 1));
+ while (!(inb(smbus_base + SMBHSTSTAT) & 1));
/* Poll for transaction completion */
do {
status = inb(smbus_base + SMBHSTSTAT);
@@ -234,7 +234,7 @@ static int do_smbus_block_read(unsigned smbus_base, unsigned device,
smbus_base + SMBHSTCTL);
}
}
- } while(status & 0x01);
+ } while (status & 0x01);
return bytes_read;
}
diff --git a/src/southbridge/intel/ibexpeak/smihandler.c b/src/southbridge/intel/ibexpeak/smihandler.c
index d11d531..0ad7e65 100644
--- a/src/southbridge/intel/ibexpeak/smihandler.c
+++ b/src/southbridge/intel/ibexpeak/smihandler.c
@@ -273,37 +273,37 @@ void southbridge_smi_set_eos(void)
static void busmaster_disable_on_bus(int bus)
{
- int slot, func;
- unsigned int val;
- unsigned char hdr;
-
- for (slot = 0; slot < 0x20; slot++) {
- for (func = 0; func < 8; func++) {
- u32 reg32;
- device_t dev = PCI_DEV(bus, slot, func);
-
- val = pci_read_config32(dev, PCI_VENDOR_ID);
-
- if (val == 0xffffffff || val == 0x00000000 ||
- val == 0x0000ffff || val == 0xffff0000)
- continue;
-
- /* Disable Bus Mastering for this one device */
- reg32 = pci_read_config32(dev, PCI_COMMAND);
- reg32 &= ~PCI_COMMAND_MASTER;
- pci_write_config32(dev, PCI_COMMAND, reg32);
-
- /* If this is a bridge, then follow it. */
- hdr = pci_read_config8(dev, PCI_HEADER_TYPE);
- hdr &= 0x7f;
- if (hdr == PCI_HEADER_TYPE_BRIDGE ||
- hdr == PCI_HEADER_TYPE_CARDBUS) {
- unsigned int buses;
- buses = pci_read_config32(dev, PCI_PRIMARY_BUS);
- busmaster_disable_on_bus((buses >> 8) & 0xff);
- }
- }
- }
+ int slot, func;
+ unsigned int val;
+ unsigned char hdr;
+
+ for (slot = 0; slot < 0x20; slot++) {
+ for (func = 0; func < 8; func++) {
+ u32 reg32;
+ device_t dev = PCI_DEV(bus, slot, func);
+
+ val = pci_read_config32(dev, PCI_VENDOR_ID);
+
+ if (val == 0xffffffff || val == 0x00000000 ||
+ val == 0x0000ffff || val == 0xffff0000)
+ continue;
+
+ /* Disable Bus Mastering for this one device */
+ reg32 = pci_read_config32(dev, PCI_COMMAND);
+ reg32 &= ~PCI_COMMAND_MASTER;
+ pci_write_config32(dev, PCI_COMMAND, reg32);
+
+ /* If this is a bridge, then follow it. */
+ hdr = pci_read_config8(dev, PCI_HEADER_TYPE);
+ hdr &= 0x7f;
+ if (hdr == PCI_HEADER_TYPE_BRIDGE ||
+ hdr == PCI_HEADER_TYPE_CARDBUS) {
+ unsigned int buses;
+ buses = pci_read_config32(dev, PCI_PRIMARY_BUS);
+ busmaster_disable_on_bus((buses >> 8) & 0xff);
+ }
+ }
+ }
}
static void southbridge_gate_memory_reset_real(int offset,
@@ -849,7 +849,7 @@ void southbridge_smi_handler(void)
}
}
- if(dump) {
+ if (dump) {
dump_smi_status(smi_sts);
}
diff --git a/src/southbridge/intel/lynxpoint/hda_verb.c b/src/southbridge/intel/lynxpoint/hda_verb.c
index 96ab34e..a8a139c 100644
--- a/src/southbridge/intel/lynxpoint/hda_verb.c
+++ b/src/southbridge/intel/lynxpoint/hda_verb.c
@@ -94,7 +94,7 @@ static int hda_wait_for_ready(u8 *base)
int timeout = 50;
- while(timeout--) {
+ while (timeout--) {
u32 reg32 = read32(base + HDA_ICII_REG);
if (!(reg32 & HDA_ICII_BUSY))
return 0;
@@ -122,7 +122,7 @@ static int hda_wait_for_valid(u8 *base)
* same duration */
int timeout = 50;
- while(timeout--) {
+ while (timeout--) {
reg32 = read32(base + HDA_ICII_REG);
if ((reg32 & (HDA_ICII_VALID | HDA_ICII_BUSY)) ==
HDA_ICII_VALID)
diff --git a/src/southbridge/intel/lynxpoint/lpc.c b/src/southbridge/intel/lynxpoint/lpc.c
index 1d20bbb..f8ec94e 100644
--- a/src/southbridge/intel/lynxpoint/lpc.c
+++ b/src/southbridge/intel/lynxpoint/lpc.c
@@ -124,7 +124,7 @@ static void pch_pirq_init(device_t dev)
* I am not so sure anymore he was right.
*/
- for(irq_dev = all_devices; irq_dev; irq_dev = irq_dev->next) {
+ for (irq_dev = all_devices; irq_dev; irq_dev = irq_dev->next) {
u8 int_pin=0, int_line=0;
if (!irq_dev->enabled || irq_dev->path.type != DEVICE_PATH_PCI)
@@ -194,7 +194,7 @@ static void pch_power_options(device_t dev)
* If the option is not existent (Laptops), use Kconfig setting.
*/
get_option(&pwr_on, "power_on_after_fail");
- pwr_on = MAINBOARD_POWER_KEEP;
+ pwr_on = MAINBOARD_POWER_KEEP;
reg16 = pci_read_config16(dev, GEN_PMCON_3);
reg16 &= 0xfffe;
diff --git a/src/southbridge/intel/lynxpoint/me_9.x.c b/src/southbridge/intel/lynxpoint/me_9.x.c
index 43e5289..355db4b 100644
--- a/src/southbridge/intel/lynxpoint/me_9.x.c
+++ b/src/southbridge/intel/lynxpoint/me_9.x.c
@@ -485,7 +485,7 @@ static int mkhi_get_fwcaps(mbp_mefwcaps *cap)
&cap_msg, sizeof(cap_msg)) < 0) {
printk(BIOS_ERR, "ME: GET FWCAPS message failed\n");
return -1;
- }
+ }
*cap = cap_msg.caps_sku;
return 0;
}
@@ -650,7 +650,7 @@ static int me_icc_set_clock_enables(u32 mask)
if (mei_sendrecv_icc(&icc, &clk, sizeof(clk), NULL, 0) < 0) {
printk(BIOS_ERR, "ME: ICC SET CLOCK ENABLES message failed\n");
return -1;
- } else {
+ } else {
printk(BIOS_INFO, "ME: ICC SET CLOCK ENABLES 0x%08x\n", mask);
}
diff --git a/src/southbridge/intel/lynxpoint/reset.c b/src/southbridge/intel/lynxpoint/reset.c
index daabbbc..804fb81 100644
--- a/src/southbridge/intel/lynxpoint/reset.c
+++ b/src/southbridge/intel/lynxpoint/reset.c
@@ -19,10 +19,10 @@
void soft_reset(void)
{
- outb(0x04, 0xcf9);
+ outb(0x04, 0xcf9);
}
void hard_reset(void)
{
- outb(0x06, 0xcf9);
+ outb(0x06, 0xcf9);
}
diff --git a/src/southbridge/intel/lynxpoint/smihandler.c b/src/southbridge/intel/lynxpoint/smihandler.c
index 4f0db1b..0102308 100644
--- a/src/southbridge/intel/lynxpoint/smihandler.c
+++ b/src/southbridge/intel/lynxpoint/smihandler.c
@@ -68,37 +68,37 @@ void southbridge_smi_set_eos(void)
static void busmaster_disable_on_bus(int bus)
{
- int slot, func;
- unsigned int val;
- unsigned char hdr;
-
- for (slot = 0; slot < 0x20; slot++) {
- for (func = 0; func < 8; func++) {
- u32 reg32;
- device_t dev = PCI_DEV(bus, slot, func);
-
- val = pci_read_config32(dev, PCI_VENDOR_ID);
-
- if (val == 0xffffffff || val == 0x00000000 ||
- val == 0x0000ffff || val == 0xffff0000)
- continue;
-
- /* Disable Bus Mastering for this one device */
- reg32 = pci_read_config32(dev, PCI_COMMAND);
- reg32 &= ~PCI_COMMAND_MASTER;
- pci_write_config32(dev, PCI_COMMAND, reg32);
-
- /* If this is a bridge, then follow it. */
- hdr = pci_read_config8(dev, PCI_HEADER_TYPE);
- hdr &= 0x7f;
- if (hdr == PCI_HEADER_TYPE_BRIDGE ||
- hdr == PCI_HEADER_TYPE_CARDBUS) {
- unsigned int buses;
- buses = pci_read_config32(dev, PCI_PRIMARY_BUS);
- busmaster_disable_on_bus((buses >> 8) & 0xff);
- }
- }
- }
+ int slot, func;
+ unsigned int val;
+ unsigned char hdr;
+
+ for (slot = 0; slot < 0x20; slot++) {
+ for (func = 0; func < 8; func++) {
+ u32 reg32;
+ device_t dev = PCI_DEV(bus, slot, func);
+
+ val = pci_read_config32(dev, PCI_VENDOR_ID);
+
+ if (val == 0xffffffff || val == 0x00000000 ||
+ val == 0x0000ffff || val == 0xffff0000)
+ continue;
+
+ /* Disable Bus Mastering for this one device */
+ reg32 = pci_read_config32(dev, PCI_COMMAND);
+ reg32 &= ~PCI_COMMAND_MASTER;
+ pci_write_config32(dev, PCI_COMMAND, reg32);
+
+ /* If this is a bridge, then follow it. */
+ hdr = pci_read_config8(dev, PCI_HEADER_TYPE);
+ hdr &= 0x7f;
+ if (hdr == PCI_HEADER_TYPE_BRIDGE ||
+ hdr == PCI_HEADER_TYPE_CARDBUS) {
+ unsigned int buses;
+ buses = pci_read_config32(dev, PCI_PRIMARY_BUS);
+ busmaster_disable_on_bus((buses >> 8) & 0xff);
+ }
+ }
+ }
}
@@ -459,7 +459,7 @@ static void southbridge_smi_monitor(void)
printk(BIOS_DEBUG, " trapped io address = 0x%x\n",
trap_cycle & 0xfffc);
for (i=0; i < 4; i++)
- if(IOTRAP(i)) printk(BIOS_DEBUG, " TRAP = %d\n", i);
+ if (IOTRAP(i)) printk(BIOS_DEBUG, " TRAP = %d\n", i);
printk(BIOS_DEBUG, " AHBE = %x\n", (trap_cycle >> 16) & 0xf);
printk(BIOS_DEBUG, " MASK = 0x%08x\n", mask);
printk(BIOS_DEBUG, " read/write: %s\n",
diff --git a/src/southbridge/nvidia/ck804/early_setup_car.c b/src/southbridge/nvidia/ck804/early_setup_car.c
index ae8b6a0..6b21a3f 100644
--- a/src/southbridge/nvidia/ck804/early_setup_car.c
+++ b/src/southbridge/nvidia/ck804/early_setup_car.c
@@ -377,6 +377,6 @@ void soft_reset(void)
void enable_fid_change_on_sb(unsigned sbbusn, unsigned sbdn)
{
- /* The default value for CK804 is good. */
- /* Set VFSMAF (VID/FID System Management Action Field) to 2. */
+ /* The default value for CK804 is good. */
+ /* Set VFSMAF (VID/FID System Management Action Field) to 2. */
}
diff --git a/src/southbridge/nvidia/mcp55/early_setup_car.c b/src/southbridge/nvidia/mcp55/early_setup_car.c
index 9af2bbc..619ba4c 100644
--- a/src/southbridge/nvidia/mcp55/early_setup_car.c
+++ b/src/southbridge/nvidia/mcp55/early_setup_car.c
@@ -381,7 +381,7 @@ static int mcp55_early_setup_x(void)
device_t dev;
dev = PCI_DEV(busnx, devnx, 0);
id = pci_read_config32(dev, PCI_VENDOR_ID);
- if(id == 0x036910de) {
+ if (id == 0x036910de) {
busn[mcp55_num] = busnx;
devn[mcp55_num] = devnx;
diff --git a/src/southbridge/nvidia/mcp55/nic.c b/src/southbridge/nvidia/mcp55/nic.c
index 2df096a..2474ef3 100644
--- a/src/southbridge/nvidia/mcp55/nic.c
+++ b/src/southbridge/nvidia/mcp55/nic.c
@@ -127,26 +127,26 @@ static void nic_init(struct device *dev)
struct device *dev_eeprom;
dev_eeprom = dev_find_slot_on_smbus(conf->mac_eeprom_smbus, conf->mac_eeprom_addr);
- if(dev_eeprom) {
+ if (dev_eeprom) {
// if that is valid we will use that
unsigned char dat[6];
int status;
int i;
- for(i=0;i<6;i++) {
+ for (i=0;i<6;i++) {
status = smbus_read_byte(dev_eeprom, i);
- if(status < 0) break;
+ if (status < 0) break;
dat[i] = status & 0xff;
}
- if(status >= 0) {
+ if (status >= 0) {
mac_l = 0;
- for(i=3;i>=0;i--) {
+ for (i=3;i>=0;i--) {
mac_l <<= 8;
mac_l += dat[i];
}
- if(mac_l != 0xffffffff) {
+ if (mac_l != 0xffffffff) {
mac_l += nic_index;
mac_h = 0;
- for(i=5;i>=4;i--) {
+ for (i=5;i>=4;i--) {
mac_h <<= 8;
mac_h += dat[i];
}
@@ -156,7 +156,7 @@ static void nic_init(struct device *dev)
}
}
// if that is invalid we will read that from romstrap
- if(!eeprom_valid) {
+ if (!eeprom_valid) {
u32 *mac_pos;
mac_pos = (u32 *)0xffffffd0; // refer to romstrap.inc and romstrap.ld
mac_l = read32(mac_pos) + nic_index; // overflow?
diff --git a/src/southbridge/nvidia/mcp55/sata.c b/src/southbridge/nvidia/mcp55/sata.c
index fa761d2..4c2830e 100644
--- a/src/southbridge/nvidia/mcp55/sata.c
+++ b/src/southbridge/nvidia/mcp55/sata.c
@@ -35,7 +35,7 @@ static void sata_init(struct device *dev)
dword = pci_read_config32(dev, 0x50);
/* Ensure prefetch is disabled */
dword &= ~((1 << 15) | (1 << 13));
- if(conf) {
+ if (conf) {
if (conf->sata1_enable) {
/* Enable secondary SATA interface */
dword |= (1<<0);
diff --git a/src/southbridge/nvidia/mcp55/smbus.h b/src/southbridge/nvidia/mcp55/smbus.h
index 9db2117..8f2884a 100644
--- a/src/southbridge/nvidia/mcp55/smbus.h
+++ b/src/southbridge/nvidia/mcp55/smbus.h
@@ -48,7 +48,7 @@ static int smbus_wait_until_done(unsigned smbus_io_base)
if ( (val & 0xff) != 0) {
return 0;
}
- } while(--loops);
+ } while (--loops);
return -3;
}
static int do_smbus_recv_byte(unsigned smbus_io_base, unsigned device)
diff --git a/src/southbridge/ricoh/rl5c476/rl5c476.c b/src/southbridge/ricoh/rl5c476/rl5c476.c
index 083d064..8284ec8 100644
--- a/src/southbridge/ricoh/rl5c476/rl5c476.c
+++ b/src/southbridge/ricoh/rl5c476/rl5c476.c
@@ -166,7 +166,7 @@ static void rl5c476_read_resources(device_t dev)
/* For CF socket we need an extra memory window for
* the control structure of the CF itself
*/
- if( enable_cf_boot && (PCI_FUNC(dev->path.pci.devfn) == 1)){
+ if ( enable_cf_boot && (PCI_FUNC(dev->path.pci.devfn) == 1)){
/* fake index as it isn't in PCI config space */
resource = new_resource(dev, 1);
resource->flags |= IORESOURCE_MEM;
@@ -181,9 +181,9 @@ static void rl5c476_set_resources(device_t dev)
{
struct resource *resource;
printk(BIOS_DEBUG, "%s In set resources\n",dev_path(dev));
- if( enable_cf_boot && (PCI_FUNC(dev->path.pci.devfn) == 1)){
+ if ( enable_cf_boot && (PCI_FUNC(dev->path.pci.devfn) == 1)){
resource = find_resource(dev,1);
- if( !(resource->flags & IORESOURCE_STORED) ){
+ if ( !(resource->flags & IORESOURCE_STORED) ){
resource->flags |= IORESOURCE_STORED ;
printk(BIOS_DEBUG, "%s 1 ==> %llx\n", dev_path(dev), resource->base);
cf_base = resource->base;
diff --git a/src/southbridge/sis/sis966/aza.c b/src/southbridge/sis/sis966/aza.c
index dfd146d..9c05cb1 100644
--- a/src/southbridge/sis/sis966/aza.c
+++ b/src/southbridge/sis/sis966/aza.c
@@ -56,7 +56,7 @@ static int set_bits(void *port, u32 mask, u32 val)
udelay(100);
} while ((dword != val) && --count);
- if(!count) return -1;
+ if (!count) return -1;
udelay(500);
return 0;
@@ -98,9 +98,9 @@ static int codec_detect(u8 *base)
set_bits(base + 0x08, 1, 1);
- do{
+ do {
dword = read32(base + 0x08)&0x1;
- if(idx++>1000) { printk(BIOS_DEBUG, "controller reset fail !!!\n"); break;}
+ if (idx++>1000) { printk(BIOS_DEBUG, "controller reset fail !!!\n"); break;}
} while (dword !=1);
dword=send_verb(base,0x000F0000); // get codec VendorId and DeviceId
@@ -184,7 +184,7 @@ static u32 verb_data[] = {
static unsigned find_verb(u32 viddid, u32 **verb)
{
- if ((viddid == 0x10ec0883) || (viddid == 0x10ec0882) || (viddid == 0x10ec0880)) return 0;
+ if ((viddid == 0x10ec0883) || (viddid == 0x10ec0882) || (viddid == 0x10ec0880)) return 0;
*verb = (u32 *)verb_data;
return sizeof(verb_data)/sizeof(u32);
}
@@ -215,14 +215,14 @@ static void codec_init(u8 *base, int addr)
printk(BIOS_DEBUG, "codec viddid: %08x\n", dword);
verb_size = find_verb(dword, &verb);
- if(!verb_size) {
+ if (!verb_size) {
printk(BIOS_DEBUG, "No verb!\n");
return;
}
printk(BIOS_DEBUG, "verb_size: %d\n", verb_size);
/* 3 */
- for(i=0; i<verb_size; i++) {
+ for (i=0; i<verb_size; i++) {
send_verb(base,verb[i]);
}
printk(BIOS_DEBUG, "verb loaded!\n");
@@ -236,50 +236,50 @@ static void codecs_init(u8 *base, u32 codec_mask)
static void aza_init(struct device *dev)
{
- u8 *base;
- struct resource *res;
- u32 codec_mask;
+ u8 *base;
+ struct resource *res;
+ u32 codec_mask;
- printk(BIOS_DEBUG, "AZALIA_INIT:---------->\n");
+ printk(BIOS_DEBUG, "AZALIA_INIT:---------->\n");
//-------------- enable AZA (SiS7502) -------------------------
{
- u8 temp8;
- int i=0;
- while(SiS_SiS7502_init[i][0] != 0)
- {
- temp8 = pci_read_config8(dev, SiS_SiS7502_init[i][0]);
- temp8 &= SiS_SiS7502_init[i][1];
- temp8 |= SiS_SiS7502_init[i][2];
- pci_write_config8(dev, SiS_SiS7502_init[i][0], temp8);
- i++;
- };
+ u8 temp8;
+ int i=0;
+ while (SiS_SiS7502_init[i][0] != 0)
+ {
+ temp8 = pci_read_config8(dev, SiS_SiS7502_init[i][0]);
+ temp8 &= SiS_SiS7502_init[i][1];
+ temp8 |= SiS_SiS7502_init[i][2];
+ pci_write_config8(dev, SiS_SiS7502_init[i][0], temp8);
+ i++;
+ };
}
//-----------------------------------------------------------
- // put audio to D0 state
- pci_write_config8(dev, 0x54,0x00);
+ // put audio to D0 state
+ pci_write_config8(dev, 0x54,0x00);
#if DEBUG_AZA
{
- int i;
-
- printk(BIOS_DEBUG, "****** Azalia PCI config ******");
- printk(BIOS_DEBUG, "\n 03020100 07060504 0B0A0908 0F0E0D0C");
-
- for (i=0;i<0xff;i+=4){
- if ((i%16)==0){
- printk(BIOS_DEBUG, "\n%02x: ", i);
- }
- printk(BIOS_DEBUG, "%08x ", pci_read_config32(dev,i));
- }
- printk(BIOS_DEBUG, "\n");
+ int i;
+
+ printk(BIOS_DEBUG, "****** Azalia PCI config ******");
+ printk(BIOS_DEBUG, "\n 03020100 07060504 0B0A0908 0F0E0D0C");
+
+ for (i=0;i<0xff;i+=4){
+ if ((i%16)==0){
+ printk(BIOS_DEBUG, "\n%02x: ", i);
+ }
+ printk(BIOS_DEBUG, "%08x ", pci_read_config32(dev,i));
+ }
+ printk(BIOS_DEBUG, "\n");
}
#endif
res = find_resource(dev, 0x10);
- if(!res)
+ if (!res)
return;
base = res2mmio(res, 0, 0);
@@ -287,12 +287,12 @@ static void aza_init(struct device *dev)
codec_mask = codec_detect(base);
- if(codec_mask) {
+ if (codec_mask) {
printk(BIOS_DEBUG, "codec_mask = %02x\n", codec_mask);
codecs_init(base, codec_mask);
}
- printk(BIOS_DEBUG, "AZALIA_INIT:<----------\n");
+ printk(BIOS_DEBUG, "AZALIA_INIT:<----------\n");
}
static void lpci_set_subsystem(device_t dev, unsigned vendor, unsigned device)
diff --git a/src/southbridge/sis/sis966/early_setup_car.c b/src/southbridge/sis/sis966/early_setup_car.c
index b9ee592..ba6d8a3 100644
--- a/src/southbridge/sis/sis966/early_setup_car.c
+++ b/src/southbridge/sis/sis966/early_setup_car.c
@@ -29,7 +29,7 @@ void sis966_early_pcie_setup(unsigned busnx, unsigned devnx, unsigned anactrl_io
dword |= 0x3f0; // disable it at first
pci_write_config32(dev, 0xe4, dword);
- for(i=0; i<3; i++) {
+ for (i=0; i<3; i++) {
tgio_ctrl = inl(anactrl_io_base + 0xcc);
tgio_ctrl &= ~(3<<9);
tgio_ctrl |= (i<<9);
diff --git a/src/southbridge/sis/sis966/early_smbus.c b/src/southbridge/sis/sis966/early_smbus.c
index 15d4f4c..4a2b867 100644
--- a/src/southbridge/sis/sis966/early_smbus.c
+++ b/src/southbridge/sis/sis966/early_smbus.c
@@ -37,7 +37,7 @@ int smbus_wait_until_ready(unsigned smbus_io_base)
return 0;
}
outb(val,smbus_io_base + SMBHSTSTAT);
- } while(--loops);
+ } while (--loops);
return -2;
}
@@ -53,7 +53,7 @@ int smbus_wait_until_done(unsigned smbus_io_base)
if ( (val & 0xff) != 0x02) {
return 0;
}
- } while(--loops);
+ } while (--loops);
return -3;
}
@@ -135,11 +135,10 @@ static inline int do_smbus_read_byte(unsigned smbus_io_base, unsigned device, un
smbus_delay();
int i, j;
- for(i = 0;i < 0x1000; i++)
- {
- if (inb(smbus_io_base + 0x00) != 0x08)
- { smbus_delay();
- for(j=0;j<0xFFFF;j++);
+ for (i = 0;i < 0x1000; i++) {
+ if (inb(smbus_io_base + 0x00) != 0x08) {
+ smbus_delay();
+ for (j=0;j<0xFFFF;j++);
}
}
@@ -502,12 +501,13 @@ static const uint8_t SiS_SiS1183_init[44][3]={
};
/* In => Share Memory size
- => 00h : 0MBytes
- => 02h : 32MBytes
- => 03h : 64MBytes
- => 04h : 128MBytes
- => Others: Reserved
-*/
+ * => 00h : 0MBytes
+ * => 02h : 32MBytes
+ * => 03h : 64MBytes
+ * => 03h : 64MBytes
+ * => 04h : 128MBytes
+ * => Others: Reserved
+ */
static void Init_Share_Memory(uint8_t ShareSize)
{
device_t dev;
@@ -517,62 +517,62 @@ static void Init_Share_Memory(uint8_t ShareSize)
}
/* In: => Aperture size
- => 00h : 32MBytes
- => 01h : 64MBytes
- => 02h : 128MBytes
- => 03h : 256MBytes
- => 04h : 512MBytes
- => Others: Reserved
-*/
+ * => 00h : 32MBytes
+ * => 01h : 64MBytes
+ * => 02h : 128MBytes
+ * => 03h : 256MBytes
+ * => 04h : 512MBytes
+ * => Others: Reserved
+ */
static void Init_Aper_Size(uint8_t AperSize)
{
- device_t dev;
- uint16_t SiSAperSizeTable[]={0x0F38, 0x0F30, 0x0F20, 0x0F00, 0x0E00};
+ device_t dev;
+ uint16_t SiSAperSizeTable[]={0x0F38, 0x0F30, 0x0F20, 0x0F00, 0x0E00};
- dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_AMD, 0x1103), 0);
- pci_write_config8(dev, 0x90, AperSize << 1);
+ dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_AMD, 0x1103), 0);
+ pci_write_config8(dev, 0x90, AperSize << 1);
- dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_SIS, PCI_DEVICE_ID_SIS_SIS761), 0);
- pci_write_config16(dev, 0xB4, SiSAperSizeTable[AperSize]);
+ dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_SIS, PCI_DEVICE_ID_SIS_SIS761), 0);
+ pci_write_config16(dev, 0xB4, SiSAperSizeTable[AperSize]);
}
static void sis_init_stage1(void)
{
- device_t dev;
- uint8_t temp8;
- int i;
- uint8_t GUI_En;
+ device_t dev;
+ uint8_t temp8;
+ int i;
+ uint8_t GUI_En;
// SiS_Chipset_Initialization
// ========================== NB =============================
dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_SIS, PCI_DEVICE_ID_SIS_SIS761), 0);
i=0;
- while(SiS_NB_init[i][0] != 0)
- { temp8 = pci_read_config8(dev, SiS_NB_init[i][0]);
- temp8 &= SiS_NB_init[i][1];
- temp8 |= SiS_NB_init[i][2];
- pci_write_config8(dev, SiS_NB_init[i][0], temp8);
- i++;
+ while (SiS_NB_init[i][0] != 0) {
+ temp8 = pci_read_config8(dev, SiS_NB_init[i][0]);
+ temp8 &= SiS_NB_init[i][1];
+ temp8 |= SiS_NB_init[i][2];
+ pci_write_config8(dev, SiS_NB_init[i][0], temp8);
+ i++;
};
// ========================== LPC =============================
dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_SIS, PCI_DEVICE_ID_SIS_SIS966_LPC), 0);
i=0;
- while(SiS_LPC_init[i][0] != 0)
- { temp8 = pci_read_config8(dev, SiS_LPC_init[i][0]);
- temp8 &= SiS_LPC_init[i][1];
- temp8 |= SiS_LPC_init[i][2];
- pci_write_config8(dev, SiS_LPC_init[i][0], temp8);
- i++;
+ while (SiS_LPC_init[i][0] != 0) {
+ temp8 = pci_read_config8(dev, SiS_LPC_init[i][0]);
+ temp8 &= SiS_LPC_init[i][1];
+ temp8 |= SiS_LPC_init[i][2];
+ pci_write_config8(dev, SiS_LPC_init[i][0], temp8);
+ i++;
};
// ========================== ACPI =============================
i=0;
- while(SiS_ACPI_init[i][0] != 0)
- { temp8 = inb(0x800 + SiS_ACPI_init[i][0]);
- temp8 &= SiS_ACPI_init[i][1];
- temp8 |= SiS_ACPI_init[i][2];
- outb(temp8, 0x800 + SiS_ACPI_init[i][0]);
- i++;
+ while (SiS_ACPI_init[i][0] != 0) {
+ temp8 = inb(0x800 + SiS_ACPI_init[i][0]);
+ temp8 &= SiS_ACPI_init[i][1];
+ temp8 |= SiS_ACPI_init[i][2];
+ outb(temp8, 0x800 + SiS_ACPI_init[i][0]);
+ i++;
};
// ========================== NBPCIE =============================
dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_SIS, PCI_DEVICE_ID_SIS_SIS761), 0); //Disable Internal GUI enable bit
@@ -582,12 +582,12 @@ static void sis_init_stage1(void)
dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_SIS, PCI_DEVICE_ID_SIS_SIS761_PCIE), 0);
i=0;
- while(SiS_NBPCIE_init[i][0] != 0)
- { temp8 = pci_read_config8(dev, SiS_NBPCIE_init[i][0]);
- temp8 &= SiS_NBPCIE_init[i][1];
- temp8 |= SiS_NBPCIE_init[i][2];
- pci_write_config8(dev, SiS_NBPCIE_init[i][0], temp8);
- i++;
+ while (SiS_NBPCIE_init[i][0] != 0) {
+ temp8 = pci_read_config8(dev, SiS_NBPCIE_init[i][0]);
+ temp8 &= SiS_NBPCIE_init[i][1];
+ temp8 |= SiS_NBPCIE_init[i][2];
+ pci_write_config8(dev, SiS_NBPCIE_init[i][0], temp8);
+ i++;
};
dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_SIS, PCI_DEVICE_ID_SIS_SIS761), 0); //Restore Internal GUI enable bit
temp8 = pci_read_config8(dev, 0x4C);
@@ -608,20 +608,19 @@ static void sis_init_stage2(void)
// ========================== NB_AGP =============================
- dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_SIS, PCI_DEVICE_ID_SIS_SIS761), 0); //Enable Internal GUI enable bit
- pci_write_config8(dev, 0x4C, pci_read_config8(dev, 0x4C) | 0x10);
+ dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_SIS, PCI_DEVICE_ID_SIS_SIS761), 0); //Enable Internal GUI enable bit
+ pci_write_config8(dev, 0x4C, pci_read_config8(dev, 0x4C) | 0x10);
- dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_SIS, PCI_DEVICE_ID_SIS_AGP), 0);
- i=0;
+ dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_SIS, PCI_DEVICE_ID_SIS_AGP), 0);
+ i=0;
- while(SiS_NBAGP_init[i][0] != 0)
- {
- temp8 = pci_read_config8(dev, SiS_NBAGP_init[i][0]);
- temp8 &= SiS_NBAGP_init[i][1];
- temp8 |= SiS_NBAGP_init[i][2];
- pci_write_config8(dev, SiS_NBAGP_init[i][0], temp8);
- i++;
- };
+ while (SiS_NBAGP_init[i][0] != 0) {
+ temp8 = pci_read_config8(dev, SiS_NBAGP_init[i][0]);
+ temp8 &= SiS_NBAGP_init[i][1];
+ temp8 |= SiS_NBAGP_init[i][2];
+ pci_write_config8(dev, SiS_NBAGP_init[i][0], temp8);
+ i++;
+ };
/**
* Share Memory size
@@ -640,38 +639,38 @@ static void sis_init_stage2(void)
* => Others: Reserved
*/
- Init_Share_Memory(0x02); //0x02 : 32M
- Init_Aper_Size(0x01); //0x1 : 64M
+ Init_Share_Memory(0x02); //0x02 : 32M
+ Init_Aper_Size(0x01); //0x1 : 64M
// ========================== NB =============================
- printk(BIOS_DEBUG, "Init NorthBridge sis761 -------->\n");
- dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_SIS, PCI_DEVICE_ID_SIS_SIS761), 0);
- msr = rdmsr(0xC001001A);
+ printk(BIOS_DEBUG, "Init NorthBridge sis761 -------->\n");
+ dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_SIS, PCI_DEVICE_ID_SIS_SIS761), 0);
+ msr = rdmsr(0xC001001A);
printk(BIOS_DEBUG, "Memory Top Bound %x\n",msr.lo );
- temp16=(pci_read_config8(dev, 0x4C) & 0xE0) >> 5;
- temp16=0x0001<<(temp16-1);
- temp16<<=8;
+ temp16=(pci_read_config8(dev, 0x4C) & 0xE0) >> 5;
+ temp16=0x0001<<(temp16-1);
+ temp16<<=8;
- printk(BIOS_DEBUG, "Integrated VGA Shared memory size=%dM bytes\n", temp16 >> 4);
- pci_write_config16(dev, 0x8E, (msr.lo >> 16) -temp16*1);
- pci_write_config8(dev, 0x7F, 0x08); // ACPI Base
- outb(inb(0x856) | 0x40, 0x856); // Auto-Reset Function
+ printk(BIOS_DEBUG, "Integrated VGA Shared memory size=%dM bytes\n", temp16 >> 4);
+ pci_write_config16(dev, 0x8E, (msr.lo >> 16) -temp16*1);
+ pci_write_config8(dev, 0x7F, 0x08); // ACPI Base
+ outb(inb(0x856) | 0x40, 0x856); // Auto-Reset Function
// ========================== ACPI =============================
i=0;
printk(BIOS_DEBUG, "Init ACPI -------->\n");
- do
- { temp8 = inb(0x800 + SiS_ACPI_2_init[i][0]);
- temp8 &= SiS_ACPI_2_init[i][1];
- temp8 |= SiS_ACPI_2_init[i][2];
- outb(temp8, 0x800 + SiS_ACPI_2_init[i][0]);
- i++;
- }while(SiS_ACPI_2_init[i][0] != 0);
+ do {
+ temp8 = inb(0x800 + SiS_ACPI_2_init[i][0]);
+ temp8 &= SiS_ACPI_2_init[i][1];
+ temp8 |= SiS_ACPI_2_init[i][2];
+ outb(temp8, 0x800 + SiS_ACPI_2_init[i][0]);
+ i++;
+ } while (SiS_ACPI_2_init[i][0] != 0);
// ========================== Misc =============================
- printk(BIOS_DEBUG, "Init Misc -------->\n");
+ printk(BIOS_DEBUG, "Init Misc -------->\n");
dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_SIS, PCI_DEVICE_ID_SIS_SIS966_LPC), 0);
/* R77h Internal PCI Device Enable 1 (Power On Value = 0h)
diff --git a/src/southbridge/sis/sis966/ide.c b/src/southbridge/sis/sis966/ide.c
index ebea6f3..5686227 100644
--- a/src/southbridge/sis/sis966/ide.c
+++ b/src/southbridge/sis/sis966/ide.c
@@ -101,15 +101,14 @@ printk(BIOS_DEBUG, "IDE_INIT:---------->\n");
//-------------- enable IDE (SiS5513) -------------------------
{
- uint8_t temp8;
- int i=0;
- while(SiS_SiS5513_init[i][0] != 0)
- {
- temp8 = pci_read_config8(dev, SiS_SiS5513_init[i][0]);
- temp8 &= SiS_SiS5513_init[i][1];
- temp8 |= SiS_SiS5513_init[i][2];
- pci_write_config8(dev, SiS_SiS5513_init[i][0], temp8);
- i++;
+ uint8_t temp8;
+ int i=0;
+ while (SiS_SiS5513_init[i][0] != 0) {
+ temp8 = pci_read_config8(dev, SiS_SiS5513_init[i][0]);
+ temp8 &= SiS_SiS5513_init[i][1];
+ temp8 |= SiS_SiS5513_init[i][2];
+ pci_write_config8(dev, SiS_SiS5513_init[i][0], temp8);
+ i++;
};
}
//-----------------------------------------------------------
@@ -143,17 +142,17 @@ printk(BIOS_DEBUG, "IDE_INIT:---------->\n");
#if DEBUG_IDE
{
- int i;
+ int i;
- printk(BIOS_DEBUG, "****** IDE PCI config ******");
- printk(BIOS_DEBUG, "\n 03020100 07060504 0B0A0908 0F0E0D0C");
+ printk(BIOS_DEBUG, "****** IDE PCI config ******");
+ printk(BIOS_DEBUG, "\n 03020100 07060504 0B0A0908 0F0E0D0C");
- for (i=0;i<0xff;i+=4){
- if ((i%16)==0)
- printk(BIOS_DEBUG, "\n%02x: ", i);
- printk(BIOS_DEBUG, "%08x ", pci_read_config32(dev,i));
- }
- printk(BIOS_DEBUG, "\n");
+ for (i=0;i<0xff;i+=4) {
+ if ((i%16)==0)
+ printk(BIOS_DEBUG, "\n%02x: ", i);
+ printk(BIOS_DEBUG, "%08x ", pci_read_config32(dev,i));
+ }
+ printk(BIOS_DEBUG, "\n");
}
#endif
printk(BIOS_DEBUG, "IDE_INIT:<----------\n");
diff --git a/src/southbridge/sis/sis966/lpc.c b/src/southbridge/sis/sis966/lpc.c
index ef26745..e1a356b 100644
--- a/src/southbridge/sis/sis966/lpc.c
+++ b/src/southbridge/sis/sis966/lpc.c
@@ -112,7 +112,7 @@ static void lpc_init(device_t dev)
/* Throttle the CPU speed down for testing */
on = SLOW_CPU_OFF;
get_option(&on, "slow_cpu");
- if(on) {
+ if (on) {
uint16_t pm10_bar;
uint32_t dword;
pm10_bar = (pci_read_config16(dev, 0x60)&0xff00);
@@ -123,33 +123,33 @@ static void lpc_init(device_t dev)
(on*12)+(on>>1),(on&1)*5);
}
- /* Enable Error reporting */
- /* Set up sync flood detected */
- byte = pci_read_config8(dev, 0x47);
- byte |= (1 << 1);
- pci_write_config8(dev, 0x47, byte);
-
- /* Set up NMI on errors */
- byte = inb(0x70); // RTC70
- byte_old = byte;
- nmi_option = NMI_OFF;
- get_option(&nmi_option, "nmi");
- if (nmi_option) {
- byte &= ~(1 << 7); /* set NMI */
- } else {
- byte |= ( 1 << 7); // Can not mask NMI from PCI-E and NMI_NOW
- }
- if ( byte != byte_old) {
- outb(byte, 0x70);
- }
-
- /* Initialize the real time clock */
- cmos_init(0);
-
- /* Initialize isa dma */
- isa_dma_init();
-
- printk(BIOS_DEBUG, "LPC_INIT <--------\n");
+ /* Enable Error reporting */
+ /* Set up sync flood detected */
+ byte = pci_read_config8(dev, 0x47);
+ byte |= (1 << 1);
+ pci_write_config8(dev, 0x47, byte);
+
+ /* Set up NMI on errors */
+ byte = inb(0x70); // RTC70
+ byte_old = byte;
+ nmi_option = NMI_OFF;
+ get_option(&nmi_option, "nmi");
+ if (nmi_option) {
+ byte &= ~(1 << 7); /* set NMI */
+ } else {
+ byte |= ( 1 << 7); // Can not mask NMI from PCI-E and NMI_NOW
+ }
+ if ( byte != byte_old) {
+ outb(byte, 0x70);
+ }
+
+ /* Initialize the real time clock */
+ cmos_init(0);
+
+ /* Initialize isa dma */
+ isa_dma_init();
+
+ printk(BIOS_DEBUG, "LPC_INIT <--------\n");
}
static void sis966_lpc_read_resources(device_t dev)
@@ -195,11 +195,11 @@ static void sis966_lpc_enable_childrens_resources(device_t dev)
for (link = dev->link_list; link; link = link->next) {
device_t child;
for (child = link->children; child; child = child->sibling) {
- if(child->enabled && (child->path.type == DEVICE_PATH_PNP)) {
+ if (child->enabled && (child->path.type == DEVICE_PATH_PNP)) {
struct resource *res;
- for(res = child->resource_list; res; res = res->next) {
+ for (res = child->resource_list; res; res = res->next) {
unsigned long base, end; // don't need long long
- if(!(res->flags & IORESOURCE_IO)) continue;
+ if (!(res->flags & IORESOURCE_IO)) continue;
base = res->base;
end = resource_end(res);
printk(BIOS_DEBUG, "sis966 lpc decode:%s, base=0x%08lx, end=0x%08lx\n",dev_path(child),base, end);
@@ -217,8 +217,8 @@ static void sis966_lpc_enable_childrens_resources(device_t dev)
case 0x300: // Midi 0
reg |= (1<<12); break;
}
- if( (base == 0x290) || (base >= 0x400)) {
- if(var_num>=4) continue; // only 4 var ; compact them ?
+ if ( (base == 0x290) || (base >= 0x400)) {
+ if (var_num>=4) continue; // only 4 var ; compact them ?
reg |= (1<<(28+var_num));
reg_var[var_num++] = (base & 0xffff)|((end & 0xffff)<<16);
}
@@ -227,7 +227,7 @@ static void sis966_lpc_enable_childrens_resources(device_t dev)
}
}
pci_write_config32(dev, 0xa0, reg);
- for(i=0;i<var_num;i++) {
+ for (i=0;i<var_num;i++) {
pci_write_config32(dev, 0xa8 + i*4, reg_var[i]);
}
diff --git a/src/southbridge/sis/sis966/nic.c b/src/southbridge/sis/sis966/nic.c
index 0d014aa..a167848 100644
--- a/src/southbridge/sis/sis966/nic.c
+++ b/src/southbridge/sis/sis966/nic.c
@@ -51,73 +51,71 @@ u16 MacAddr[3];
static void writeApcByte(int addr, u8 value)
{
- outb(addr,0x78);
- outb(value,0x79);
+ outb(addr,0x78);
+ outb(value,0x79);
}
static u8 readApcByte(int addr)
{
- u8 value;
- outb(addr,0x78);
- value=inb(0x79);
- return(value);
+ u8 value;
+ outb(addr,0x78);
+ value=inb(0x79);
+ return(value);
}
static void readApcMacAddr(void)
{
- u8 i;
+ u8 i;
// enable APC in south bridge sis966 D2F0
- outl(0x80001048,0xcf8);
- outl((inl(0xcfc) & 0xfffffffd),0xcfc ); // enable IO78/79h for APC Index/Data
+ outl(0x80001048,0xcf8);
+ outl((inl(0xcfc) & 0xfffffffd),0xcfc ); // enable IO78/79h for APC Index/Data
- printk(BIOS_DEBUG, "MAC addr in APC = ");
- for (i = 0x9 ; i <=0xe ; i++)
- {
- printk(BIOS_DEBUG, "%2.2x",readApcByte(i));
- }
- printk(BIOS_DEBUG, "\n");
+ printk(BIOS_DEBUG, "MAC addr in APC = ");
+ for (i = 0x9 ; i <=0xe ; i++) {
+ printk(BIOS_DEBUG, "%2.2x",readApcByte(i));
+ }
+ printk(BIOS_DEBUG, "\n");
- /* Set APC Reload */
- writeApcByte(0x7,readApcByte(0x7)&0xf7);
- writeApcByte(0x7,readApcByte(0x7)|0x0a);
+ /* Set APC Reload */
+ writeApcByte(0x7,readApcByte(0x7)&0xf7);
+ writeApcByte(0x7,readApcByte(0x7)|0x0a);
- /* disable APC in south bridge */
- outl(0x80001048,0xcf8);
- outl(inl(0xcfc)&0xffffffbf,0xcfc);
+ /* disable APC in south bridge */
+ outl(0x80001048,0xcf8);
+ outl(inl(0xcfc)&0xffffffbf,0xcfc);
}
static void set_apc(struct device *dev)
{
- u16 addr;
- u16 i;
- u8 bTmp;
-
- /* enable APC in south bridge sis966 D2F0 */
- outl(0x80001048,0xcf8);
- outl((inl(0xcfc) & 0xfffffffd),0xcfc ); // enable IO78/79h for APC Index/Data
-
- for (i = 0 ; i <3; i++)
- {
- addr=0x9+2*i;
- writeApcByte(addr,(u8)(MacAddr[i]&0xFF));
- writeApcByte(addr+1L,(u8)((MacAddr[i]>>8)&0xFF));
- // printf("%x - ",readMacAddrByte(0x59+i));
- }
-
- /* Set APC Reload */
- writeApcByte(0x7,readApcByte(0x7)&0xf7);
- writeApcByte(0x7,readApcByte(0x7)|0x0a);
-
- /* disable APC in south bridge */
- outl(0x80001048,0xcf8);
- outl(inl(0xcfc)&0xffffffbf,0xcfc);
-
- // CFG reg0x73 bit=1, tell driver MAC Address load to APC
- bTmp = pci_read_config8(dev, 0x73);
- bTmp|=0x1;
- pci_write_config8(dev, 0x73, bTmp);
+ u16 addr;
+ u16 i;
+ u8 bTmp;
+
+ /* enable APC in south bridge sis966 D2F0 */
+ outl(0x80001048,0xcf8);
+ outl((inl(0xcfc) & 0xfffffffd),0xcfc ); // enable IO78/79h for APC Index/Data
+
+ for (i = 0 ; i <3; i++) {
+ addr=0x9+2*i;
+ writeApcByte(addr,(u8)(MacAddr[i]&0xFF));
+ writeApcByte(addr+1L,(u8)((MacAddr[i]>>8)&0xFF));
+ // printf("%x - ",readMacAddrByte(0x59+i));
+ }
+
+ /* Set APC Reload */
+ writeApcByte(0x7,readApcByte(0x7)&0xf7);
+ writeApcByte(0x7,readApcByte(0x7)|0x0a);
+
+ /* disable APC in south bridge */
+ outl(0x80001048,0xcf8);
+ outl(inl(0xcfc)&0xffffffbf,0xcfc);
+
+ // CFG reg0x73 bit=1, tell driver MAC Address load to APC
+ bTmp = pci_read_config8(dev, 0x73);
+ bTmp|=0x1;
+ pci_write_config8(dev, 0x73, bTmp);
}
/**
@@ -131,100 +129,88 @@ static void set_apc(struct device *dev)
#define LoopNum 200
static unsigned long ReadEEprom( struct device *dev, u8 *base, u32 Reg)
{
- u32 data;
- u32 i;
- u32 ulValue;
+ u32 data;
+ u32 i;
+ u32 ulValue;
+ ulValue = (0x80 | (0x2 << 8) | (Reg << 10)); //BIT_7
- ulValue = (0x80 | (0x2 << 8) | (Reg << 10)); //BIT_7
+ write32(base + 0x3c, ulValue);
- write32(base + 0x3c, ulValue);
+ mdelay(10);
- mdelay(10);
+ for (i=0 ; i <= LoopNum; i++) {
+ ulValue=read32(base + 0x3c);
- for (i=0 ; i <= LoopNum; i++)
- {
- ulValue=read32(base + 0x3c);
+ if (!(ulValue & 0x0080)) //BIT_7
+ break;
- if (!(ulValue & 0x0080)) //BIT_7
- break;
-
- mdelay(100);
- }
+ mdelay(100);
+ }
- mdelay(50);
+ mdelay(50);
- if (i==LoopNum) data=0x10000;
- else{
- ulValue=read32(base + 0x3c);
- data = ((ulValue & 0xffff0000) >> 16);
- }
+ if (i==LoopNum) data=0x10000;
+ else {
+ ulValue=read32(base + 0x3c);
+ data = ((ulValue & 0xffff0000) >> 16);
+ }
- return data;
+ return data;
}
static int phy_read(u8 *base, unsigned phy_addr, unsigned phy_reg)
{
- u32 ulValue;
- u32 Read_Cmd;
- u16 usData;
-
-
-
- Read_Cmd = ((phy_reg << 11) |
- (phy_addr << 6) |
- SMI_READ |
- SMI_REQUEST);
-
- // SmiMgtInterface Reg is the SMI management interface register(offset 44h) of MAC
- write32(base + 0x44, Read_Cmd);
-
- // Polling SMI_REQ bit to be deasserted indicated read command completed
- do
- {
- // Wait 20 usec before checking status
- mdelay(20);
- ulValue = read32(base + 0x44);
- } while((ulValue & SMI_REQUEST) != 0);
- //printk(BIOS_DEBUG, "base %x cmd %lx ret val %lx\n", tmp,Read_Cmd,ulValue);
- usData=(ulValue>>16);
-
-
+ u32 ulValue;
+ u32 Read_Cmd;
+ u16 usData;
+
+ Read_Cmd = ((phy_reg << 11) |
+ (phy_addr << 6) |
+ SMI_READ |
+ SMI_REQUEST);
+
+ // SmiMgtInterface Reg is the SMI management interface register(offset 44h) of MAC
+ write32(base + 0x44, Read_Cmd);
+
+ // Polling SMI_REQ bit to be deasserted indicated read command completed
+ do {
+ // Wait 20 usec before checking status
+ mdelay(20);
+ ulValue = read32(base + 0x44);
+ } while ((ulValue & SMI_REQUEST) != 0);
+ //printk(BIOS_DEBUG, "base %x cmd %lx ret val %lx\n", tmp,Read_Cmd,ulValue);
+ usData=(ulValue>>16);
return usData;
-
}
// Detect a valid PHY
// If there exist a valid PHY then return TRUE, else return FALSE
static int phy_detect(u8 *base,u16 *PhyAddr) //BOOL PHY_Detect()
{
- int bFoundPhy = FALSE;
- u16 usData;
- int PhyAddress = 0;
+ int bFoundPhy = FALSE;
+ u16 usData;
+ int PhyAddress = 0;
- // Scan all PHY address(0 ~ 31) to find a valid PHY
- for (PhyAddress = 0; PhyAddress < 32; PhyAddress++)
- {
+ // Scan all PHY address(0 ~ 31) to find a valid PHY
+ for (PhyAddress = 0; PhyAddress < 32; PhyAddress++) {
usData=phy_read(base,PhyAddress,StatusReg); // Status register is a PHY's register(offset 01h)
- // Found a valid PHY
-
- if ((usData != 0x0) && (usData != 0xffff))
- {
- bFoundPhy = TRUE;
- break;
- }
- }
+ // Found a valid PHY
+ if ((usData != 0x0) && (usData != 0xffff)) {
+ bFoundPhy = TRUE;
+ break;
+ }
+ }
- if (!bFoundPhy)
- {
- printk(BIOS_DEBUG, "PHY not found !!!!\n");
+ if (!bFoundPhy) {
+ printk(BIOS_DEBUG, "PHY not found !!!!\n");
}
- *PhyAddr=PhyAddress;
+ *PhyAddr=PhyAddress;
return bFoundPhy;
}
@@ -232,59 +218,55 @@ static int phy_detect(u8 *base,u16 *PhyAddr) //BOOL PHY_Detect()
static void nic_init(struct device *dev)
{
- int val;
- u16 PhyAddr;
- u8 *base;
- struct resource *res;
+ int val;
+ u16 PhyAddr;
+ u8 *base;
+ struct resource *res;
- printk(BIOS_DEBUG, "NIC_INIT:---------->\n");
+ printk(BIOS_DEBUG, "NIC_INIT:---------->\n");
//-------------- enable NIC (SiS19x) -------------------------
{
- u8 temp8;
- int i=0;
- while(SiS_SiS191_init[i][0] != 0)
- {
- temp8 = pci_read_config8(dev, SiS_SiS191_init[i][0]);
- temp8 &= SiS_SiS191_init[i][1];
- temp8 |= SiS_SiS191_init[i][2];
- pci_write_config8(dev, SiS_SiS191_init[i][0], temp8);
- i++;
+ u8 temp8;
+ int i=0;
+ while (SiS_SiS191_init[i][0] != 0) {
+ temp8 = pci_read_config8(dev, SiS_SiS191_init[i][0]);
+ temp8 &= SiS_SiS191_init[i][1];
+ temp8 |= SiS_SiS191_init[i][2];
+ pci_write_config8(dev, SiS_SiS191_init[i][0], temp8);
+ i++;
};
}
//-----------------------------------------------------------
{
- unsigned long i;
- unsigned long ulValue;
+ unsigned long i;
+ unsigned long ulValue;
res = find_resource(dev, 0x10);
- if (!res)
- {
+ if (!res) {
printk(BIOS_DEBUG, "NIC Cannot find resource..\n");
return;
}
base = res2mmio(res, 0, 0);
- printk(BIOS_DEBUG, "NIC base address %p\n",base);
+ printk(BIOS_DEBUG, "NIC base address %p\n",base);
- if (!(val=phy_detect(base,&PhyAddr)))
- {
- printk(BIOS_DEBUG, "PHY detect fail !!!!\n");
+ if (!(val=phy_detect(base,&PhyAddr))) {
+ printk(BIOS_DEBUG, "PHY detect fail !!!!\n");
return;
}
- ulValue=read32(base + 0x38L); // check EEPROM existing
+ ulValue=read32(base + 0x38L); // check EEPROM existing
- if ((ulValue & 0x0002))
- {
+ if ((ulValue & 0x0002)) {
- // read MAC address from EEPROM at first
+ // read MAC address from EEPROM at first
- // if that is valid we will use that
+ // if that is valid we will use that
printk(BIOS_DEBUG, "EEPROM contents %lx\n",ReadEEprom( dev, base, 0LL));
- for(i=0;i<3;i++) {
+ for (i=0;i<3;i++) {
//status = smbus_read_byte(dev_eeprom, i);
ulValue=ReadEEprom( dev, base, i+3L);
if (ulValue ==0x10000) break; // error
@@ -292,31 +274,31 @@ static void nic_init(struct device *dev)
MacAddr[i] =ulValue & 0xFFFF;
}
- }else{
- // read MAC address from firmware
- printk(BIOS_DEBUG, "EEPROM invalid!!\nReg 0x38h=%.8lx\n",ulValue);
- MacAddr[0]=read16((u16 *)0xffffffc0); // mac address store at here
- MacAddr[1]=read16((u16 *)0xffffffc2);
- MacAddr[2]=read16((u16 *)0xffffffc4);
- }
+ } else {
+ // read MAC address from firmware
+ printk(BIOS_DEBUG, "EEPROM invalid!!\nReg 0x38h=%.8lx\n",ulValue);
+ MacAddr[0]=read16((u16 *)0xffffffc0); // mac address store at here
+ MacAddr[1]=read16((u16 *)0xffffffc2);
+ MacAddr[2]=read16((u16 *)0xffffffc4);
+ }
- set_apc(dev);
+ set_apc(dev);
- readApcMacAddr();
+ readApcMacAddr();
#if DEBUG_NIC
{
- int i;
+ int i;
- printk(BIOS_DEBUG, "****** NIC PCI config ******");
- printk(BIOS_DEBUG, "\n 03020100 07060504 0B0A0908 0F0E0D0C");
+ printk(BIOS_DEBUG, "****** NIC PCI config ******");
+ printk(BIOS_DEBUG, "\n 03020100 07060504 0B0A0908 0F0E0D0C");
- for (i=0;i<0xff;i+=4){
- if ((i%16)==0)
- printk(BIOS_DEBUG, "\n%02x: ", i);
- printk(BIOS_DEBUG, "%08x ", pci_read_config32(dev,i));
- }
- printk(BIOS_DEBUG, "\n");
+ for (i=0;i<0xff;i+=4) {
+ if ((i%16)==0)
+ printk(BIOS_DEBUG, "\n%02x: ", i);
+ printk(BIOS_DEBUG, "%08x ", pci_read_config32(dev,i));
+ }
+ printk(BIOS_DEBUG, "\n");
}
diff --git a/src/southbridge/sis/sis966/sata.c b/src/southbridge/sis/sis966/sata.c
index eb69ab0..3f114a0 100644
--- a/src/southbridge/sis/sis966/sata.c
+++ b/src/southbridge/sis/sis966/sata.c
@@ -109,22 +109,19 @@ static void sata_init(struct device *dev)
{
struct southbridge_sis_sis966_config *conf;
-
-
conf = dev->chip_info;
- printk(BIOS_DEBUG, "SATA_INIT:---------->\n");
+ printk(BIOS_DEBUG, "SATA_INIT:---------->\n");
//-------------- enable IDE (SiS1183) -------------------------
{
- uint8_t temp8;
- int i=0;
- while(SiS_SiS1183_init[i][0] != 0)
- {
- temp8 = pci_read_config8(dev, SiS_SiS1183_init[i][0]);
- temp8 &= SiS_SiS1183_init[i][1];
- temp8 |= SiS_SiS1183_init[i][2];
- pci_write_config8(dev, SiS_SiS1183_init[i][0], temp8);
- i++;
+ uint8_t temp8;
+ int i=0;
+ while (SiS_SiS1183_init[i][0] != 0) {
+ temp8 = pci_read_config8(dev, SiS_SiS1183_init[i][0]);
+ temp8 &= SiS_SiS1183_init[i][1];
+ temp8 |= SiS_SiS1183_init[i][2];
+ pci_write_config8(dev, SiS_SiS1183_init[i][0], temp8);
+ i++;
};
}
//-----------------------------------------------------------
@@ -133,33 +130,33 @@ static void sata_init(struct device *dev)
uint32_t i,j;
uint32_t temp32;
-for (i=0;i<10;i++){
- temp32=0;
- temp32= pci_read_config32(dev, 0xC0);
- for ( j=0;j<0xFFFF;j++);
- printk(BIOS_DEBUG, "status= %x\n",temp32);
- if (((temp32&0xF) == 0x3) || ((temp32&0xF) == 0x0)) break;
+for (i=0;i<10;i++) {
+ temp32=0;
+ temp32= pci_read_config32(dev, 0xC0);
+ for ( j=0;j<0xFFFF;j++);
+ printk(BIOS_DEBUG, "status= %x\n",temp32);
+ if (((temp32&0xF) == 0x3) || ((temp32&0xF) == 0x0)) break;
}
}
#if DEBUG_SATA
{
- int i;
+ int i;
- printk(BIOS_DEBUG, "****** SATA PCI config ******");
- printk(BIOS_DEBUG, "\n 03020100 07060504 0B0A0908 0F0E0D0C");
+ printk(BIOS_DEBUG, "****** SATA PCI config ******");
+ printk(BIOS_DEBUG, "\n 03020100 07060504 0B0A0908 0F0E0D0C");
- for (i=0;i<0xff;i+=4){
- if ((i%16)==0)
- printk(BIOS_DEBUG, "\n%02x: ", i);
- printk(BIOS_DEBUG, "%08x ", pci_read_config32(dev,i));
- }
- printk(BIOS_DEBUG, "\n");
+ for (i=0;i<0xff;i+=4) {
+ if ((i%16)==0)
+ printk(BIOS_DEBUG, "\n%02x: ", i);
+ printk(BIOS_DEBUG, "%08x ", pci_read_config32(dev,i));
+ }
+ printk(BIOS_DEBUG, "\n");
}
#endif
- printk(BIOS_DEBUG, "SATA_INIT:<----------\n");
+ printk(BIOS_DEBUG, "SATA_INIT:<----------\n");
}
diff --git a/src/southbridge/sis/sis966/sis966.c b/src/southbridge/sis/sis966/sis966.c
index 6ac15db..57d6498 100644
--- a/src/southbridge/sis/sis966/sis966.c
+++ b/src/southbridge/sis/sis966/sis966.c
@@ -70,7 +70,7 @@ void sis966_enable(device_t dev)
conf = dev->chip_info;
int i;
- if(dev->device==0x0000) {
+ if (dev->device==0x0000) {
reg = pci_read_config32(dev, PCI_VENDOR_ID);
deviceid = (reg >> 16) & 0xffff;
vendorid = reg & 0xffff;
@@ -92,9 +92,9 @@ void sis966_enable(device_t dev)
case PCI_DEVICE_ID_SIS_SIS966_NIC:
devfn -= (7<<3);
index = 10;
- for(i=0;i<2;i++) {
+ for (i=0;i<2;i++) {
lpc_dev = find_lpc_dev(dev, devfn - (i<<3));
- if(!lpc_dev) continue;
+ if (!lpc_dev) continue;
index -= i;
devfn -= (i<<3);
break;
@@ -112,7 +112,7 @@ void sis966_enable(device_t dev)
devfn -= (4<<3);
index = 22;
i = (dev->path.pci.devfn) & 7;
- if(i>0) {
+ if (i>0) {
index -= (i+3);
}
break;
@@ -124,14 +124,14 @@ void sis966_enable(device_t dev)
index = 0;
}
- if(!lpc_dev)
+ if (!lpc_dev)
lpc_dev = find_lpc_dev(dev, devfn);
if ( !lpc_dev ) return;
- if(index2!=0) {
+ if (index2!=0) {
sm_dev = dev_find_slot(dev->bus->secondary, devfn + 1);
- if(!sm_dev) return;
+ if (!sm_dev) return;
if ( sm_dev ) {
reg_old = reg = pci_read_config32(sm_dev, 0xe4);
@@ -165,9 +165,9 @@ void sis966_enable(device_t dev)
}
- if( index == 16) {
+ if ( index == 16) {
sm_dev = dev_find_slot(dev->bus->secondary, devfn + 1);
- if(!sm_dev) return;
+ if (!sm_dev) return;
final_reg = pci_read_config32(sm_dev, 0xe8);
final_reg &= ~0x0057cf00;
@@ -184,9 +184,9 @@ void sis966_enable(device_t dev)
*/
}
- if(index == 9 ) { //NIC1 is the final, We need update final reg to 0xe8
+ if (index == 9 ) { //NIC1 is the final, We need update final reg to 0xe8
sm_dev = dev_find_slot(dev->bus->secondary, devfn + 1);
- if(!sm_dev) return;
+ if (!sm_dev) return;
reg_old = pci_read_config32(sm_dev, 0xe8);
if (final_reg != reg_old) {
pci_write_config32(sm_dev, 0xe8, final_reg);
diff --git a/src/southbridge/sis/sis966/usb.c b/src/southbridge/sis/sis966/usb.c
index 64398e2..3f4f98d 100644
--- a/src/southbridge/sis/sis966/usb.c
+++ b/src/southbridge/sis/sis966/usb.c
@@ -51,39 +51,39 @@ uint8_t SiS_SiS7001_init[16][3]={
static void usb_init(struct device *dev)
{
- printk(BIOS_DEBUG, "USB 1.1 INIT:---------->\n");
+ printk(BIOS_DEBUG, "USB 1.1 INIT:---------->\n");
//-------------- enable USB1.1 (SiS7001) -------------------------
{
- uint8_t temp8;
- int i=0;
+ uint8_t temp8;
+ int i=0;
- while(SiS_SiS7001_init[i][0] != 0)
- { temp8 = pci_read_config8(dev, SiS_SiS7001_init[i][0]);
- temp8 &= SiS_SiS7001_init[i][1];
- temp8 |= SiS_SiS7001_init[i][2];
- pci_write_config8(dev, SiS_SiS7001_init[i][0], temp8);
- i++;
- };
+ while (SiS_SiS7001_init[i][0] != 0) {
+ temp8 = pci_read_config8(dev, SiS_SiS7001_init[i][0]);
+ temp8 &= SiS_SiS7001_init[i][1];
+ temp8 |= SiS_SiS7001_init[i][2];
+ pci_write_config8(dev, SiS_SiS7001_init[i][0], temp8);
+ i++;
+ };
}
//-----------------------------------------------------------
#if DEBUG_USB
{
- int i;
+ int i;
- printk(BIOS_DEBUG, "****** USB 1.1 PCI config ******");
- printk(BIOS_DEBUG, "\n 03020100 07060504 0B0A0908 0F0E0D0C");
+ printk(BIOS_DEBUG, "****** USB 1.1 PCI config ******");
+ printk(BIOS_DEBUG, "\n 03020100 07060504 0B0A0908 0F0E0D0C");
- for (i=0;i<0xff;i+=4){
- if ((i%16)==0)
- printk(BIOS_DEBUG, "\n%02x: ", i);
- printk(BIOS_DEBUG, "%08x ", pci_read_config32(dev,i));
- }
- printk(BIOS_DEBUG, "\n");
+ for (i=0;i<0xff;i+=4) {
+ if ((i%16)==0)
+ printk(BIOS_DEBUG, "\n%02x: ", i);
+ printk(BIOS_DEBUG, "%08x ", pci_read_config32(dev,i));
+ }
+ printk(BIOS_DEBUG, "\n");
}
#endif
- printk(BIOS_DEBUG, "USB 1.1 INIT:<----------\n");
+ printk(BIOS_DEBUG, "USB 1.1 INIT:<----------\n");
}
static void lpci_set_subsystem(device_t dev, unsigned vendor, unsigned device)
diff --git a/src/southbridge/sis/sis966/usb2.c b/src/southbridge/sis/sis966/usb2.c
index 8c34723..79e7d09 100644
--- a/src/southbridge/sis/sis966/usb2.c
+++ b/src/southbridge/sis/sis966/usb2.c
@@ -62,46 +62,45 @@ static const u8 SiS_SiS7002_init[22][3]={
static void usb2_init(struct device *dev)
{
- u8 *base;
- struct resource *res;
- int i;
- u8 temp8;
+ u8 *base;
+ struct resource *res;
+ int i;
+ u8 temp8;
- printk(BIOS_DEBUG, "USB 2.0 INIT:---------->\n");
+ printk(BIOS_DEBUG, "USB 2.0 INIT:---------->\n");
//-------------- enable USB2.0 (SiS7002) ----------------------
i = 0;
- while (SiS_SiS7002_init[i][0] != 0)
- {
- temp8 = pci_read_config8(dev, SiS_SiS7002_init[i][0]);
- temp8 &= SiS_SiS7002_init[i][1];
- temp8 |= SiS_SiS7002_init[i][2];
- pci_write_config8(dev, SiS_SiS7002_init[i][0], temp8);
- i++;
- };
-
- res = find_resource(dev, 0x10);
- if (!res)
- return;
-
- base = res2mmio(res, 0, 0);
- printk(BIOS_DEBUG, "base = 0x%p\n", base);
- write32(base + 0x20, 0x2);
+ while (SiS_SiS7002_init[i][0] != 0) {
+ temp8 = pci_read_config8(dev, SiS_SiS7002_init[i][0]);
+ temp8 &= SiS_SiS7002_init[i][1];
+ temp8 |= SiS_SiS7002_init[i][2];
+ pci_write_config8(dev, SiS_SiS7002_init[i][0], temp8);
+ i++;
+ };
+
+ res = find_resource(dev, 0x10);
+ if (!res)
+ return;
+
+ base = res2mmio(res, 0, 0);
+ printk(BIOS_DEBUG, "base = 0x%p\n", base);
+ write32(base + 0x20, 0x2);
//-------------------------------------------------------------
#if DEBUG_USB2
- printk(BIOS_DEBUG, "****** USB 2.0 PCI config ******");
- printk(BIOS_DEBUG, "\n 03020100 07060504 0B0A0908 0F0E0D0C");
-
- for (i=0;i<0xff;i+=4){
- if ((i%16)==0)
- printk(BIOS_DEBUG, "\n%02x: ", i);
- printk(BIOS_DEBUG, "%08x ", pci_read_config32(dev,i));
- }
- printk(BIOS_DEBUG, "\n");
+ printk(BIOS_DEBUG, "****** USB 2.0 PCI config ******");
+ printk(BIOS_DEBUG, "\n 03020100 07060504 0B0A0908 0F0E0D0C");
+
+ for (i=0;i<0xff;i+=4) {
+ if ((i%16)==0)
+ printk(BIOS_DEBUG, "\n%02x: ", i);
+ printk(BIOS_DEBUG, "%08x ", pci_read_config32(dev,i));
+ }
+ printk(BIOS_DEBUG, "\n");
#endif
- printk(BIOS_DEBUG, "USB 2.0 INIT:<----------\n");
+ printk(BIOS_DEBUG, "USB 2.0 INIT:<----------\n");
}
static void lpci_set_subsystem(device_t dev, unsigned vendor, unsigned device)
diff --git a/src/southbridge/via/k8t890/dram.c b/src/southbridge/via/k8t890/dram.c
index 308efbe..e907528 100644
--- a/src/southbridge/via/k8t890/dram.c
+++ b/src/southbridge/via/k8t890/dram.c
@@ -107,7 +107,7 @@ k8m890_host_fb_size_get(void)
{
struct device *dev = dev_find_device(PCI_VENDOR_ID_VIA,
PCI_DEVICE_ID_VIA_K8M800_DRAM, 0);
- if(!dev) dev = dev_find_device(PCI_VENDOR_ID_VIA,
+ if (!dev) dev = dev_find_device(PCI_VENDOR_ID_VIA,
PCI_DEVICE_ID_VIA_K8M890CE_3, 0);
unsigned char tmp;
diff --git a/src/southbridge/via/vt8237r/smihandler.c b/src/southbridge/via/vt8237r/smihandler.c
index fff3656..805c96e 100644
--- a/src/southbridge/via/vt8237r/smihandler.c
+++ b/src/southbridge/via/vt8237r/smihandler.c
@@ -245,7 +245,7 @@ void southbridge_smi_handler(unsigned int node, smm_state_save_area_t *state_sav
}
}
- if(dump) {
+ if (dump) {
dump_smi_status(smi_sts);
}
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