[coreboot-gerrit] Patch set updated for coreboot: PCI ops: Remove conflicting duplicate declarations
Kyösti Mälkki (kyosti.malkki@gmail.com)
gerrit at coreboot.org
Mon Dec 5 06:29:27 CET 2016
Kyösti Mälkki (kyosti.malkki at gmail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17720
-gerrit
commit aecdfb0be5cc4d471d329aa057adc5e24176f29d
Author: Kyösti Mälkki <kyosti.malkki at gmail.com>
Date: Mon Dec 5 06:33:32 2016 +0200
PCI ops: Remove conflicting duplicate declarations
The code originates from times before __SIMPLE_DEVICE__ was
introduced. To keep behaviour unchanged, use explicit PCI
IO operations here.
Change-Id: I44851633115f9aee4c308fd3711571a4b14c5f2f
Signed-off-by: Kyösti Mälkki <kyosti.malkki at gmail.com>
---
src/northbridge/amd/amdk8/reset_test.c | 18 +++++-----
src/southbridge/amd/amd8111/reset.c | 56 ++++++++++++--------------------
src/southbridge/broadcom/bcm5785/reset.c | 23 ++-----------
src/southbridge/nvidia/ck804/reset.c | 23 ++-----------
src/southbridge/nvidia/mcp55/reset.c | 23 ++-----------
src/southbridge/sis/sis966/reset.c | 23 ++-----------
6 files changed, 37 insertions(+), 129 deletions(-)
diff --git a/src/northbridge/amd/amdk8/reset_test.c b/src/northbridge/amd/amdk8/reset_test.c
index 53f2433..d8734a9 100644
--- a/src/northbridge/amd/amdk8/reset_test.c
+++ b/src/northbridge/amd/amdk8/reset_test.c
@@ -13,7 +13,7 @@ static inline int cpu_init_detected(unsigned nodeid)
pci_devfn_t dev;
dev = PCI_DEV(0, 0x18 + nodeid, 0);
- htic = pci_read_config32(dev, HT_INIT_CONTROL);
+ htic = pci_io_read_config32(dev, HT_INIT_CONTROL);
return !!(htic & HTIC_INIT_Detect);
}
@@ -21,7 +21,7 @@ static inline int cpu_init_detected(unsigned nodeid)
static inline int bios_reset_detected(void)
{
u32 htic;
- htic = pci_read_config32(PCI_DEV(0, 0x18, 0), HT_INIT_CONTROL);
+ htic = pci_io_read_config32(PCI_DEV(0, 0x18, 0), HT_INIT_CONTROL);
return (htic & HTIC_ColdR_Detect) && !(htic & HTIC_BIOSR_Detect);
}
@@ -29,7 +29,7 @@ static inline int bios_reset_detected(void)
static inline int cold_reset_detected(void)
{
u32 htic;
- htic = pci_read_config32(PCI_DEV(0, 0x18, 0), HT_INIT_CONTROL);
+ htic = pci_io_read_config32(PCI_DEV(0, 0x18, 0), HT_INIT_CONTROL);
return !(htic & HTIC_ColdR_Detect);
}
@@ -39,18 +39,18 @@ static inline void distinguish_cpu_resets(unsigned nodeid)
u32 htic;
pci_devfn_t device;
device = PCI_DEV(0, 0x18 + nodeid, 0);
- htic = pci_read_config32(device, HT_INIT_CONTROL);
+ htic = pci_io_read_config32(device, HT_INIT_CONTROL);
htic |= HTIC_ColdR_Detect | HTIC_BIOSR_Detect | HTIC_INIT_Detect;
- pci_write_config32(device, HT_INIT_CONTROL, htic);
+ pci_io_write_config32(device, HT_INIT_CONTROL, htic);
}
void set_bios_reset(void);
void set_bios_reset(void)
{
u32 htic;
- htic = pci_read_config32(PCI_DEV(0, 0x18, 0), HT_INIT_CONTROL);
+ htic = pci_io_read_config32(PCI_DEV(0, 0x18, 0), HT_INIT_CONTROL);
htic &= ~HTIC_BIOSR_Detect;
- pci_write_config32(PCI_DEV(0, 0x18, 0), HT_INIT_CONTROL, htic);
+ pci_io_write_config32(PCI_DEV(0, 0x18, 0), HT_INIT_CONTROL, htic);
}
static unsigned node_link_to_bus(unsigned node, unsigned link)
@@ -59,7 +59,7 @@ static unsigned node_link_to_bus(unsigned node, unsigned link)
for (reg = 0xE0; reg < 0xF0; reg += 0x04) {
u32 config_map;
- config_map = pci_read_config32(PCI_DEV(0, 0x18, 1), reg);
+ config_map = pci_io_read_config32(PCI_DEV(0, 0x18, 1), reg);
if ((config_map & 3) != 3) {
continue;
}
@@ -76,7 +76,7 @@ static inline unsigned get_sblk(void)
{
u32 reg;
/* read PCI_DEV(0,0x18,0) 0x64 bit [8:9] to find out SbLink m */
- reg = pci_read_config32(PCI_DEV(0, 0x18, 0), 0x64);
+ reg = pci_io_read_config32(PCI_DEV(0, 0x18, 0), 0x64);
return ((reg>>8) & 3);
}
diff --git a/src/southbridge/amd/amd8111/reset.c b/src/southbridge/amd/amd8111/reset.c
index 3cc1a0a..fd2c82a 100644
--- a/src/southbridge/amd/amd8111/reset.c
+++ b/src/southbridge/amd/amd8111/reset.c
@@ -1,48 +1,33 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+
+#define __SIMPLE_DEVICE__
+
#include <arch/io.h>
#include <reset.h>
#include <device/pci_ids.h>
-#define PCI_DEV(BUS, DEV, FN) ( \
- (((BUS) & 0xFFF) << 20) | \
- (((DEV) & 0x1F) << 15) | \
- (((FN) & 0x7) << 12))
-
-#define PCI_ID(VENDOR_ID, DEVICE_ID) \
- ((((DEVICE_ID) & 0xFFFF) << 16) | ((VENDOR_ID) & 0xFFFF))
-
-static void pci_write_config8(pci_devfn_t dev, unsigned where, unsigned char value)
-{
- unsigned addr;
- addr = (dev>>4) | where;
- outl(0x80000000 | (addr & ~3), 0xCF8);
- outb(value, 0xCFC + (addr & 3));
-}
-
-static void pci_write_config32(pci_devfn_t dev, unsigned where, unsigned value)
-{
- unsigned addr;
- addr = (dev>>4) | where;
- outl(0x80000000 | (addr & ~3), 0xCF8);
- outl(value, 0xCFC);
-}
-
-static unsigned pci_read_config32(pci_devfn_t dev, unsigned where)
-{
- unsigned addr;
- addr = (dev>>4) | where;
- outl(0x80000000 | (addr & ~3), 0xCF8);
- return inl(0xCFC);
-}
#define PCI_DEV_INVALID (0xffffffffU)
-static pci_devfn_t pci_locate_device_on_bus(unsigned pci_id, unsigned bus)
+static pci_devfn_t pci_io_locate_device_on_bus(unsigned pci_id, unsigned bus)
{
pci_devfn_t dev, last;
dev = PCI_DEV(bus, 0, 0);
last = PCI_DEV(bus, 31, 7);
for (; dev <= last; dev += PCI_DEV(0,0,1)) {
unsigned int id;
- id = pci_read_config32(dev, 0);
+ id = pci_io_read_config32(dev, 0);
if (id == pci_id) {
return dev;
}
@@ -52,7 +37,6 @@ static pci_devfn_t pci_locate_device_on_bus(unsigned pci_id, unsigned bus)
#include "../../../northbridge/amd/amdk8/reset_test.c"
-
void hard_reset(void)
{
pci_devfn_t dev;
@@ -64,11 +48,11 @@ void hard_reset(void)
* There can only be one 8111 on a hypertransport chain/bus.
*/
bus = node_link_to_bus(node, link);
- dev = pci_locate_device_on_bus(
+ dev = pci_io_locate_device_on_bus(
PCI_ID(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8111_ISA),
bus);
/* Reset */
set_bios_reset();
- pci_write_config8(dev, 0x47, 1);
+ pci_io_write_config8(dev, 0x47, 1);
}
diff --git a/src/southbridge/broadcom/bcm5785/reset.c b/src/southbridge/broadcom/bcm5785/reset.c
index 82ff0fd..7511d29 100644
--- a/src/southbridge/broadcom/bcm5785/reset.c
+++ b/src/southbridge/broadcom/bcm5785/reset.c
@@ -14,30 +14,11 @@
* GNU General Public License for more details.
*/
+#define __SIMPLE_DEVICE__
+
#include <arch/io.h>
#include <reset.h>
-#define PCI_DEV(BUS, DEV, FN) ( \
- (((BUS) & 0xFFF) << 20) | \
- (((DEV) & 0x1F) << 15) | \
- (((FN) & 0x7) << 12))
-
-static void pci_write_config32(pci_devfn_t dev, unsigned where, unsigned value)
-{
- unsigned addr;
- addr = (dev>>4) | where;
- outl(0x80000000 | (addr & ~3), 0xCF8);
- outl(value, 0xCFC);
-}
-
-static unsigned pci_read_config32(pci_devfn_t dev, unsigned where)
-{
- unsigned addr;
- addr = (dev>>4) | where;
- outl(0x80000000 | (addr & ~3), 0xCF8);
- return inl(0xCFC);
-}
-
#include "../../../northbridge/amd/amdk8/reset_test.c"
void hard_reset(void)
diff --git a/src/southbridge/nvidia/ck804/reset.c b/src/southbridge/nvidia/ck804/reset.c
index 004ad58..ad994de 100644
--- a/src/southbridge/nvidia/ck804/reset.c
+++ b/src/southbridge/nvidia/ck804/reset.c
@@ -14,30 +14,11 @@
* GNU General Public License for more details.
*/
+#define __SIMPLE_DEVICE__
+
#include <arch/io.h>
#include <reset.h>
-#define PCI_DEV(BUS, DEV, FN) ( \
- (((BUS) & 0xFFF) << 20) | \
- (((DEV) & 0x1F) << 15) | \
- (((FN) & 0x7) << 12))
-
-static void pci_write_config32(pci_devfn_t dev, unsigned where, unsigned value)
-{
- unsigned addr;
- addr = (dev >> 4) | where;
- outl(0x80000000 | (addr & ~3), 0xCF8);
- outl(value, 0xCFC);
-}
-
-static unsigned pci_read_config32(pci_devfn_t dev, unsigned where)
-{
- unsigned addr;
- addr = (dev >> 4) | where;
- outl(0x80000000 | (addr & ~3), 0xCF8);
- return inl(0xCFC);
-}
-
#include "../../../northbridge/amd/amdk8/reset_test.c"
void hard_reset(void)
diff --git a/src/southbridge/nvidia/mcp55/reset.c b/src/southbridge/nvidia/mcp55/reset.c
index 12cac29..a381cd3 100644
--- a/src/southbridge/nvidia/mcp55/reset.c
+++ b/src/southbridge/nvidia/mcp55/reset.c
@@ -17,30 +17,11 @@
* GNU General Public License for more details.
*/
+#define __SIMPLE_DEVICE__
+
#include <arch/io.h>
#include <reset.h>
-#define PCI_DEV(BUS, DEV, FN) ( \
- (((BUS) & 0xFFF) << 20) | \
- (((DEV) & 0x1F) << 15) | \
- (((FN) & 0x7) << 12))
-
-static void pci_write_config32(pci_devfn_t dev, unsigned where, unsigned value)
-{
- unsigned addr;
- addr = (dev>>4) | where;
- outl(0x80000000 | (addr & ~3), 0xCF8);
- outl(value, 0xCFC);
-}
-
-static unsigned pci_read_config32(pci_devfn_t dev, unsigned where)
-{
- unsigned addr;
- addr = (dev>>4) | where;
- outl(0x80000000 | (addr & ~3), 0xCF8);
- return inl(0xCFC);
-}
-
#include "../../../northbridge/amd/amdk8/reset_test.c"
void hard_reset(void)
diff --git a/src/southbridge/sis/sis966/reset.c b/src/southbridge/sis/sis966/reset.c
index 12cac29..a381cd3 100644
--- a/src/southbridge/sis/sis966/reset.c
+++ b/src/southbridge/sis/sis966/reset.c
@@ -17,30 +17,11 @@
* GNU General Public License for more details.
*/
+#define __SIMPLE_DEVICE__
+
#include <arch/io.h>
#include <reset.h>
-#define PCI_DEV(BUS, DEV, FN) ( \
- (((BUS) & 0xFFF) << 20) | \
- (((DEV) & 0x1F) << 15) | \
- (((FN) & 0x7) << 12))
-
-static void pci_write_config32(pci_devfn_t dev, unsigned where, unsigned value)
-{
- unsigned addr;
- addr = (dev>>4) | where;
- outl(0x80000000 | (addr & ~3), 0xCF8);
- outl(value, 0xCFC);
-}
-
-static unsigned pci_read_config32(pci_devfn_t dev, unsigned where)
-{
- unsigned addr;
- addr = (dev>>4) | where;
- outl(0x80000000 | (addr & ~3), 0xCF8);
- return inl(0xCFC);
-}
-
#include "../../../northbridge/amd/amdk8/reset_test.c"
void hard_reset(void)
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