[coreboot-gerrit] Patch set updated for coreboot: mb/roda/rv11: Add new boards Lizard RV11 and RW11
Nico Huber (nico.h@gmx.de)
gerrit at coreboot.org
Sun Dec 11 02:09:20 CET 2016
Nico Huber (nico.h at gmx.de) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17446
-gerrit
commit 11dba1b13ed40b034058c199c683389d2fac55a0
Author: Dennis Wassenberg <dennis.wassenberg at secunet.com>
Date: Thu Sep 10 12:20:58 2015 +0200
mb/roda/rv11: Add new boards Lizard RV11 and RW11
The Roda Lizard RV11 is a comparatively lightweight, full-rugged
notebook. It's based on a 17W TDP dual core Ivy Bridge CPU.
The Lizard RW11 is its bigger brother (45W TDP quad core, more i/o
options).
The RV11 is the first board to use the native graphics initialization
by libgfxinit. Tested so far, are the internal eDP port, DP and VGA.
Change-Id: Iea283059ce3402dc36184baf16928b55285a9eeb
Signed-off-by: Dennis Wassenberg <dennis.wassenberg at secunet.com>
Signed-off-by: Nico Huber <nico.huber at secunet.com>
---
src/mainboard/roda/rv11/Kconfig | 74 ++++
src/mainboard/roda/rv11/Kconfig.name | 5 +
src/mainboard/roda/rv11/Makefile.inc | 23 ++
src/mainboard/roda/rv11/acpi/alsd.asl | 67 +++
src/mainboard/roda/rv11/acpi/ec.asl | 17 +
src/mainboard/roda/rv11/acpi/mainboard.asl | 21 +
src/mainboard/roda/rv11/acpi/platform.asl | 30 ++
src/mainboard/roda/rv11/acpi/thermal.asl | 142 +++++++
src/mainboard/roda/rv11/acpi_tables.c | 35 ++
src/mainboard/roda/rv11/board_info.txt | 5 +
src/mainboard/roda/rv11/cmos.layout | 132 ++++++
src/mainboard/roda/rv11/dsdt.asl | 53 +++
src/mainboard/roda/rv11/gpio.c | 453 +++++++++++++++++++++
src/mainboard/roda/rv11/hda_verb.c | 31 ++
src/mainboard/roda/rv11/romstage.c | 38 ++
.../roda/rv11/variants/rv11/devicetree.cb | 116 ++++++
.../roda/rv11/variants/rv11/gma-mainboard.ads | 9 +
.../rv11/include/acpi/brightness_levels.asl | 19 +
.../rv11/variants/rv11/include/acpi/superio.asl | 1 +
.../rv11/variants/rv11/include/variant/hda_verb.h | 67 +++
.../rv11/variants/rv11/include/variant/thermal.h | 17 +
src/mainboard/roda/rv11/variants/rv11/romstage.c | 115 ++++++
.../roda/rv11/variants/rw11/devicetree.cb | 178 ++++++++
.../roda/rv11/variants/rw11/gma-mainboard.ads | 20 +
.../rw11/include/acpi/brightness_levels.asl | 19 +
.../rv11/variants/rw11/include/acpi/superio.asl | 30 ++
.../rv11/variants/rw11/include/variant/hda_verb.h | 67 +++
.../rv11/variants/rw11/include/variant/thermal.h | 17 +
src/mainboard/roda/rv11/variants/rw11/romstage.c | 145 +++++++
29 files changed, 1946 insertions(+)
diff --git a/src/mainboard/roda/rv11/Kconfig b/src/mainboard/roda/rv11/Kconfig
new file mode 100644
index 0000000..d6cb6bd
--- /dev/null
+++ b/src/mainboard/roda/rv11/Kconfig
@@ -0,0 +1,74 @@
+if BOARD_RODA_RV11 || BOARD_RODA_RW11
+
+config BOARD_SPECIFIC_OPTIONS # dummy
+ def_bool y
+ select SYSTEM_TYPE_LAPTOP
+ select CPU_INTEL_SOCKET_RPGA989
+ select NORTHBRIDGE_INTEL_IVYBRIDGE
+ select SOUTHBRIDGE_INTEL_C216
+ select BOARD_ROMSIZE_KB_16384
+ select HAVE_ACPI_TABLES
+ select HAVE_OPTION_TABLE
+ select HAVE_ACPI_RESUME
+ select ENABLE_VMX
+ select EC_RODA_IT8518
+ select SERIRQ_CONTINUOUS_MODE
+ select MAINBOARD_HAS_LIBGFXINIT
+ select SUPERIO_ITE_IT8783EF if BOARD_RODA_RW11
+
+config MAINBOARD_DIR
+ string
+ default "roda/rv11"
+
+config VARIANT_DIR
+ string
+ default "rv11" if BOARD_RODA_RV11
+ default "rw11" if BOARD_RODA_RW11
+
+config DEVICETREE
+ string
+ default "variants/rv11/devicetree.cb" if BOARD_RODA_RV11
+ default "variants/rw11/devicetree.cb" if BOARD_RODA_RW11
+
+config MAINBOARD_PART_NUMBER
+ string
+ default "Lizard RW11" if BOARD_RODA_RW11
+ default "Lizard RV11"
+
+config MMCONF_BASE_ADDRESS
+ hex
+ default 0xf8000000 if USE_NATIVE_RAMINIT
+
+config MAX_CPUS
+ int
+ default 8
+
+config MAINBOARD_VENDOR
+ string
+ default "Roda"
+
+config HAVE_IFD_BIN
+ bool
+ default n
+
+config HAVE_ME_BIN
+ bool
+ default n
+
+config HAVE_GBE_BIN
+ bool
+ default n
+
+config IFD_BIOS_SECTION
+ string
+ default "0x00d80000:0x00ffffff"
+
+config IFD_ME_SECTION
+ string
+ default "0x00003000:0x00d7ffff"
+
+config IFD_GBE_SECTION
+ string
+ default "0x00001000:0x00002fff"
+
+endif # BOARD_RODA_RV11 || BOARD_RODA_RW11
diff --git a/src/mainboard/roda/rv11/Kconfig.name b/src/mainboard/roda/rv11/Kconfig.name
new file mode 100644
index 0000000..5feaecb
--- /dev/null
+++ b/src/mainboard/roda/rv11/Kconfig.name
@@ -0,0 +1,5 @@
+config BOARD_RODA_RV11
+ bool "Lizard RV11"
+
+config BOARD_RODA_RW11
+ bool "Lizard RW11"
diff --git a/src/mainboard/roda/rv11/Makefile.inc b/src/mainboard/roda/rv11/Makefile.inc
new file mode 100644
index 0000000..4df0952
--- /dev/null
+++ b/src/mainboard/roda/rv11/Makefile.inc
@@ -0,0 +1,23 @@
+##
+## This file is part of the coreboot project.
+##
+## Copyright (C) 2015-2016 secunet Security Networks AG
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; version 2 of the License.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+## GNU General Public License for more details.
+##
+
+romstage-y += gpio.c
+
+VARIANT_DIR := variants/$(call strip_quotes,$(CONFIG_VARIANT_DIR))
+
+romstage-y += $(VARIANT_DIR)/romstage.c
+ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += $(VARIANT_DIR)/gma-mainboard.ads
+
+CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/$(VARIANT_DIR)/include
diff --git a/src/mainboard/roda/rv11/acpi/alsd.asl b/src/mainboard/roda/rv11/acpi/alsd.asl
new file mode 100644
index 0000000..120332d
--- /dev/null
+++ b/src/mainboard/roda/rv11/acpi/alsd.asl
@@ -0,0 +1,67 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2015 secunet Security Networks AG
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+Device (ALSD)
+{
+ Name (_HID, "ACPI0008") // _HID: Hardware ID
+ Method (_STA, 0, NotSerialized) // _STA: Status
+ {
+ Return (0x0F)
+ }
+
+ Method (_ALI, 0, NotSerialized) // _ALI: Ambient Light Illuminance
+ {
+ Store (\_SB.PCI0.LPCB.EC0.LUXH, Local0)
+ Or (ShiftLeft (Local0, 8), \_SB.PCI0.LPCB.EC0.LUXL, Local0)
+ Store ("-----> _ALI: ", Debug)
+ Store (Local0, Debug)
+ Store (\_SB.PCI0.LPCB.EC0.LUXH, Debug)
+ Store (\_SB.PCI0.LPCB.EC0.LUXL, Debug)
+ Return (Local0)
+ }
+
+ Name (_ALR, Package (0x05) // _ALR: Ambient Light Response
+ {
+ Package (0x02)
+ {
+ 0x46,
+ Zero
+ },
+
+ Package (0x02)
+ {
+ 0x49,
+ 0x0A
+ },
+
+ Package (0x02)
+ {
+ 0x55,
+ 0x50
+ },
+
+ Package (0x02)
+ {
+ 0x64,
+ 0x012C
+ },
+
+ Package (0x02)
+ {
+ 0x96,
+ 0x03E8
+ }
+ })
+}
diff --git a/src/mainboard/roda/rv11/acpi/ec.asl b/src/mainboard/roda/rv11/acpi/ec.asl
new file mode 100644
index 0000000..a1bcbb1
--- /dev/null
+++ b/src/mainboard/roda/rv11/acpi/ec.asl
@@ -0,0 +1,17 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2015 secunet Security Networks AG
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#define EC_SCI_GPI 7
+#include <ec/roda/it8518/acpi/ec.asl>
diff --git a/src/mainboard/roda/rv11/acpi/mainboard.asl b/src/mainboard/roda/rv11/acpi/mainboard.asl
new file mode 100644
index 0000000..a91c5d6
--- /dev/null
+++ b/src/mainboard/roda/rv11/acpi/mainboard.asl
@@ -0,0 +1,21 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2015 secunet Security Networks AG
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+Scope (\_SB) {
+ Device (PWRB)
+ {
+ Name (_HID, EisaId("PNP0C0C"))
+ }
+}
diff --git a/src/mainboard/roda/rv11/acpi/platform.asl b/src/mainboard/roda/rv11/acpi/platform.asl
new file mode 100644
index 0000000..df21c8c
--- /dev/null
+++ b/src/mainboard/roda/rv11/acpi/platform.asl
@@ -0,0 +1,30 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2015 secunet Security Networks AG
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+/* The _PTS method (Prepare To Sleep) is called before the OS is
+ * entering a sleep state. The sleep state number is passed in Arg0
+ */
+
+Method(_PTS,1)
+{
+
+}
+
+/* The _WAK method is called on system wakeup */
+
+Method(_WAK,1)
+{
+ Return(Package(){0,0})
+}
diff --git a/src/mainboard/roda/rv11/acpi/thermal.asl b/src/mainboard/roda/rv11/acpi/thermal.asl
new file mode 100644
index 0000000..b87fc4f
--- /dev/null
+++ b/src/mainboard/roda/rv11/acpi/thermal.asl
@@ -0,0 +1,142 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2015-2016 secunet Security Networks AG
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+// Thermal Zone
+
+Scope (\_TZ)
+{
+ // Convert from Degrees C to 1/10 Kelvin for ACPI
+ Method (CTOK, 1) {
+ // 10th of Degrees C
+ Multiply (Arg0, 10, Local0)
+
+ // Convert to Kelvin
+ Add (Local0, 2732, Local0)
+
+ Return (Local0)
+ }
+
+ ThermalZone (THRM)
+ {
+ Name (_TC1, 0x02)
+ Name (_TC2, 0x05)
+
+ // Thermal zone polling frequency: 10 seconds
+ Name (_TZP, 100)
+
+ // Thermal sampling period for passive cooling: 2 seconds
+ Name (_TSP, 20)
+
+ // Threshold for OS to shutdown
+ Method (_CRT, 0, Serialized)
+ {
+ Return (CTOK (\TCRT))
+ }
+
+ // Threshold for passive cooling
+ Method (_PSV, 0, Serialized)
+ {
+ Return (CTOK (\TPSV))
+ }
+
+ // Processors used for passive cooling
+ Method (_PSL, 0, Serialized)
+ {
+ Return (\PPKG ())
+ }
+
+ Method (_TMP, 0, NotSerialized) // _TMP: Temperature
+ {
+ Store (\_SB.PCI0.LPCB.EC0.CPUT, Local0)
+
+ If (Local0 >= 0x80)
+ {
+ Store ("-----> CPU Temperature (INVALID): ", Debug)
+ Store (Local0, Debug)
+ Return (CTOK (0))
+ }
+
+ Store ("-----> CPU Temperature: ", Debug)
+ Store (Local0, Debug)
+
+ Return (CTOK (Local0))
+ }
+
+ }
+
+ ThermalZone (TZ00)
+ {
+ // Thermal zone polling frequency: 10 seconds
+ Name (_TZP, 100)
+
+ // Thermal sampling period for passive cooling: 2 seconds
+ Name (_TSP, 20)
+
+ // Threshold for OS to shutdown
+ Method (_CRT, 0, Serialized)
+ {
+ Return (CTOK (106))
+ }
+
+ Method (_TMP, 0, NotSerialized) // _TMP: Temperature
+ {
+ Store (\_SB.PCI0.LPCB.EC0.LOCT, Local0)
+
+ If (Local0 >= 0x80)
+ {
+ Store ("-----> LOC Temperature (INVALID): ", Debug)
+ Store (Local0, Debug)
+ Return (CTOK (0))
+ }
+
+ Store ("-----> LOC Temperature: ", Debug)
+ Store (Local0, Debug)
+
+ Return (CTOK (Local0))
+ }
+ }
+
+ ThermalZone (TZ01)
+ {
+ // Thermal zone polling frequency: 10 seconds
+ Name (_TZP, 100)
+
+ // Thermal sampling period for passive cooling: 2 seconds
+ Name (_TSP, 20)
+
+ // Threshold for OS to shutdown
+ Method (_CRT, 0, Serialized)
+ {
+ Return (CTOK (106))
+ }
+
+ Method (_TMP, 0, NotSerialized) // _TMP: Temperature
+ {
+ Store (\_SB.PCI0.LPCB.EC0.OEMT, Local0)
+
+ If (Local0 >= 0x80)
+ {
+ Store ("-----> OEM Temperature (INVALID): ", Debug)
+ Store (Local0, Debug)
+ Return (CTOK (0))
+ }
+
+ Store ("-----> OEM Temperature: ", Debug)
+ Store (Local0, Debug)
+
+ Return (CTOK (Local0))
+ }
+ }
+}
diff --git a/src/mainboard/roda/rv11/acpi_tables.c b/src/mainboard/roda/rv11/acpi_tables.c
new file mode 100644
index 0000000..35d28b5
--- /dev/null
+++ b/src/mainboard/roda/rv11/acpi_tables.c
@@ -0,0 +1,35 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2016 secunet Security Networks AG
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <southbridge/intel/bd82x6x/nvs.h>
+
+#include <variant/thermal.h>
+
+void acpi_create_gnvs(global_nvs_t *gnvs)
+{
+ /* Disable USB ports in S3 by default */
+ gnvs->s3u0 = 0;
+ gnvs->s3u1 = 0;
+
+ /* Disable USB ports in S5 by default */
+ gnvs->s5u0 = 0;
+ gnvs->s5u1 = 0;
+
+ /* The lid is open by default */
+ gnvs->lids = 1;
+
+ gnvs->tcrt = CRITICAL_TEMPERATURE;
+ gnvs->tpsv = PASSIVE_TEMPERATURE;
+}
diff --git a/src/mainboard/roda/rv11/board_info.txt b/src/mainboard/roda/rv11/board_info.txt
new file mode 100644
index 0000000..689ca8f
--- /dev/null
+++ b/src/mainboard/roda/rv11/board_info.txt
@@ -0,0 +1,5 @@
+Category: laptop
+ROM package: SOIC-8
+ROM protocol: SPI
+ROM socketed: n
+Flashrom support: n
diff --git a/src/mainboard/roda/rv11/cmos.layout b/src/mainboard/roda/rv11/cmos.layout
new file mode 100644
index 0000000..588a3c3
--- /dev/null
+++ b/src/mainboard/roda/rv11/cmos.layout
@@ -0,0 +1,132 @@
+##
+## This file is part of the coreboot project.
+##
+## Copyright (C) 2007-2008 coresystems GmbH
+## Copyright (C) 2015 secunet Security Networks AG
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; version 2 of the License.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+## GNU General Public License for more details.
+##
+
+# -----------------------------------------------------------------
+entries
+
+# -----------------------------------------------------------------
+# Status Register A
+# -----------------------------------------------------------------
+# Status Register B
+# -----------------------------------------------------------------
+# Status Register C
+#96 4 r 0 status_c_rsvd
+#100 1 r 0 uf_flag
+#101 1 r 0 af_flag
+#102 1 r 0 pf_flag
+#103 1 r 0 irqf_flag
+# -----------------------------------------------------------------
+# Status Register D
+#104 7 r 0 status_d_rsvd
+#111 1 r 0 valid_cmos_ram
+# -----------------------------------------------------------------
+# Diagnostic Status Register
+#112 8 r 0 diag_rsvd1
+
+# -----------------------------------------------------------------
+0 120 r 0 reserved_memory
+#120 264 r 0 unused
+
+# -----------------------------------------------------------------
+# RTC_BOOT_BYTE (coreboot hardcoded)
+384 1 e 3 boot_option
+385 3 r 0 reserved
+388 4 h 0 reboot_counter
+
+# -----------------------------------------------------------------
+# coreboot config options: console
+392 3 e 4 baud_rate
+395 4 e 5 debug_level
+#399 1 r 0 unused
+
+# coreboot config options: cpu
+400 1 e 2 hyper_threading
+401 3 e 9 gfx_uma_size
+
+#404 4 r 0 unused
+
+# coreboot config options: southbridge
+408 1 e 1 nmi
+#409 2 r 0 unused
+411 1 e 8 sata_mode
+#412 4 r 0 unused
+
+# coreboot config options: bootloader
+416 424 s 0 boot_devices
+840 8 h 0 boot_default
+848 1 e 7 cmos_defaults_loaded
+#851 5 r 0 unused
+
+# coreboot config options: mainboard specific options
+#856 40 r 0 unused
+
+# SandyBridge MRC Scrambler Seed values
+896 32 r 0 mrc_scrambler_seed
+928 32 r 0 mrc_scrambler_seed_s3
+960 16 r 0 mrc_scrambler_seed_chk
+#976 8 r 0 unused
+
+# coreboot config options: check sums
+984 16 h 0 check_sum
+#1000 24 r 0 amd_reserved
+
+# -----------------------------------------------------------------
+
+enumerations
+
+#ID value text
+1 0 Disable
+1 1 Enable
+2 0 Enable
+2 1 Disable
+3 0 Fallback
+3 1 Normal
+4 0 115200
+4 1 57600
+4 2 38400
+4 3 19200
+4 4 9600
+4 5 4800
+4 6 2400
+4 7 1200
+5 1 Emergency
+5 2 Alert
+5 3 Critical
+5 4 Error
+5 5 Warning
+5 6 Notice
+5 7 Info
+5 8 Debug
+5 9 Spew
+6 0 Disable
+6 1 Enable
+6 2 Keep
+7 0 No
+7 1 Yes
+8 0 AHCI
+8 1 Compatible
+9 0 32M
+9 1 64M
+9 2 96M
+9 3 128M
+9 4 160M
+9 5 192M
+9 6 224M
+
+# -----------------------------------------------------------------
+checksums
+
+checksum 392 895 984
diff --git a/src/mainboard/roda/rv11/dsdt.asl b/src/mainboard/roda/rv11/dsdt.asl
new file mode 100644
index 0000000..18fb1ca
--- /dev/null
+++ b/src/mainboard/roda/rv11/dsdt.asl
@@ -0,0 +1,53 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2016 secunet Security Networks AG
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+DefinitionBlock(
+ "dsdt.aml",
+ "DSDT",
+ 0x03, // DSDT revision: ACPI v3.0
+ "COREv4", // OEM id
+ "COREBOOT", // OEM table id
+ 0x20141018 // OEM revision
+)
+{
+ #include <southbridge/intel/bd82x6x/acpi/platform.asl>
+
+ // Some generic macros
+ #include "acpi/platform.asl"
+ #include "acpi/mainboard.asl"
+
+ // global NVS and variables
+ #include <southbridge/intel/bd82x6x/acpi/globalnvs.asl>
+
+ #include "acpi/thermal.asl"
+
+ #include "acpi/alsd.asl"
+
+ #include <cpu/intel/model_206ax/acpi/cpu.asl>
+
+ Scope (\_SB) {
+ Device (PCI0)
+ {
+ #include <northbridge/intel/sandybridge/acpi/sandybridge.asl>
+ #include <southbridge/intel/bd82x6x/acpi/pch.asl>
+ #include <southbridge/intel/bd82x6x/acpi/default_irq_route.asl>
+
+ #include <acpi/brightness_levels.asl>
+ }
+ }
+
+ /* Chipset specific sleep states */
+ #include <southbridge/intel/bd82x6x/acpi/sleepstates.asl>
+}
diff --git a/src/mainboard/roda/rv11/gpio.c b/src/mainboard/roda/rv11/gpio.c
new file mode 100644
index 0000000..dd9e19e
--- /dev/null
+++ b/src/mainboard/roda/rv11/gpio.c
@@ -0,0 +1,453 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2015 secunet Security Networks AG
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <southbridge/intel/common/gpio.h>
+
+/*
+ * TODO: Investigate somehow... Current values are taken from a running
+ * system with vendor supplied firmware.
+ */
+const struct pch_gpio_set1 pch_gpio_set1_mode = {
+ .gpio0 = GPIO_MODE_GPIO, /* strap */
+ .gpio1 = GPIO_MODE_GPIO, /* EC SMI# */
+ .gpio2 = GPIO_MODE_GPIO, /* strap */
+ .gpio3 = GPIO_MODE_GPIO, /* strapped weak high */
+ .gpio4 = GPIO_MODE_GPIO, /* DDR3 thermal ALERT# */
+ .gpio5 = GPIO_MODE_GPIO, /* DDR3 thermal THERM# */
+ .gpio6 = GPIO_MODE_GPIO, /* DGPU hotplug? */
+ .gpio7 = GPIO_MODE_GPIO, /* EC SCI# */
+ .gpio8 = GPIO_MODE_GPIO, /* strap */
+ .gpio9 = GPIO_MODE_NATIVE, /* USB OC #5 */
+ .gpio10 = GPIO_MODE_NATIVE, /* USB OC #6; strapped weak high */
+ .gpio11 = GPIO_MODE_GPIO, /* strapped weak high */
+ .gpio12 = GPIO_MODE_NATIVE, /* LAN PHY Power Control */
+ .gpio13 = GPIO_MODE_NATIVE, /* HDA Audio Dock Reset */
+ .gpio14 = GPIO_MODE_GPIO, /* EC wake SCI# */
+ .gpio15 = GPIO_MODE_GPIO, /* strapped high */
+ .gpio16 = GPIO_MODE_NATIVE, /* SATA 4 GP */
+ .gpio17 = GPIO_MODE_GPIO, /* strapped weak low */
+ .gpio18 = GPIO_MODE_NATIVE, /* PCIe clock request 1 */
+ .gpio19 = GPIO_MODE_NATIVE, /* SATA 9 GP */
+ .gpio20 = GPIO_MODE_NATIVE, /* PCIe clock request 2 */
+ .gpio21 = GPIO_MODE_NATIVE, /* SATA 0 GP */
+ .gpio22 = GPIO_MODE_GPIO, /* strap */
+ .gpio23 = GPIO_MODE_NATIVE, /* LPC DMA request 1; strapped weak high */
+ .gpio24 = GPIO_MODE_GPIO, /* strapped weak high */
+ .gpio25 = GPIO_MODE_NATIVE, /* PCIe clock request 3 */
+ .gpio26 = GPIO_MODE_NATIVE, /* PCIe clock request 4 */
+ .gpio27 = GPIO_MODE_GPIO, /* SATA power (active low) */
+ .gpio28 = GPIO_MODE_GPIO, /* PCH strap ODVR, Output LOW */
+ .gpio29 = GPIO_MODE_GPIO, /* Sleep LAN power (sleep low) */
+ .gpio30 = GPIO_MODE_NATIVE, /* Suspend Warning */
+ .gpio31 = GPIO_MODE_NATIVE, /* AC present */
+};
+
+const struct pch_gpio_set1 pch_gpio_set1_direction = {
+ .gpio0 = GPIO_DIR_INPUT, /* Unknown Input */
+ .gpio1 = GPIO_DIR_INPUT, /* Unknown Input */
+ .gpio2 = GPIO_DIR_INPUT, /* Unknown Input */
+ .gpio3 = GPIO_DIR_INPUT, /* Unknown Input */
+ .gpio4 = GPIO_DIR_INPUT, /* Unknown Input */
+ .gpio5 = GPIO_DIR_INPUT, /* Unknown Input */
+ .gpio6 = GPIO_DIR_INPUT, /* Unknown Input */
+ .gpio7 = GPIO_DIR_INPUT, /* Unknown Input */
+ .gpio8 = GPIO_DIR_OUTPUT, /* Unknown Output HIGH */
+ .gpio9 = GPIO_DIR_INPUT, /* Native */
+ .gpio10 = GPIO_DIR_INPUT, /* Native */
+ .gpio11 = GPIO_DIR_INPUT, /* Unknown Input */
+ .gpio12 = GPIO_DIR_INPUT, /* Native */
+ .gpio13 = GPIO_DIR_INPUT, /* Native */
+ .gpio14 = GPIO_DIR_INPUT, /* Unknown Input */
+ .gpio15 = GPIO_DIR_INPUT, /* Unknown Input */
+ .gpio16 = GPIO_DIR_INPUT, /* Native */
+ .gpio17 = GPIO_DIR_INPUT, /* Unknown Input */
+ .gpio18 = GPIO_DIR_INPUT, /* Native */
+ .gpio19 = GPIO_DIR_INPUT, /* Native */
+ .gpio20 = GPIO_DIR_INPUT, /* Native */
+ .gpio21 = GPIO_DIR_INPUT, /* Native */
+ .gpio22 = GPIO_DIR_INPUT, /* Unknown Input */
+ .gpio23 = GPIO_DIR_INPUT, /* Native */
+ .gpio24 = GPIO_DIR_INPUT, /* Unknown Input */
+ .gpio25 = GPIO_DIR_INPUT, /* Native */
+ .gpio26 = GPIO_DIR_INPUT, /* Native */
+ .gpio27 = GPIO_DIR_OUTPUT, /* Unknown Output LOW */
+ .gpio28 = GPIO_DIR_OUTPUT, /* Unknown Output LOW */
+ .gpio29 = GPIO_DIR_OUTPUT, /* Unknown Output HIGH */
+ .gpio30 = GPIO_DIR_INPUT, /* Native */
+ .gpio31 = GPIO_DIR_INPUT, /* Native */
+};
+
+const struct pch_gpio_set1 pch_gpio_set1_level = {
+ .gpio0 = GPIO_LEVEL_LOW, /* Unknown Input */
+ .gpio1 = GPIO_LEVEL_LOW, /* Unknown Input */
+ .gpio2 = GPIO_LEVEL_LOW, /* Unknown Input */
+ .gpio3 = GPIO_LEVEL_LOW, /* Unknown Input */
+ .gpio4 = GPIO_LEVEL_LOW, /* Unknown Input */
+ .gpio5 = GPIO_LEVEL_LOW, /* Unknown Input */
+ .gpio6 = GPIO_LEVEL_LOW, /* Unknown Input */
+ .gpio7 = GPIO_LEVEL_LOW, /* Unknown Input */
+ .gpio8 = GPIO_LEVEL_HIGH, /* Unknown Output HIGH */
+ .gpio9 = GPIO_LEVEL_LOW, /* Native */
+ .gpio10 = GPIO_LEVEL_LOW, /* Native */
+ .gpio11 = GPIO_LEVEL_LOW, /* Unknown Input */
+ .gpio12 = GPIO_LEVEL_LOW, /* Native */
+ .gpio13 = GPIO_LEVEL_LOW, /* Native */
+ .gpio14 = GPIO_LEVEL_LOW, /* Unknown Input */
+ .gpio15 = GPIO_LEVEL_LOW, /* Unknown Input */
+ .gpio16 = GPIO_LEVEL_LOW, /* Native */
+ .gpio17 = GPIO_LEVEL_LOW, /* Unknown Input */
+ .gpio18 = GPIO_LEVEL_LOW, /* Native */
+ .gpio19 = GPIO_LEVEL_LOW, /* Native */
+ .gpio20 = GPIO_LEVEL_LOW, /* Native */
+ .gpio21 = GPIO_LEVEL_LOW, /* Native */
+ .gpio22 = GPIO_LEVEL_LOW, /* Unknown Input */
+ .gpio23 = GPIO_LEVEL_LOW, /* Native */
+ .gpio24 = GPIO_LEVEL_LOW, /* Unknown Input */
+ .gpio25 = GPIO_LEVEL_LOW, /* Native */
+ .gpio26 = GPIO_LEVEL_LOW, /* Native */
+ .gpio27 = GPIO_LEVEL_LOW, /* Unknown Output LOW */
+ .gpio28 = GPIO_LEVEL_LOW, /* Unknown Output LOW */
+ .gpio29 = GPIO_LEVEL_HIGH, /* Unknown Output HIGH */
+ .gpio30 = GPIO_LEVEL_LOW, /* Native */
+ .gpio31 = GPIO_LEVEL_LOW, /* Native */
+};
+
+const struct pch_gpio_set1 pch_gpio_set1_reset = {
+ .gpio0 = GPIO_RESET_PWROK,
+ .gpio1 = GPIO_RESET_PWROK,
+ .gpio2 = GPIO_RESET_PWROK,
+ .gpio3 = GPIO_RESET_PWROK,
+ .gpio4 = GPIO_RESET_PWROK,
+ .gpio5 = GPIO_RESET_PWROK,
+ .gpio6 = GPIO_RESET_PWROK,
+ .gpio7 = GPIO_RESET_PWROK,
+ .gpio8 = GPIO_RESET_PWROK,
+ .gpio9 = GPIO_RESET_PWROK,
+ .gpio10 = GPIO_RESET_PWROK,
+ .gpio11 = GPIO_RESET_PWROK,
+ .gpio12 = GPIO_RESET_PWROK,
+ .gpio13 = GPIO_RESET_PWROK,
+ .gpio14 = GPIO_RESET_PWROK,
+ .gpio15 = GPIO_RESET_PWROK,
+ .gpio16 = GPIO_RESET_PWROK,
+ .gpio17 = GPIO_RESET_PWROK,
+ .gpio18 = GPIO_RESET_PWROK,
+ .gpio19 = GPIO_RESET_PWROK,
+ .gpio20 = GPIO_RESET_PWROK,
+ .gpio21 = GPIO_RESET_PWROK,
+ .gpio22 = GPIO_RESET_PWROK,
+ .gpio23 = GPIO_RESET_PWROK,
+ .gpio24 = GPIO_RESET_PWROK,
+ .gpio25 = GPIO_RESET_PWROK,
+ .gpio26 = GPIO_RESET_PWROK,
+ .gpio27 = GPIO_RESET_PWROK,
+ .gpio28 = GPIO_RESET_PWROK,
+ .gpio29 = GPIO_RESET_PWROK,
+ .gpio30 = GPIO_RESET_RSMRST,
+ .gpio31 = GPIO_RESET_PWROK,
+};
+
+const struct pch_gpio_set1 pch_gpio_set1_invert = {
+ .gpio0 = GPIO_NO_INVERT,
+ .gpio1 = GPIO_INVERT,
+ .gpio2 = GPIO_NO_INVERT,
+ .gpio3 = GPIO_INVERT,
+ .gpio4 = GPIO_NO_INVERT,
+ .gpio5 = GPIO_NO_INVERT,
+ .gpio6 = GPIO_NO_INVERT,
+ .gpio7 = GPIO_INVERT,
+ .gpio8 = GPIO_NO_INVERT,
+ .gpio9 = GPIO_NO_INVERT,
+ .gpio10 = GPIO_NO_INVERT,
+ .gpio11 = GPIO_NO_INVERT,
+ .gpio12 = GPIO_NO_INVERT,
+ .gpio13 = GPIO_NO_INVERT,
+ .gpio14 = GPIO_INVERT,
+ .gpio15 = GPIO_INVERT,
+ .gpio16 = GPIO_NO_INVERT,
+ .gpio17 = GPIO_NO_INVERT,
+ .gpio18 = GPIO_NO_INVERT,
+ .gpio19 = GPIO_NO_INVERT,
+ .gpio20 = GPIO_NO_INVERT,
+ .gpio21 = GPIO_NO_INVERT,
+ .gpio22 = GPIO_NO_INVERT,
+ .gpio23 = GPIO_NO_INVERT,
+ .gpio24 = GPIO_NO_INVERT,
+ .gpio25 = GPIO_NO_INVERT,
+ .gpio26 = GPIO_NO_INVERT,
+ .gpio27 = GPIO_NO_INVERT,
+ .gpio28 = GPIO_NO_INVERT,
+ .gpio29 = GPIO_NO_INVERT,
+ .gpio30 = GPIO_NO_INVERT,
+ .gpio31 = GPIO_NO_INVERT,
+};
+
+const struct pch_gpio_set1 pch_gpio_set1_blink = {
+ .gpio0 = GPIO_NO_BLINK,
+ .gpio1 = GPIO_NO_BLINK,
+ .gpio2 = GPIO_NO_BLINK,
+ .gpio3 = GPIO_NO_BLINK,
+ .gpio4 = GPIO_NO_BLINK,
+ .gpio5 = GPIO_NO_BLINK,
+ .gpio6 = GPIO_NO_BLINK,
+ .gpio7 = GPIO_NO_BLINK,
+ .gpio8 = GPIO_NO_BLINK,
+ .gpio9 = GPIO_NO_BLINK,
+ .gpio10 = GPIO_NO_BLINK,
+ .gpio11 = GPIO_NO_BLINK,
+ .gpio12 = GPIO_NO_BLINK,
+ .gpio13 = GPIO_NO_BLINK,
+ .gpio14 = GPIO_NO_BLINK,
+ .gpio15 = GPIO_NO_BLINK,
+ .gpio16 = GPIO_NO_BLINK,
+ .gpio17 = GPIO_NO_BLINK,
+ .gpio18 = GPIO_NO_BLINK,
+ .gpio19 = GPIO_NO_BLINK,
+ .gpio20 = GPIO_NO_BLINK,
+ .gpio21 = GPIO_NO_BLINK,
+ .gpio22 = GPIO_NO_BLINK,
+ .gpio23 = GPIO_NO_BLINK,
+ .gpio24 = GPIO_NO_BLINK,
+ .gpio25 = GPIO_NO_BLINK,
+ .gpio26 = GPIO_NO_BLINK,
+ .gpio27 = GPIO_NO_BLINK,
+ .gpio28 = GPIO_NO_BLINK,
+ .gpio29 = GPIO_NO_BLINK,
+ .gpio30 = GPIO_NO_BLINK,
+ .gpio31 = GPIO_NO_BLINK,
+};
+
+const struct pch_gpio_set2 pch_gpio_set2_mode = {
+ .gpio32 = GPIO_MODE_NATIVE, /* Native */
+ .gpio33 = GPIO_MODE_NATIVE, /* Native */
+ .gpio34 = GPIO_MODE_GPIO, /* Unknown Output LOW */
+ .gpio35 = GPIO_MODE_NATIVE, /* Native */
+ .gpio36 = GPIO_MODE_NATIVE, /* Native */
+ .gpio37 = GPIO_MODE_GPIO, /* Unknown Output LOW */
+ .gpio38 = GPIO_MODE_GPIO, /* Unknown Input */
+ .gpio39 = GPIO_MODE_GPIO, /* Unknown Input */
+ .gpio40 = GPIO_MODE_NATIVE, /* USB OC #1 */
+ .gpio41 = GPIO_MODE_NATIVE, /* USB OC #2 */
+ .gpio42 = GPIO_MODE_NATIVE, /* USB OC #3 */
+ .gpio43 = GPIO_MODE_NATIVE, /* USB OC #4 */
+ .gpio44 = GPIO_MODE_NATIVE, /* Native */
+ .gpio45 = GPIO_MODE_NATIVE, /* Native */
+ .gpio46 = GPIO_MODE_GPIO, /* Unknown Output HIGH */
+ .gpio47 = GPIO_MODE_NATIVE, /* Native */
+ .gpio48 = GPIO_MODE_GPIO, /* Unknown Input */
+ .gpio49 = GPIO_MODE_GPIO, /* Unknown Input */
+ .gpio50 = GPIO_MODE_GPIO, /* Unknown Output HIGH */
+ .gpio51 = GPIO_MODE_GPIO, /* Unknown Output HIGH */
+ .gpio52 = GPIO_MODE_GPIO, /* Unknown Output HIGH */
+ .gpio53 = GPIO_MODE_GPIO, /* Unknown Output HIGH */
+ .gpio54 = GPIO_MODE_GPIO, /* Unknown Output HIGH */
+ .gpio55 = GPIO_MODE_GPIO, /* Unknown Output LOW */
+ .gpio56 = GPIO_MODE_NATIVE, /* Native */
+ .gpio57 = GPIO_MODE_GPIO, /* Unknown Input */
+ .gpio58 = GPIO_MODE_NATIVE, /* Native */
+ .gpio59 = GPIO_MODE_NATIVE, /* USB OC #0 */
+ .gpio60 = GPIO_MODE_GPIO, /* Unknown Output HIGH */
+ .gpio61 = GPIO_MODE_NATIVE, /* Native */
+ .gpio62 = GPIO_MODE_NATIVE, /* Native */
+ .gpio63 = GPIO_MODE_NATIVE, /* Native */
+};
+
+const struct pch_gpio_set2 pch_gpio_set2_direction = {
+ .gpio32 = GPIO_DIR_INPUT, /* Native */
+ .gpio33 = GPIO_DIR_INPUT, /* Native */
+ .gpio34 = GPIO_DIR_OUTPUT, /* Unknown Output LOW */
+ .gpio35 = GPIO_DIR_INPUT, /* Native */
+ .gpio36 = GPIO_DIR_INPUT, /* Native */
+ .gpio37 = GPIO_DIR_OUTPUT, /* Unknown Output LOW */
+ .gpio38 = GPIO_DIR_INPUT, /* Unknown Input */
+ .gpio39 = GPIO_DIR_INPUT, /* Unknown Input */
+ .gpio40 = GPIO_DIR_INPUT, /* Native */
+ .gpio41 = GPIO_DIR_INPUT, /* Native */
+ .gpio42 = GPIO_DIR_INPUT, /* Native */
+ .gpio43 = GPIO_DIR_INPUT, /* Native */
+ .gpio44 = GPIO_DIR_INPUT, /* Native */
+ .gpio45 = GPIO_DIR_INPUT, /* Native */
+ .gpio46 = GPIO_DIR_OUTPUT, /* Unknown Output HIGH */
+ .gpio47 = GPIO_DIR_INPUT, /* Native */
+ .gpio48 = GPIO_DIR_INPUT, /* Unknown Input */
+ .gpio49 = GPIO_DIR_INPUT, /* Unknown Input */
+ .gpio50 = GPIO_DIR_OUTPUT, /* Unknown Output HIGH */
+ .gpio51 = GPIO_DIR_OUTPUT, /* Unknown Output HIGH */
+ .gpio52 = GPIO_DIR_OUTPUT, /* Unknown Output HIGH */
+ .gpio53 = GPIO_DIR_OUTPUT, /* Unknown Output HIGH */
+ .gpio54 = GPIO_DIR_OUTPUT, /* Unknown Output HIGH */
+ .gpio55 = GPIO_DIR_OUTPUT, /* Unknown Output LOW */
+ .gpio56 = GPIO_DIR_INPUT, /* Native */
+ .gpio57 = GPIO_DIR_INPUT, /* Unknown Input */
+ .gpio58 = GPIO_DIR_INPUT, /* Native */
+ .gpio59 = GPIO_DIR_INPUT, /* Native */
+ .gpio60 = GPIO_DIR_OUTPUT, /* Unknown Output HIGH */
+ .gpio61 = GPIO_DIR_INPUT, /* Native */
+ .gpio62 = GPIO_DIR_INPUT, /* Native */
+ .gpio63 = GPIO_DIR_INPUT, /* Native */
+};
+
+const struct pch_gpio_set2 pch_gpio_set2_level = {
+ .gpio32 = GPIO_LEVEL_LOW, /* Native */
+ .gpio33 = GPIO_LEVEL_LOW, /* Native */
+ .gpio34 = GPIO_LEVEL_LOW, /* Unknown Output LOW */
+ .gpio35 = GPIO_LEVEL_LOW, /* Native */
+ .gpio36 = GPIO_LEVEL_LOW, /* Native */
+ .gpio37 = GPIO_LEVEL_LOW, /* Unknown Output LOW */
+ .gpio38 = GPIO_LEVEL_LOW, /* Unknown Input */
+ .gpio39 = GPIO_LEVEL_LOW, /* Unknown Input */
+ .gpio40 = GPIO_LEVEL_LOW, /* Native */
+ .gpio41 = GPIO_LEVEL_LOW, /* Native */
+ .gpio42 = GPIO_LEVEL_LOW, /* Native */
+ .gpio43 = GPIO_LEVEL_LOW, /* Native */
+ .gpio44 = GPIO_LEVEL_LOW, /* Native */
+ .gpio45 = GPIO_LEVEL_LOW, /* Native */
+ .gpio46 = GPIO_LEVEL_HIGH, /* Unknown Output HIGH */
+ .gpio47 = GPIO_LEVEL_LOW, /* Native */
+ .gpio48 = GPIO_LEVEL_LOW, /* Unknown Input */
+ .gpio49 = GPIO_LEVEL_LOW, /* Unknown Input */
+ .gpio50 = GPIO_LEVEL_HIGH, /* Unknown Output HIGH */
+ .gpio51 = GPIO_LEVEL_HIGH, /* Unknown Output HIGH */
+ .gpio52 = GPIO_LEVEL_HIGH, /* Unknown Output HIGH */
+ .gpio53 = GPIO_LEVEL_HIGH, /* Unknown Output HIGH */
+ .gpio54 = GPIO_LEVEL_HIGH, /* Unknown Output HIGH */
+ .gpio55 = GPIO_LEVEL_LOW, /* Unknown Output LOW */
+ .gpio56 = GPIO_LEVEL_LOW, /* Native */
+ .gpio57 = GPIO_LEVEL_LOW, /* Unknown Input */
+ .gpio58 = GPIO_LEVEL_LOW, /* Native */
+ .gpio59 = GPIO_LEVEL_LOW, /* Native */
+ .gpio60 = GPIO_LEVEL_HIGH, /* Unknown Output HIGH */
+ .gpio61 = GPIO_LEVEL_LOW, /* Native */
+ .gpio62 = GPIO_LEVEL_LOW, /* Native */
+ .gpio63 = GPIO_LEVEL_LOW, /* Native */
+};
+
+const struct pch_gpio_set2 pch_gpio_set2_reset = {
+ .gpio32 = GPIO_RESET_PWROK,
+ .gpio33 = GPIO_RESET_PWROK,
+ .gpio34 = GPIO_RESET_PWROK,
+ .gpio35 = GPIO_RESET_PWROK,
+ .gpio36 = GPIO_RESET_PWROK,
+ .gpio37 = GPIO_RESET_PWROK,
+ .gpio38 = GPIO_RESET_PWROK,
+ .gpio39 = GPIO_RESET_PWROK,
+ .gpio40 = GPIO_RESET_PWROK,
+ .gpio41 = GPIO_RESET_PWROK,
+ .gpio42 = GPIO_RESET_PWROK,
+ .gpio43 = GPIO_RESET_PWROK,
+ .gpio44 = GPIO_RESET_PWROK,
+ .gpio45 = GPIO_RESET_PWROK,
+ .gpio46 = GPIO_RESET_PWROK,
+ .gpio47 = GPIO_RESET_PWROK,
+ .gpio48 = GPIO_RESET_PWROK,
+ .gpio49 = GPIO_RESET_PWROK,
+ .gpio50 = GPIO_RESET_PWROK,
+ .gpio51 = GPIO_RESET_PWROK,
+ .gpio52 = GPIO_RESET_PWROK,
+ .gpio53 = GPIO_RESET_PWROK,
+ .gpio54 = GPIO_RESET_PWROK,
+ .gpio55 = GPIO_RESET_PWROK,
+ .gpio56 = GPIO_RESET_PWROK,
+ .gpio57 = GPIO_RESET_PWROK,
+ .gpio58 = GPIO_RESET_PWROK,
+ .gpio59 = GPIO_RESET_PWROK,
+ .gpio60 = GPIO_RESET_PWROK,
+ .gpio61 = GPIO_RESET_PWROK,
+ .gpio62 = GPIO_RESET_PWROK,
+ .gpio63 = GPIO_RESET_PWROK,
+};
+
+const struct pch_gpio_set3 pch_gpio_set3_mode = {
+ .gpio64 = GPIO_MODE_NATIVE, /* Native */
+ .gpio65 = GPIO_MODE_NATIVE, /* Native */
+ .gpio66 = GPIO_MODE_GPIO, /* Unknown Output LOW */
+ .gpio67 = GPIO_MODE_GPIO, /* Unknown Input */
+ .gpio68 = GPIO_MODE_GPIO, /* Unknown Output HIGH */
+ .gpio69 = GPIO_MODE_GPIO, /* Unknown Input */
+ .gpio70 = GPIO_MODE_NATIVE, /* Native */
+ .gpio71 = GPIO_MODE_NATIVE, /* Native */
+ .gpio72 = GPIO_MODE_NATIVE, /* Native */
+ .gpio73 = GPIO_MODE_NATIVE, /* Native */
+ .gpio74 = GPIO_MODE_NATIVE, /* Native */
+ .gpio75 = GPIO_MODE_NATIVE, /* Native */
+};
+
+const struct pch_gpio_set3 pch_gpio_set3_direction = {
+ .gpio64 = GPIO_DIR_INPUT, /* Native */
+ .gpio65 = GPIO_DIR_INPUT, /* Native */
+ .gpio66 = GPIO_DIR_OUTPUT, /* Unknown Output LOW */
+ .gpio67 = GPIO_DIR_INPUT, /* Unknown Input */
+ .gpio68 = GPIO_DIR_OUTPUT, /* Unknown Output HIGH */
+ .gpio69 = GPIO_DIR_INPUT, /* Unknown Input */
+ .gpio70 = GPIO_DIR_INPUT, /* Native */
+ .gpio71 = GPIO_DIR_INPUT, /* Native */
+ .gpio72 = GPIO_DIR_INPUT, /* Native */
+ .gpio73 = GPIO_DIR_INPUT, /* Native */
+ .gpio74 = GPIO_DIR_INPUT, /* Native */
+ .gpio75 = GPIO_DIR_INPUT, /* Native */
+};
+
+const struct pch_gpio_set3 pch_gpio_set3_level = {
+ .gpio64 = GPIO_LEVEL_LOW, /* Native */
+ .gpio65 = GPIO_LEVEL_LOW, /* Native */
+ .gpio66 = GPIO_LEVEL_LOW, /* Unknown Output LOW */
+ .gpio67 = GPIO_LEVEL_LOW, /* Unknown Input */
+ .gpio68 = GPIO_LEVEL_HIGH, /* Unknown Output HIGH */
+ .gpio69 = GPIO_LEVEL_LOW, /* Unknown Input */
+ .gpio70 = GPIO_LEVEL_LOW, /* Native */
+ .gpio71 = GPIO_LEVEL_LOW, /* Native */
+ .gpio72 = GPIO_LEVEL_LOW, /* Native */
+ .gpio73 = GPIO_LEVEL_LOW, /* Native */
+ .gpio74 = GPIO_LEVEL_LOW, /* Native */
+ .gpio75 = GPIO_LEVEL_LOW, /* Native */
+};
+
+const struct pch_gpio_set3 pch_gpio_set3_reset = {
+ .gpio64 = GPIO_RESET_PWROK,
+ .gpio65 = GPIO_RESET_PWROK,
+ .gpio66 = GPIO_RESET_PWROK,
+ .gpio67 = GPIO_RESET_PWROK,
+ .gpio68 = GPIO_RESET_PWROK,
+ .gpio69 = GPIO_RESET_PWROK,
+ .gpio70 = GPIO_RESET_PWROK,
+ .gpio71 = GPIO_RESET_PWROK,
+ .gpio72 = GPIO_RESET_PWROK,
+ .gpio73 = GPIO_RESET_PWROK,
+ .gpio74 = GPIO_RESET_PWROK,
+ .gpio75 = GPIO_RESET_PWROK,
+};
+
+const struct pch_gpio_map mainboard_gpio_map = {
+ .set1 = {
+ .mode = &pch_gpio_set1_mode,
+ .direction = &pch_gpio_set1_direction,
+ .level = &pch_gpio_set1_level,
+ .reset = &pch_gpio_set1_reset,
+ .invert = &pch_gpio_set1_invert,
+ .blink = &pch_gpio_set1_blink,
+ },
+ .set2 = {
+ .mode = &pch_gpio_set2_mode,
+ .direction = &pch_gpio_set2_direction,
+ .level = &pch_gpio_set2_level,
+ .reset = &pch_gpio_set2_reset,
+ },
+ .set3 = {
+ .mode = &pch_gpio_set3_mode,
+ .direction = &pch_gpio_set3_direction,
+ .level = &pch_gpio_set3_level,
+ .reset = &pch_gpio_set3_reset,
+ },
+};
diff --git a/src/mainboard/roda/rv11/hda_verb.c b/src/mainboard/roda/rv11/hda_verb.c
new file mode 100644
index 0000000..fbaec16
--- /dev/null
+++ b/src/mainboard/roda/rv11/hda_verb.c
@@ -0,0 +1,31 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2016 secunet Security Networks AG
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <device/azalia_device.h>
+
+#include <variant/hda_verb.h>
+
+const u32 pc_beep_verbs[] = {
+ 0x00170500, /* power up codec */
+ 0x01470500, /* power up speakers */
+ 0x01470100, /* select lout1 (input 0x0) for speakers */
+ 0x01470740, /* enable speakers output */
+ 0x00b37517, /* unmute beep (mixer's input 0x5), set amp 0dB */
+ 0x00c37100, /* unmute mixer in lout1 (lout1 input 0x1) */
+ 0x00c3b015, /* set lout1 output volume -15dB */
+ 0x0143b000, /* unmute speakers */
+};
+
+AZALIA_ARRAY_SIZES;
diff --git a/src/mainboard/roda/rv11/romstage.c b/src/mainboard/roda/rv11/romstage.c
new file mode 100644
index 0000000..7219b0b
--- /dev/null
+++ b/src/mainboard/roda/rv11/romstage.c
@@ -0,0 +1,38 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 The ChromiumOS Authors. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <northbridge/intel/sandybridge/sandybridge.h>
+#include <southbridge/intel/bd82x6x/pch.h>
+
+void rcba_config(void)
+{
+ u32 reg32;
+
+ /* Disable unused devices (board specific) */
+ reg32 = RCBA32(FD);
+ reg32 |= PCH_DISABLE_ALWAYS;
+ /* Disable PCI bridge so MRC does not probe this bus */
+ reg32 |= PCH_DISABLE_P2P;
+ RCBA32(FD) = reg32;
+}
+
+void mainboard_early_init(int s3resume)
+{
+}
+
+int mainboard_should_reset_usb(int s3resume)
+{
+ return !s3resume;
+}
diff --git a/src/mainboard/roda/rv11/variants/rv11/devicetree.cb b/src/mainboard/roda/rv11/variants/rv11/devicetree.cb
new file mode 100644
index 0000000..4455fdb
--- /dev/null
+++ b/src/mainboard/roda/rv11/variants/rv11/devicetree.cb
@@ -0,0 +1,116 @@
+##
+## This file is part of the coreboot project.
+##
+## Copyright (C) 2015-2016 secunet Security Networks AG
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; version 2 of the License.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+## GNU General Public License for more details.
+##
+
+chip northbridge/intel/sandybridge
+ # IGD Displays
+ register "gfx.ndid" = "3"
+ register "gfx.did" = "{ 0x80000400, 0x80000300, 0x80000100, }"
+
+ # Enable Panel as eDP and configure power delays
+ register "gpu_panel_port_select" = "1" # eDP_A
+ register "gpu_panel_power_cycle_delay" = "6" # 500ms
+ register "gpu_panel_power_up_delay" = "2000" # 200ms
+ register "gpu_panel_power_down_delay" = "500" # 50ms
+ register "gpu_panel_power_backlight_on_delay" = "1" # 100us as recommended by PRM
+ register "gpu_panel_power_backlight_off_delay" = "2000" # 200ms
+
+ # Set backlight PWM values for eDP
+ register "gpu_cpu_backlight" = "0x0000001a"
+ register "gpu_pch_backlight" = "0x002e0000"
+
+ device cpu_cluster 0 on
+ chip cpu/intel/socket_rPGA989
+ device lapic 0 on end
+ end
+ chip cpu/intel/model_206ax
+ # Magic APIC ID to locate this chip
+ device lapic 0xACAC off end
+
+ register "c1_acpower" = "1" # ACPI(C1) = MWAIT(C1)
+ register "c2_acpower" = "4" # ACPI(C2) = MWAIT(C6)
+ register "c3_acpower" = "0"
+
+ register "c1_battery" = "1" # ACPI(C1) = MWAIT(C1)
+ register "c2_battery" = "4" # ACPI(C2) = MWAIT(C6)
+ register "c3_battery" = "0"
+ end
+ end
+
+ device domain 0 on
+ device pci 00.0 on end # host bridge
+ device pci 02.0 on end # vga controller
+
+ chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH
+ # Enable both SATA ports 0, 1
+ register "sata_port_map" = "0x03"
+ # Set max SATA speed to 6.0 Gb/s (should be the default, anyway)
+ register "sata_interface_speed_support" = "0x3"
+
+ # Route GPI7 (EC SCI) as SCI
+ register "gpi7_routing" = "2"
+
+ # Enable GPE17 (GPI7) and TCO SCI
+ register "gpe0_en" = "0x00800040"
+
+ # Disable root port coalescing
+ register "pcie_port_coalesce" = "0"
+ register "pcie_hotplug_map" = "{ 0, 0, 0, 1, 0, 0, 0, 0 }"
+
+ register "p_cnt_throttling_supported" = "1"
+
+ register "xhci_overcurrent_mapping" = "0x00080401"
+ register "xhci_switchable_ports" = "0x0f"
+ register "superspeed_capable_ports" = "0x0f"
+
+ register "spi_uvscc" = "0x2005"
+ register "spi_lvscc" = "0x2005"
+
+ device pci 14.0 on end # USB 3.0 Controller
+ device pci 16.0 on end # Management Engine Interface 1
+ device pci 16.1 off end # Management Engine Interface 2
+ device pci 16.2 off end # Management Engine IDE-R
+ device pci 16.3 off end # Management Engine KT
+ device pci 19.0 on end # Intel Gigabit Ethernet
+ device pci 1a.0 on end # USB2 EHCI #2
+ device pci 1b.0 on # High Definition Audio
+ subsystemid 0x1a86 0x4352
+ end
+
+ # Disabling 1c.0 might break IRQ settings as it enables port coalescing
+ device pci 1c.0 on end # PCIe Port #1
+ device pci 1c.1 on end # PCIe Port #2
+ device pci 1c.2 off end # PCIe Port #3
+ device pci 1c.3 on end # PCIe Port #4
+ device pci 1c.4 on end # PCIe Port #5
+ device pci 1c.5 off end # PCIe Port #6
+ device pci 1c.6 on end # PCIe Port #7
+ device pci 1c.7 on end # PCIe Port #8
+
+ device pci 1d.0 on end # USB2 EHCI #1
+ device pci 1e.0 off end # PCI bridge
+ device pci 1f.0 on # LPC bridge
+ chip ec/roda/it8518
+ # 60h/64h KBC
+ device pnp ff.0 on # dummy address
+ end
+ end
+ end # LPC bridge
+ device pci 1f.2 on end # SATA Controller 1
+ device pci 1f.3 on end # SMBus
+ device pci 1f.5 off end # SATA Controller 2
+ device pci 1f.6 off end # Thermal
+ end
+ end
+end
diff --git a/src/mainboard/roda/rv11/variants/rv11/gma-mainboard.ads b/src/mainboard/roda/rv11/variants/rv11/gma-mainboard.ads
new file mode 100644
index 0000000..e16846d
--- /dev/null
+++ b/src/mainboard/roda/rv11/variants/rv11/gma-mainboard.ads
@@ -0,0 +1,9 @@
+with HW.GFX.GMA;
+
+use HW.GFX.GMA;
+
+private package GMA.Mainboard is
+
+ ports : constant Port_List := (Internal, Digital3, others => Disabled);
+
+end GMA.Mainboard;
diff --git a/src/mainboard/roda/rv11/variants/rv11/include/acpi/brightness_levels.asl b/src/mainboard/roda/rv11/variants/rv11/include/acpi/brightness_levels.asl
new file mode 100644
index 0000000..b150475
--- /dev/null
+++ b/src/mainboard/roda/rv11/variants/rv11/include/acpi/brightness_levels.asl
@@ -0,0 +1,19 @@
+Scope (GFX0)
+{
+ Name (BRIG, Package (13)
+ {
+ 74, /* default AC */
+ 74, /* default Battery */
+ 9, /* 4 / 46 */
+ 11, /* 5 / 46 */
+ 15, /* 6 / 46 */
+ 20, /* 9 / 46 */
+ 24, /* 11 / 46 */
+ 28, /* 12 / 46 */
+ 39, /* 17 / 46 */
+ 50, /* 23 / 46 */
+ 60, /* 27 / 46 */
+ 74, /* 34 / 46 */
+ 100, /* 46 / 46 */
+ })
+}
diff --git a/src/mainboard/roda/rv11/variants/rv11/include/acpi/superio.asl b/src/mainboard/roda/rv11/variants/rv11/include/acpi/superio.asl
new file mode 100644
index 0000000..d1b2193
--- /dev/null
+++ b/src/mainboard/roda/rv11/variants/rv11/include/acpi/superio.asl
@@ -0,0 +1 @@
+/* no super i/o */
diff --git a/src/mainboard/roda/rv11/variants/rv11/include/variant/hda_verb.h b/src/mainboard/roda/rv11/variants/rv11/include/variant/hda_verb.h
new file mode 100644
index 0000000..e80edc5
--- /dev/null
+++ b/src/mainboard/roda/rv11/variants/rv11/include/variant/hda_verb.h
@@ -0,0 +1,67 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2015 secunet Security Networks AG
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+const u32 cim_verb_data[] = {
+ /* coreboot specific header */
+ 0x10ec0262, /* Codec Vendor / Device ID: Realtek ALC262 */
+ 0x1a864352, /* Subsystem ID */
+ 0x0000000e, /* Number of jacks */
+
+ /* NID 0x01, HDA Codec Subsystem ID Verb Table: 0x10ec0262 */
+ AZALIA_SUBVENDOR(0, 0x1a864352),
+
+ AZALIA_PIN_CFG(0, 0x11, 0x40000000),
+
+ AZALIA_PIN_CFG(0, 0x12, 0x90a60140),
+
+ AZALIA_PIN_CFG(0, 0x14, 0x90170110),
+
+ AZALIA_PIN_CFG(0, 0x15, 0x01214020),
+
+ AZALIA_PIN_CFG(0, 0x16, 0x411111f0),
+
+ AZALIA_PIN_CFG(0, 0x18, 0x01a19030),
+
+ AZALIA_PIN_CFG(0, 0x19, 0x411111f0),
+
+ AZALIA_PIN_CFG(0, 0x1a, 0x411111f0),
+
+ AZALIA_PIN_CFG(0, 0x1b, 0x411111f0),
+
+ AZALIA_PIN_CFG(0, 0x1c, 0x411111f0),
+
+ AZALIA_PIN_CFG(0, 0x1d, 0x4036a235),
+
+ AZALIA_PIN_CFG(0, 0x1e, 0x411111f0),
+
+ AZALIA_PIN_CFG(0, 0x1f, 0x411111f0),
+
+ /* coreboot specific header */
+ 0x80862806, /* Codec Vendor / Device ID: Intel PantherPoint HDMI */
+ 0x80860101, /* Subsystem ID */
+ 0x00000004, /* Number of jacks */
+
+ /* NID 0x01, HDA Codec Subsystem ID Verb Table: 0x80860101 */
+ AZALIA_SUBVENDOR(3, 0x80860101),
+
+ /* Pin Complex (NID 0x05) Digital Out at Int HDMI */
+ AZALIA_PIN_CFG(3, 0x05, 0x18560010),
+
+ /* Pin Complex (NID 0x06) Digital Out at Int HDMI */
+ AZALIA_PIN_CFG(3, 0x06, 0x18560020),
+
+ /* Pin Complex (NID 0x07) Digital Out at Int HDMI */
+ AZALIA_PIN_CFG(3, 0x07, 0x18560030),
+};
diff --git a/src/mainboard/roda/rv11/variants/rv11/include/variant/thermal.h b/src/mainboard/roda/rv11/variants/rv11/include/variant/thermal.h
new file mode 100644
index 0000000..31cf28e
--- /dev/null
+++ b/src/mainboard/roda/rv11/variants/rv11/include/variant/thermal.h
@@ -0,0 +1,17 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2016 secunet Security Networks AG
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#define CRITICAL_TEMPERATURE 106
+#define PASSIVE_TEMPERATURE 100
diff --git a/src/mainboard/roda/rv11/variants/rv11/romstage.c b/src/mainboard/roda/rv11/variants/rv11/romstage.c
new file mode 100644
index 0000000..c7de994
--- /dev/null
+++ b/src/mainboard/roda/rv11/variants/rv11/romstage.c
@@ -0,0 +1,115 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2015 secunet Security Networks AG
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <stdint.h>
+#include <device/pci.h>
+#include <northbridge/intel/sandybridge/raminit.h>
+#include <northbridge/intel/sandybridge/raminit_native.h>
+#include <northbridge/intel/sandybridge/sandybridge.h>
+#include <southbridge/intel/bd82x6x/pch.h>
+
+void pch_enable_lpc(void)
+{
+ /* Enable KBC on 0x60/0x64 (KBC),
+ EC on 0x62/0x66 (MC) */
+ pci_write_config16(PCH_LPC_DEV, LPC_EN,
+ KBC_LPC_EN | MC_LPC_EN);
+}
+
+void mainboard_config_superio(void)
+{
+}
+
+void mainboard_fill_pei_data(struct pei_data *const pei_data)
+{
+ const struct pei_data pei_data_template = {
+ .pei_version = PEI_VERSION,
+ .mchbar = (uintptr_t)DEFAULT_MCHBAR,
+ .dmibar = (uintptr_t)DEFAULT_DMIBAR,
+ .epbar = DEFAULT_EPBAR,
+ .pciexbar = CONFIG_MMCONF_BASE_ADDRESS,
+ .smbusbar = SMBUS_IO_BASE,
+ .wdbbar = 0x4000000,
+ .wdbsize = 0x1000,
+ .hpet_address = CONFIG_HPET_ADDRESS,
+ .rcba = (uintptr_t)DEFAULT_RCBABASE,
+ .pmbase = DEFAULT_PMBASE,
+ .gpiobase = DEFAULT_GPIOBASE,
+ .thermalbase = 0xfed08000,
+ .system_type = 0, // 0 Mobile, 1 Desktop/Server
+ .tseg_size = CONFIG_SMM_TSEG_SIZE,
+ .spd_addresses = { 0xA0, 0x00, 0xA4, 0x00 },
+ .ts_addresses = { 0x00, 0x00, 0x00, 0x00 },
+ .ec_present = 1,
+ .gbe_enable = 1,
+ .ddr3lv_support = 0,
+ // 0 = leave channel enabled
+ // 1 = disable dimm 0 on channel
+ // 2 = disable dimm 1 on channel
+ // 3 = disable dimm 0+1 on channel
+ .dimm_channel0_disabled = 2,
+ .dimm_channel1_disabled = 2,
+ .max_ddr3_freq = 1600,
+ .usb_port_config = {
+ /* Enabled / OC PIN / Length */
+ { 1, 0, 0x0040 }, /* P00: 1st USB3 (OC #0) */
+ { 1, 4, 0x0040 }, /* P01: 2nd USB3 (OC #4) */
+ { 1, 1, 0x0080 }, /* P02: 1st Multibay USB3 (OC #1) */
+ { 1, 2, 0x0080 }, /* P03: 2nd Multibay USB3 (OC #2) */
+ { 1, 8, 0x0040 }, /* P04: MiniPCIe 1 USB2 (no OC) */
+ { 1, 8, 0x0040 }, /* P05: MiniPCIe 2 USB2 (no OC) */
+ { 1, 8, 0x0040 }, /* P06: MiniPCIe 3 USB2 (no OC) */
+ { 1, 8, 0x0040 }, /* P07: GPS USB2 (no OC) */
+ { 1, 8, 0x0040 }, /* P08: MiniPCIe 4 USB2 (no OC) */
+ { 1, 3, 0x0040 }, /* P09: Express Card USB2 (OC #3) */
+ { 1, 8, 0x0040 }, /* P10: SD card reader USB2 (no OC) */
+ { 1, 8, 0x0040 }, /* P11: Sensors Hub? USB2 (no OC) */
+ { 1, 8, 0x0040 }, /* P12: Touch Screen USB2 (no OC) */
+ { 1, 5, 0x0040 }, /* P13: reserved? USB2 (OC #5) */
+ },
+ .usb3 = {
+ .mode = 3, /* Smart Auto? */
+ .hs_port_switch_mask = 0xf, /* All four ports. */
+ .preboot_support = 1, /* preOS driver? */
+ .xhci_streams = 1, /* Enable. */
+ },
+ .pcie_init = 1,
+ };
+ *pei_data = pei_data_template;
+}
+
+const struct southbridge_usb_port mainboard_usb_ports[] = {
+ /* Enabled / Power / OC PIN */
+ { 1, 0, 0 }, /* P00: 1st USB3 (OC #0) */
+ { 1, 0, 4 }, /* P01: 2nd USB3 (OC #4) */
+ { 1, 1, 1 }, /* P02: 1st Multibay USB3 (OC #1) */
+ { 1, 1, 2 }, /* P03: 2nd Multibay USB3 (OC #2) */
+ { 1, 0, 8 }, /* P04: MiniPCIe 1 USB2 (no OC) */
+ { 1, 0, 8 }, /* P05: MiniPCIe 2 USB2 (no OC) */
+ { 1, 0, 8 }, /* P06: MiniPCIe 3 USB2 (no OC) */
+ { 1, 0, 8 }, /* P07: GPS USB2 (no OC) */
+ { 1, 0, 8 }, /* P08: MiniPCIe 4 USB2 (no OC) */
+ { 1, 0, 3 }, /* P09: Express Card USB2 (OC #3) */
+ { 1, 0, 8 }, /* P10: SD card reader USB2 (no OC) */
+ { 1, 0, 8 }, /* P11: Sensors Hub? USB2 (no OC) */
+ { 1, 0, 8 }, /* P12: Touch Screen USB2 (no OC) */
+ { 1, 0, 5 }, /* P13: reserved? USB2 (OC #5) */
+};
+
+void mainboard_get_spd(spd_raw_data *spd, bool id_only)
+{
+ read_spd(&spd[0], 0x50, id_only);
+ read_spd(&spd[2], 0x52, id_only);
+}
diff --git a/src/mainboard/roda/rv11/variants/rw11/devicetree.cb b/src/mainboard/roda/rv11/variants/rw11/devicetree.cb
new file mode 100644
index 0000000..845bca8
--- /dev/null
+++ b/src/mainboard/roda/rv11/variants/rw11/devicetree.cb
@@ -0,0 +1,178 @@
+##
+## This file is part of the coreboot project.
+##
+## Copyright (C) 2016 secunet Security Networks AG
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; version 2 of the License.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+## GNU General Public License for more details.
+##
+
+chip northbridge/intel/sandybridge
+ # IGD Displays
+ register "gfx.ndid" = "4"
+ register "gfx.did" = "{ 0x80000400, 0x80000300, 0x80000301, 0x80000100, }"
+
+ # Enable Panel as eDP and configure power delays
+ register "gpu_panel_port_select" = "1" # eDP_A
+ register "gpu_panel_power_cycle_delay" = "6" # 500ms
+ register "gpu_panel_power_up_delay" = "2000" # 200ms
+ register "gpu_panel_power_down_delay" = "500" # 50ms
+ register "gpu_panel_power_backlight_on_delay" = "1" # 100us as recommended by PRM
+ register "gpu_panel_power_backlight_off_delay" = "2000" # 200ms
+
+ # Set backlight PWM values for eDP
+ register "gpu_cpu_backlight" = "0x00000ac8"
+ register "gpu_pch_backlight" = "0x13120000"
+
+ device cpu_cluster 0 on
+ chip cpu/intel/socket_rPGA989
+ device lapic 0 on end
+ end
+ chip cpu/intel/model_206ax
+ # Magic APIC ID to locate this chip
+ device lapic 0xACAC off end
+
+ register "c1_acpower" = "1" # ACPI(C1) = MWAIT(C1)
+ register "c2_acpower" = "4" # ACPI(C2) = MWAIT(C6)
+ register "c3_acpower" = "0"
+
+ register "c1_battery" = "1" # ACPI(C1) = MWAIT(C1)
+ register "c2_battery" = "4" # ACPI(C2) = MWAIT(C6)
+ register "c3_battery" = "0"
+ end
+ end
+
+ device domain 0 on
+ device pci 00.0 on end # host bridge
+ device pci 02.0 on end # vga controller
+
+ chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH
+ # LPC i/o generic decodes
+ register "gen1_dec" = "0x003c0a01" # ITE environment controller
+ register "gen2_dec" = "0x000403e9" # additional com port
+ register "gen3_dec" = "0x000402e9" # additional com port
+
+ # Enable both SATA ports 0, 1
+ register "sata_port_map" = "0x03"
+ # Set max SATA speed to 6.0 Gb/s (should be the default, anyway)
+ register "sata_interface_speed_support" = "0x3"
+
+ # Route GPI7 (EC SCI) as SCI
+ register "gpi7_routing" = "2"
+
+ # Enable GPE17 (GPI7) and TCO SCI
+ register "gpe0_en" = "0x00800040"
+
+ # Disable root port coalescing
+ register "pcie_port_coalesce" = "0"
+ register "pcie_hotplug_map" = "{ 0, 0, 0, 0, 0, 0, 1, 1 }"
+
+ register "p_cnt_throttling_supported" = "1"
+
+ register "xhci_overcurrent_mapping" = "0x00000c03"
+ register "xhci_switchable_ports" = "0x0f"
+ register "superspeed_capable_ports" = "0x0f"
+
+ register "spi_uvscc" = "0x2005"
+ register "spi_lvscc" = "0x2005"
+
+ device pci 14.0 on end # USB 3.0 Controller
+ device pci 16.0 on end # Management Engine Interface 1
+ device pci 16.1 off end # Management Engine Interface 2
+ device pci 16.2 off end # Management Engine IDE-R
+ device pci 16.3 off end # Management Engine KT
+ device pci 19.0 on end # Intel Gigabit Ethernet
+ device pci 1a.0 on end # USB2 EHCI #2
+ device pci 1b.0 on # High Definition Audio
+ subsystemid 0x1a86 0x4352
+ end
+
+ # Disabling 1c.0 might break IRQ settings as it enables port coalescing
+ device pci 1c.0 on end # PCIe Port #1
+ device pci 1c.1 on end # PCIe Port #2
+ device pci 1c.2 on end # PCIe Port #3
+ device pci 1c.3 on end # PCIe Port #4
+ device pci 1c.4 on end # PCIe Port #5
+ device pci 1c.5 on end # PCIe Port #6
+ device pci 1c.6 on end # PCIe Port #7
+ device pci 1c.7 on end # PCIe Port #8
+
+ device pci 1d.0 on end # USB2 EHCI #1
+ device pci 1e.0 off end # PCI bridge
+ device pci 1f.0 on # LPC bridge
+ chip ec/roda/it8518
+ register "cpuhot_limit" = "100"
+ # 60h/64h KBC
+ device pnp ff.0 on # dummy address
+ end
+ end
+ chip superio/ite/it8783ef
+ register "TMPIN1" = "THERMAL_RESISTOR"
+ register "TMPIN2" = "THERMAL_RESISTOR"
+ register "ec.vin_mask" = "VIN_ALL"
+ register "FAN1.mode" = "FAN_SMART_AUTOMATIC"
+ register "FAN1.smart.tmpin" = " 1"
+ register "FAN1.smart.tmp_off" = "60"
+ register "FAN1.smart.tmp_start" = "64"
+ register "FAN1.smart.tmp_delta" = " 2"
+ register "FAN1.smart.pwm_start" = "30"
+ register "FAN1.smart.slope" = "64"
+ register "FAN2.mode" = "FAN_SMART_AUTOMATIC"
+ register "FAN2.smart.tmpin" = " 1"
+ register "FAN2.smart.tmp_off" = "60"
+ register "FAN2.smart.tmp_start" = "64"
+ register "FAN2.smart.tmp_delta" = " 2"
+ register "FAN2.smart.pwm_start" = "30"
+ register "FAN2.smart.slope" = "64"
+ register "FAN3.mode" = "FAN_MODE_OFF"
+ device pnp 2e.0 off end # Floppy
+ device pnp 2e.1 on # COM 1
+ io 0x60 = 0x3f8
+ irq 0x70 = 4
+ end
+ device pnp 2e.2 on # COM 2
+ io 0x60 = 0x2f8
+ irq 0x70 = 3
+ end
+ device pnp 2e.3 on # Printer Port
+ io 0x60 = 0x378
+ io 0x62 = 0x000
+ irq 0x70 = 7
+ drq 0x74 = 4
+ irq 0xf0 = 0x00
+ end
+ device pnp 2e.4 on # Environment Controller
+ io 0x60 = 0xa30
+ io 0x62 = 0xa20
+ irq 0x70 = 0
+ irq 0xf0 = 0x80
+ end
+ device pnp 2e.5 off end # Keyboard
+ device pnp 2e.6 off end # Mouse
+ device pnp 2e.7 off end # GPIO
+ device pnp 2e.8 on # COM 3
+ io 0x60 = 0x3e8
+ irq 0x70 = 4
+ end
+ device pnp 2e.9 on # COM 4
+ io 0x60 = 0x2e8
+ irq 0x70 = 3
+ end
+ device pnp 2e.a off end # COM 5
+ device pnp 2e.b off end # COM 6
+ device pnp 2e.c off end # CIR
+ end
+ end # LPC bridge
+ device pci 1f.2 on end # SATA Controller 1
+ device pci 1f.3 on end # SMBus
+ device pci 1f.5 off end # SATA Controller 2
+ device pci 1f.6 off end # Thermal
+ end
+ end
+end
diff --git a/src/mainboard/roda/rv11/variants/rw11/gma-mainboard.ads b/src/mainboard/roda/rv11/variants/rw11/gma-mainboard.ads
new file mode 100644
index 0000000..52b81fa
--- /dev/null
+++ b/src/mainboard/roda/rv11/variants/rw11/gma-mainboard.ads
@@ -0,0 +1,20 @@
+with HW.GFX.GMA;
+
+use HW.GFX.GMA;
+
+private package GMA.Mainboard is
+
+ -- For a three-pipe setup, bandwidth is shared between the 2nd and
+ -- the 3rd pipe (if it's not eDP). Thus, probe ports that likely
+ -- have a high-resolution display attached first, `Internal` last.
+
+ ports : constant Port_List :=
+ (DP2,
+ DP3,
+ Digital2,
+ Digital3,
+ Analog,
+ Internal,
+ others => Disabled);
+
+end GMA.Mainboard;
diff --git a/src/mainboard/roda/rv11/variants/rw11/include/acpi/brightness_levels.asl b/src/mainboard/roda/rv11/variants/rw11/include/acpi/brightness_levels.asl
new file mode 100644
index 0000000..7dba1f2
--- /dev/null
+++ b/src/mainboard/roda/rv11/variants/rw11/include/acpi/brightness_levels.asl
@@ -0,0 +1,19 @@
+Scope (GFX0)
+{
+ Name (BRIG, Package (13)
+ {
+ 74, /* default AC */
+ 74, /* default Battery */
+ 9, /* 439 / 4882 */
+ 11, /* 537 / 4882 */
+ 14, /* 683 / 4882 */
+ 18, /* 878 / 4882 */
+ 22, /* 1074 / 4882 */
+ 28, /* 1366 / 4882 */
+ 36, /* 1757 / 4882 */
+ 46, /* 2245 / 4882 */
+ 58, /* 2831 / 4882 */
+ 74, /* 3612 / 4882 */
+ 100, /* 4882 / 4882 */
+ })
+}
diff --git a/src/mainboard/roda/rv11/variants/rw11/include/acpi/superio.asl b/src/mainboard/roda/rv11/variants/rw11/include/acpi/superio.asl
new file mode 100644
index 0000000..ae53167
--- /dev/null
+++ b/src/mainboard/roda/rv11/variants/rw11/include/acpi/superio.asl
@@ -0,0 +1,30 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2016 secunet Security Networks AG
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#undef SUPERIO_DEV
+#undef SUPERIO_PNP_BASE
+#undef IT8783EF_SHOW_UARTA
+#undef IT8783EF_SHOW_UARTB
+#undef IT8783EF_SHOW_UARTC
+#undef IT8783EF_SHOW_UARTD
+#undef IT8783EF_SHOW_KBC
+#undef IT8783EF_SHOW_PS2M
+#define SUPERIO_DEV SIO0
+#define SUPERIO_PNP_BASE 0x2e
+#define IT8783EF_SHOW_UARTA 1
+#define IT8783EF_SHOW_UARTB 1
+#define IT8783EF_SHOW_UARTC 1
+#define IT8783EF_SHOW_UARTD 1
+#include <superio/ite/it8783ef/acpi/superio.asl>
diff --git a/src/mainboard/roda/rv11/variants/rw11/include/variant/hda_verb.h b/src/mainboard/roda/rv11/variants/rw11/include/variant/hda_verb.h
new file mode 100644
index 0000000..edc5f64
--- /dev/null
+++ b/src/mainboard/roda/rv11/variants/rw11/include/variant/hda_verb.h
@@ -0,0 +1,67 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2016 secunet Security Networks AG
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+const u32 cim_verb_data[] = {
+ /* coreboot specific header */
+ 0x10ec0262, /* Codec Vendor / Device ID: Realtek ALC262 */
+ 0x1a864352, /* Subsystem ID */
+ 0x0000000e, /* Number of jacks */
+
+ /* NID 0x01, HDA Codec Subsystem ID Verb Table: 0x10ec0262 */
+ AZALIA_SUBVENDOR(0, 0x1a864352),
+
+ AZALIA_PIN_CFG(0, 0x11, 0x18561180),
+
+ AZALIA_PIN_CFG(0, 0x12, 0x90a60130),
+
+ AZALIA_PIN_CFG(0, 0x14, 0x90170110),
+
+ AZALIA_PIN_CFG(0, 0x15, 0x03214020),
+
+ AZALIA_PIN_CFG(0, 0x16, 0x40000000),
+
+ AZALIA_PIN_CFG(0, 0x18, 0x03a19040),
+
+ AZALIA_PIN_CFG(0, 0x19, 0x411111f0),
+
+ AZALIA_PIN_CFG(0, 0x1a, 0x03813050),
+
+ AZALIA_PIN_CFG(0, 0x1b, 0x411111f0),
+
+ AZALIA_PIN_CFG(0, 0x1c, 0x411111f0),
+
+ AZALIA_PIN_CFG(0, 0x1d, 0x40d6862d),
+
+ AZALIA_PIN_CFG(0, 0x1e, 0x411111f0),
+
+ AZALIA_PIN_CFG(0, 0x1f, 0x411111f0),
+
+ /* coreboot specific header */
+ 0x80862806, /* Codec Vendor / Device ID: Intel PantherPoint HDMI */
+ 0x80860101, /* Subsystem ID */
+ 0x00000004, /* Number of jacks */
+
+ /* NID 0x01, HDA Codec Subsystem ID Verb Table: 0x80860101 */
+ AZALIA_SUBVENDOR(3, 0x80860101),
+
+ /* Pin Complex (NID 0x05) Digital Out at Int HDMI */
+ AZALIA_PIN_CFG(3, 0x05, 0x18560010),
+
+ /* Pin Complex (NID 0x06) Digital Out at Int HDMI */
+ AZALIA_PIN_CFG(3, 0x06, 0x18560020),
+
+ /* Pin Complex (NID 0x07) Digital Out at Int HDMI */
+ AZALIA_PIN_CFG(3, 0x07, 0x18560030),
+};
diff --git a/src/mainboard/roda/rv11/variants/rw11/include/variant/thermal.h b/src/mainboard/roda/rv11/variants/rw11/include/variant/thermal.h
new file mode 100644
index 0000000..d3b72cd
--- /dev/null
+++ b/src/mainboard/roda/rv11/variants/rw11/include/variant/thermal.h
@@ -0,0 +1,17 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2016 secunet Security Networks AG
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#define CRITICAL_TEMPERATURE 100
+#define PASSIVE_TEMPERATURE 95
diff --git a/src/mainboard/roda/rv11/variants/rw11/romstage.c b/src/mainboard/roda/rv11/variants/rw11/romstage.c
new file mode 100644
index 0000000..ca705a4
--- /dev/null
+++ b/src/mainboard/roda/rv11/variants/rw11/romstage.c
@@ -0,0 +1,145 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2016 secunet Security Networks AG
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <stdint.h>
+#include <device/pci.h>
+#include <device/pnp.h>
+#include <northbridge/intel/sandybridge/raminit.h>
+#include <northbridge/intel/sandybridge/raminit_native.h>
+#include <northbridge/intel/sandybridge/sandybridge.h>
+#include <southbridge/intel/bd82x6x/pch.h>
+#include <superio/ite/it8783ef/it8783ef.h>
+#include <superio/ite/common/ite.h>
+
+void pch_enable_lpc(void)
+{
+ /* COMA on 0x3f8, COMB on 0x2f8 */
+ pci_write_config16(PCH_LPC_DEV, LPC_IO_DEC, 0x0010);
+ /* Enable KBC on 0x60/0x64 (KBC),
+ EC on 0x62/0x66 (MC),
+ SIO on 0x2e/0x2f (CNF1) */
+ pci_write_config16(PCH_LPC_DEV, LPC_EN,
+ CNF1_LPC_EN | MC_LPC_EN | KBC_LPC_EN |
+ COMB_LPC_EN | COMA_LPC_EN);
+}
+
+void mainboard_config_superio(void)
+{
+ const pnp_devfn_t dev = PNP_DEV(0x2e, IT8783EF_GPIO);
+
+ pnp_enter_conf_state(dev);
+ pnp_set_logical_device(dev);
+
+ pnp_write_config(dev, 0x23, ITE_UART_CLK_PREDIVIDE_24);
+
+ /* Switch multi function for UART4 */
+ pnp_write_config(dev, 0x2a, 0x04);
+ /* Switch multi function for UART3 */
+ pnp_write_config(dev, 0x2c, 0x13);
+
+ /* No GPIOs used: Clear any output / pull-up that's set by default */
+ pnp_write_config(dev, 0xb8, 0x00);
+ pnp_write_config(dev, 0xc0, 0x00);
+ pnp_write_config(dev, 0xc3, 0x00);
+ pnp_write_config(dev, 0xc8, 0x00);
+ pnp_write_config(dev, 0xcb, 0x00);
+ pnp_write_config(dev, 0xef, 0x00);
+
+ pnp_exit_conf_state(dev);
+}
+
+void mainboard_fill_pei_data(struct pei_data *const pei_data)
+{
+ const struct pei_data pei_data_template = {
+ .pei_version = PEI_VERSION,
+ .mchbar = (uintptr_t)DEFAULT_MCHBAR,
+ .dmibar = (uintptr_t)DEFAULT_DMIBAR,
+ .epbar = DEFAULT_EPBAR,
+ .pciexbar = CONFIG_MMCONF_BASE_ADDRESS,
+ .smbusbar = SMBUS_IO_BASE,
+ .wdbbar = 0x4000000,
+ .wdbsize = 0x1000,
+ .hpet_address = CONFIG_HPET_ADDRESS,
+ .rcba = (uintptr_t)DEFAULT_RCBABASE,
+ .pmbase = DEFAULT_PMBASE,
+ .gpiobase = DEFAULT_GPIOBASE,
+ .thermalbase = 0xfed08000,
+ .system_type = 0, // 0 Mobile, 1 Desktop/Server
+ .tseg_size = CONFIG_SMM_TSEG_SIZE,
+ .spd_addresses = { 0xA0, 0xA2, 0xA4, 0xA6 },
+ .ts_addresses = { 0x00, 0x00, 0x00, 0x00 },
+ .ec_present = 1,
+ .gbe_enable = 1,
+ .ddr3lv_support = 0,
+ // 0 = leave channel enabled
+ // 1 = disable dimm 0 on channel
+ // 2 = disable dimm 1 on channel
+ // 3 = disable dimm 0+1 on channel
+ .dimm_channel0_disabled = 0,
+ .dimm_channel1_disabled = 0,
+ .max_ddr3_freq = 1600,
+ .usb_port_config = {
+ /* Enabled / OC PIN / Length */
+ { 1, 0, 0x0080 }, /* P00: 1st (left) USB3 (OC #0) */
+ { 1, 0, 0x0080 }, /* P01: 2nd (left) USB3 (OC #0) */
+ { 1, 1, 0x0080 }, /* P02: 1st Multibay USB3 (OC #1) */
+ { 1, 1, 0x0080 }, /* P03: 2nd Multibay USB3 (OC #1) */
+ { 1, 8, 0x0040 }, /* P04: MiniPCIe 1 USB2 (no OC) */
+ { 1, 8, 0x0040 }, /* P05: MiniPCIe 2 USB2 (no OC) */
+ { 1, 8, 0x0040 }, /* P06: USB Hub x4 USB2 (no OC) */
+ { 1, 8, 0x0040 }, /* P07: MiniPCIe 4 USB2 (no OC) */
+ { 1, 8, 0x0080 }, /* P08: SD card reader USB2 (no OC) */
+ { 1, 4, 0x0080 }, /* P09: 3rd (right) USB2 (OC #4) */
+ { 1, 5, 0x0040 }, /* P10: 4th (right) USB2 (OC #5) */
+ { 1, 8, 0x0040 }, /* P11: 3rd Multibay USB2 (no OC) */
+ { 1, 8, 0x0080 }, /* P12: misc internal USB2 (no OC) */
+ { 1, 6, 0x0080 }, /* P13: misc internal USB2 (OC #6) */
+ },
+ .usb3 = {
+ .mode = 3, /* Smart Auto? */
+ .hs_port_switch_mask = 0xf, /* All four ports. */
+ .preboot_support = 1, /* preOS driver? */
+ .xhci_streams = 1, /* Enable. */
+ },
+ .pcie_init = 1,
+ };
+ *pei_data = pei_data_template;
+}
+
+const struct southbridge_usb_port mainboard_usb_ports[] = {
+ /* Enabled / Power / OC PIN */
+ { 1, 1, 0 }, /* P00: 1st (left) USB3 (OC #0) */
+ { 1, 1, 0 }, /* P01: 2nd (left) USB3 (OC #0) */
+ { 1, 1, 1 }, /* P02: 1st Multibay USB3 (OC #1) */
+ { 1, 1, 1 }, /* P03: 2nd Multibay USB3 (OC #1) */
+ { 1, 0, 8 }, /* P04: MiniPCIe 1 USB2 (no OC) */
+ { 1, 0, 8 }, /* P05: MiniPCIe 2 USB2 (no OC) */
+ { 1, 0, 8 }, /* P06: USB Hub x4 USB2 (no OC) */
+ { 1, 0, 8 }, /* P07: MiniPCIe 4 USB2 (no OC) */
+ { 1, 1, 8 }, /* P08: SD card reader USB2 (no OC) */
+ { 1, 1, 4 }, /* P09: 3rd (right) USB2 (OC #4) */
+ { 1, 0, 5 }, /* P10: 4th (right) USB2 (OC #5) */
+ { 1, 0, 8 }, /* P11: 3rd Multibay USB2 (no OC) */
+ { 1, 1, 8 }, /* P12: misc internal USB2 (no OC) */
+ { 1, 1, 6 }, /* P13: misc internal USB2 (OC #6) */
+};
+
+void mainboard_get_spd(spd_raw_data *spd, bool id_only)
+{
+ read_spd(&spd[0], 0x50, id_only);
+ read_spd(&spd[1], 0x51, id_only);
+ read_spd(&spd[2], 0x52, id_only);
+ read_spd(&spd[3], 0x53, id_only);
+}
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