[coreboot-gerrit] Patch merged into coreboot/master: riscv: Add support for timer interrupts

[gerrit at coreboot.org]

the following patch was just integrated into master:
commit d9307c2e8aa3272fe57a67d2a5f31e38fa69d328
Author: Ronald G. Minnich <rminnich at gmail.com>
Date:   Mon Dec 12 15:09:42 2016 -0800

    riscv: Add support for timer interrupts
    
    RISCV requires that timer interrupts be handled in machine
    mode and delegated as necessary. Also you can only reset the
    timer interrupt by writing to mtimecmp. Further, you must
    write a number > mtime, not just != mtime. This rather clumsy
    situation requires that we write some value into the future
    into mtimecmp lest we never be able to leave machine mode as
    the interrupt either is not cleared or instantly reoccurs.
    
    This current code is tested and works for harvey (Plan 9)
    timer interrupts.
    
    Change-Id: I8538d5fd8d80d9347773c638f5cbf0da18dc1cae
    Signed-off-by: Ronald G. Minnich <rminnich at gmail.com>
    Reviewed-on: https://review.coreboot.org/17807
    Tested-by: build bot (Jenkins)
    Reviewed-by: Jonathan Neuschäfer <j.neuschaefer at gmx.net>


See https://review.coreboot.org/17807 for details.

-gerrit