[coreboot-gerrit] Patch set updated for coreboot: skylake: Restore target offset value after exiting from S3

[Sumeet R Pawnikar (sumeet.r.pawnikar@intel.com)]

Sumeet R Pawnikar (sumeet.r.pawnikar at intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17889

-gerrit

commit dd905e347a245dcc42683734ee0ae0e70ae888b9
Author: Sumeet Pawnikar <sumeet.r.pawnikar at intel.com>
Date:   Thu Dec 15 19:29:51 2016 +0530

    skylake: Restore target offset value after exiting from S3
    
    Before entering in S3, the target offset value is 10 degree C.
    After exiting from S3, Coreboot is not restoring the target offset value
    and it is setting it to the default value as 0.
    With the default target offset value as 0 and target temperature Tjmax
    value as 100 degree C, Pcode firmware starts taking prochot action at
    100 degree C [Tjmax-Offset].
    But before Pcode firmware starts prochot action at 100 degree C, device
    is getting shutdown at 99 degree C due to DPTF critical CPU temperature
    after exiting from S3.
    So, this patch restores the target offset value after exiting from S3.
    
    BUG=chrome-os-partner:59397
    BRANCH=None.
    TEST=Built for skylake platform and verified the target offset value
    before and after S3.
    
    Change-Id: Iacf64cbc40871bbec3bede65f196bf292e0149a6
    Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar at intel.com>
---
 src/mainboard/google/chell/devicetree.cb | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/src/mainboard/google/chell/devicetree.cb b/src/mainboard/google/chell/devicetree.cb
index 34250d3..2ffaec6 100644
--- a/src/mainboard/google/chell/devicetree.cb
+++ b/src/mainboard/google/chell/devicetree.cb
@@ -183,6 +183,8 @@ chip soc/intel/skylake
 	# PL2 override 15W
 	register "tdp_pl2_override" = "15"
 
+	register "tcc_offset" = "10"     # TCC of 90C
+
 	# Send an extra VR mailbox command for the supported MPS IMVP8 model
 	register "SendVrMbxCmd" = "1"