[coreboot-gerrit] Patch set updated for coreboot: skylake: Move TCC activation functionality under all boot flows

[Sumeet R Pawnikar (sumeet.r.pawnikar@intel.com)]

Sumeet R Pawnikar (sumeet.r.pawnikar at intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17889

-gerrit

commit 518597752c2d5eb7261423ffe88d5d00a2cd07e9
Author: Sumeet Pawnikar <sumeet.r.pawnikar at intel.com>
Date:   Thu Dec 15 19:29:51 2016 +0530

    skylake: Move TCC activation functionality under all boot flows
    
    TCC activation functinality has package scope, so explicitly
    setting it during all boot flows instead of relying on FSP
    code for setting it only in the warm and cold reboot case.
    
    BUG=chrome-os-partner:59397
    BRANCH=None.
    TEST=Built for skylake platform and verified the target offset value
    before and after S3.
    
    Change-Id: Iacf64cbc40871bbec3bede65f196bf292e0149a6
    Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar at intel.com>
---
 src/soc/intel/skylake/cpu.c             | 7 ++-----
 src/soc/intel/skylake/include/soc/cpu.h | 1 +
 src/soc/intel/skylake/systemagent.c     | 3 +++
 3 files changed, 6 insertions(+), 5 deletions(-)

diff --git a/src/soc/intel/skylake/cpu.c b/src/soc/intel/skylake/cpu.c
index 3ec8d2c..2e6270a 100644
--- a/src/soc/intel/skylake/cpu.c
+++ b/src/soc/intel/skylake/cpu.c
@@ -191,13 +191,13 @@ void set_power_limits(u8 power_limit_1_time)
 	}
 }
 
-static void configure_thermal_target(void)
+void configure_thermal_target(void)
 {
 	device_t dev = SA_DEV_ROOT;
 	config_t *conf = dev->chip_info;
 	msr_t msr;
 
-	/* Set TCC activaiton offset if supported */
+	/* Set TCC activation offset if supported */
 	msr = rdmsr(MSR_PLATFORM_INFO);
 	if ((msr.lo & (1 << 30)) && conf->tcc_offset) {
 		msr = rdmsr(MSR_TEMPERATURE_TARGET);
@@ -366,9 +366,6 @@ static void cpu_core_init(device_t cpu)
 	/* Configure Intel Speed Shift */
 	configure_isst();
 
-	/* Thermal throttle activation offset */
-	configure_thermal_target();
-
 	/* Enable Direct Cache Access */
 	configure_dca_cap();
 
diff --git a/src/soc/intel/skylake/include/soc/cpu.h b/src/soc/intel/skylake/include/soc/cpu.h
index ecb9833..b9d7684 100644
--- a/src/soc/intel/skylake/include/soc/cpu.h
+++ b/src/soc/intel/skylake/include/soc/cpu.h
@@ -58,6 +58,7 @@
 /* Configure power limits for turbo mode */
 void set_power_limits(u8 power_limit_1_time);
 int cpu_config_tdp_levels(void);
+void configure_thermal_target(void);
 
 /* CPU identification */
 u32 cpu_family_model(void);
diff --git a/src/soc/intel/skylake/systemagent.c b/src/soc/intel/skylake/systemagent.c
index 2f49633..7764471 100644
--- a/src/soc/intel/skylake/systemagent.c
+++ b/src/soc/intel/skylake/systemagent.c
@@ -400,6 +400,9 @@ static void systemagent_init(struct device *dev)
 	/* Configure turbo power limits 1ms after reset complete bit */
 	mdelay(1);
 	set_power_limits(28);
+
+	/* Thermal throttle activation offset */
+	configure_thermal_target();
 }
 
 static struct device_operations systemagent_ops = {