[coreboot-gerrit] New patch to review for coreboot: google/snappy: Update DPTF settings

[Wisley Chen (wisley.chen@quantatw.com)]

Wisley Chen (wisley.chen at quantatw.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17955

-gerrit

commit 55826505109f3ca0904d2a1264f0b976bb37ddb8
Author: Wisley Chen <wisley.chen at quantatw.com>
Date:   Fri Dec 23 04:43:18 2016 -0500

    google/snappy: Update DPTF settings
    
    1. Update DPTF TSR1/TSR2 passive/critial trigger points.
       TSR1 passive point:53, critial point:80
       TSR2 passive point:90, critial point:100
    
    2. Update PL1 Min to 1.6W amd PL1 Max to 12W
    
    3. Update thermal relationship table (TRT) setting.
    
    BUG=none
    BRANCH=master
    TEST=build, boot on snappy dut and verified by thermal team member.
    
    Change-Id: I8b4fb178daa7c2e4091a14779a125bd5e943d023
    Signed-off-by: Wisley Chen <wisley.chen at quantatw.com>
---
 .../reef/variants/snappy/include/variant/acpi/dptf.asl   | 16 ++++++++--------
 1 file changed, 8 insertions(+), 8 deletions(-)

diff --git a/src/mainboard/google/reef/variants/snappy/include/variant/acpi/dptf.asl b/src/mainboard/google/reef/variants/snappy/include/variant/acpi/dptf.asl
index f0e605b..e868c46 100644
--- a/src/mainboard/google/reef/variants/snappy/include/variant/acpi/dptf.asl
+++ b/src/mainboard/google/reef/variants/snappy/include/variant/acpi/dptf.asl
@@ -29,12 +29,12 @@
 
 #define DPTF_TSR1_SENSOR_ID	1
 #define DPTF_TSR1_SENSOR_NAME	"Ambient"
-#define DPTF_TSR1_PASSIVE	48
-#define DPTF_TSR1_CRITICAL	65
+#define DPTF_TSR1_PASSIVE	53
+#define DPTF_TSR1_CRITICAL	80
 
 #define DPTF_TSR2_SENSOR_ID	2
 #define DPTF_TSR2_SENSOR_NAME	"Charger"
-#define DPTF_TSR2_PASSIVE	85
+#define DPTF_TSR2_PASSIVE	90
 #define DPTF_TSR2_CRITICAL	100
 
 #define DPTF_ENABLE_CHARGER
@@ -61,10 +61,10 @@ Name (DTRT, Package () {
 #endif
 
 	/* CPU Effect on Temp Sensor 1 */
-	Package () { \_SB.PCI0.TCPU, \_SB.DPTF.TSR1, 100, 300, 0, 0, 0, 0 },
+	Package () { \_SB.PCI0.TCPU, \_SB.DPTF.TSR1, 200, 80, 0, 0, 0, 0 },
 
 	/* CPU Effect on Temp Sensor 2 */
-	Package () { \_SB.PCI0.TCPU, \_SB.DPTF.TSR2, 100, 600, 0, 0, 0, 0 },
+	Package () { \_SB.PCI0.TCPU, \_SB.DPTF.TSR2, 100, 150, 0, 0, 0, 0 },
 })
 
 Name (MPPC, Package ()
@@ -72,11 +72,11 @@ Name (MPPC, Package ()
 	0x2,		/* Revision */
 	Package () {	/* Power Limit 1 */
 		0,	/* PowerLimitIndex, 0 for Power Limit 1 */
-		3000,	/* PowerLimitMinimum */
-		6000,	/* PowerLimitMaximum */
+		1600,	/* PowerLimitMinimum */
+		12000,	/* PowerLimitMaximum */
 		1000,	/* TimeWindowMinimum */
 		1000,	/* TimeWindowMaximum */
-		300	/* StepSize */
+		200	/* StepSize */
 	},
 	Package () {	/* Power Limit 2 */
 		1,	/* PowerLimitIndex, 1 for Power Limit 2 */