[coreboot-gerrit] Patch set updated for coreboot: soc/intel/skylake: Initialize LPSS UART based on DRIVERS_UART_8250MEM_32
Subrata Banik (subrata.banik@intel.com)
gerrit at coreboot.org
Fri Dec 23 20:51:28 CET 2016
Subrata Banik (subrata.banik at intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17956
-gerrit
commit 29999fb6b4fe04c90dbbea35a49068241f2ccdeb
Author: Subrata Banik <subrata.banik at intel.com>
Date: Fri Dec 23 16:42:55 2016 +0530
soc/intel/skylake: Initialize LPSS UART based on DRIVERS_UART_8250MEM_32
pch_uart_init and base address assignment should be done
based on DRIVERS_UART_8250MEM_32 config selection. Enabling
legacy UART for debug on RVP does not require additional UART2
programming.
TEST=Build and boot SKL RVP to have serial log through legacy UART.
Change-Id: Iea4f204275c6eb78646f510a7097f7cf8470b576
Signed-off-by: Subrata Banik <subrata.banik at intel.com>
---
src/soc/intel/skylake/bootblock/bootblock.c | 6 ++++--
1 file changed, 4 insertions(+), 2 deletions(-)
diff --git a/src/soc/intel/skylake/bootblock/bootblock.c b/src/soc/intel/skylake/bootblock/bootblock.c
index 93a031f..1c0892f 100644
--- a/src/soc/intel/skylake/bootblock/bootblock.c
+++ b/src/soc/intel/skylake/bootblock/bootblock.c
@@ -29,8 +29,10 @@ void bootblock_soc_early_init(void)
bootblock_cpu_init();
pch_early_iorange_init();
- if (IS_ENABLED(CONFIG_UART_DEBUG))
- pch_uart_init();
+ if (!IS_ENABLED(CONFIG_DRIVERS_UART_8250MEM_32))
+ return;
+
+ pch_uart_init();
}
void bootblock_soc_init(void)
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