[coreboot-gerrit] Patch set updated for coreboot: mainboard/google/reef: Update DPTF parameters EVT1_v0.3

[Tim Chen (Tim-Chen@quantatw.com)]

Tim Chen (Tim-Chen at quantatw.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17975

-gerrit

commit 689a945d2f0ca6a58c0d22b564abfc87190e9c83
Author: Tim Chen <Tim-Chen at quantatw.com>
Date:   Wed Dec 28 14:44:52 2016 +0800

    mainboard/google/reef: Update DPTF parameters EVT1_v0.3
    
    Update the DPTF parameters based on thermal test result.
    (ZHT_DPTF_EVT1_v0.3_20161227.xlsx)
    
    1. Update DPTF CPU/TSR1/TSR2 passive/critial trigger points.
       CPU  critical point:103
       TSR1 passive point:45
       TSR2 passive point:55, critical point:90
    
    2. Change thermal relationship table (TRT) setting.
       Change CPU Throttle Effect on CPU sample rate to 3secs
       Change Charger Effect on Temp Sensor 2 sample rate to 60secs
       Change CPU Effect on Temp Sensor 1 sample rate to 8secs
    
    BUG=chrome-os-partner:60038
    BRANCH=master
    TEST=build and boot on electro dut
    
    Change-Id: I3746750f7ea4a2e01153a36c28a5c33140c9e38c
    Signed-off-by: Tim Chen <Tim-Chen at quantatw.com>
---
 .../variants/baseboard/include/baseboard/acpi/dptf.asl     | 14 +++++++-------
 1 file changed, 7 insertions(+), 7 deletions(-)

diff --git a/src/mainboard/google/reef/variants/baseboard/include/baseboard/acpi/dptf.asl b/src/mainboard/google/reef/variants/baseboard/include/baseboard/acpi/dptf.asl
index 116e675..87d3fa3 100644
--- a/src/mainboard/google/reef/variants/baseboard/include/baseboard/acpi/dptf.asl
+++ b/src/mainboard/google/reef/variants/baseboard/include/baseboard/acpi/dptf.asl
@@ -15,7 +15,7 @@
  */
 
 #define DPTF_CPU_PASSIVE	95
-#define DPTF_CPU_CRITICAL	99
+#define DPTF_CPU_CRITICAL	103
 #define DPTF_CPU_ACTIVE_AC0	90
 #define DPTF_CPU_ACTIVE_AC1	80
 #define DPTF_CPU_ACTIVE_AC2	70
@@ -29,13 +29,13 @@
 
 #define DPTF_TSR1_SENSOR_ID	1
 #define DPTF_TSR1_SENSOR_NAME	"Ambient"
-#define DPTF_TSR1_PASSIVE	46
+#define DPTF_TSR1_PASSIVE	45
 #define DPTF_TSR1_CRITICAL	75
 
 #define DPTF_TSR2_SENSOR_ID	2
 #define DPTF_TSR2_SENSOR_NAME	"Charger"
-#define DPTF_TSR2_PASSIVE	100
-#define DPTF_TSR2_CRITICAL	125
+#define DPTF_TSR2_PASSIVE	55
+#define DPTF_TSR2_CRITICAL	90
 
 #define DPTF_ENABLE_CHARGER
 
@@ -50,18 +50,18 @@ Name (CHPS, Package () {
 
 Name (DTRT, Package () {
 	/* CPU Throttle Effect on CPU */
-	Package () { \_SB.PCI0.TCPU, \_SB.PCI0.TCPU, 100, 800, 0, 0, 0, 0 },
+	Package () { \_SB.PCI0.TCPU, \_SB.PCI0.TCPU, 100, 30, 0, 0, 0, 0 },
 
 	/* CPU Effect on Temp Sensor 0 */
 	Package () { \_SB.PCI0.TCPU, \_SB.DPTF.TSR0, 100, 1200, 0, 0, 0, 0 },
 
 #ifdef DPTF_ENABLE_CHARGER
 	/* Charger Effect on Temp Sensor 2 */
-	Package () { \_SB.DPTF.TCHG, \_SB.DPTF.TSR2, 200, 1200, 0, 0, 0, 0 },
+	Package () { \_SB.DPTF.TCHG, \_SB.DPTF.TSR2, 200, 600, 0, 0, 0, 0 },
 #endif
 
 	/* CPU Effect on Temp Sensor 1 */
-	Package () { \_SB.PCI0.TCPU, \_SB.DPTF.TSR1, 100, 600, 0, 0, 0, 0 },
+	Package () { \_SB.PCI0.TCPU, \_SB.DPTF.TSR1, 100, 80, 0, 0, 0, 0 },
 
 	/* CPU Effect on Temp Sensor 2 */
 	Package () { \_SB.PCI0.TCPU, \_SB.DPTF.TSR2, 100, 1200, 0, 0, 0, 0 },