[coreboot-gerrit] New patch to review for coreboot: [WIP] Add Exar superIO chip XR28V382
Patrick Agrain (patrick.agrain@al-enterprise.com)
gerrit at coreboot.org
Thu Dec 29 10:30:26 CET 2016
Patrick Agrain (patrick.agrain at al-enterprise.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17987
-gerrit
commit 1bb560449aca9820f8930df15448c1f39b2b2ff3
Author: Patrick Agrain <patrick.agrain at al-enterprise.com>
Date: Thu Dec 29 01:06:21 2016 -0800
[WIP] Add Exar superIO chip XR28V382
This commit is to push new code to support the superIO chip from Exar
XR28V382 in the coreboot source tree and to allow reviewers to tell
what could be missing.
First test shows following messages on console (DEBUG level):
PCI: Static device PCI: 00:01.0 not found, disabling it.
child PNP: 002e.0 not a PCI device
And later...
PCI: Left over static devices:
PNP: 002e.0
PNP: 002e.1
PNP: 002e.8
PCI: Check your devicetree.cb.
PCI: pci_scan_bus for bus 01
Change-Id: Iabb5eec22d831369b41c5c8df47a1f55b5724ffe
---
src/superio/exar/Makefile.inc | 17 ++++++
src/superio/exar/xr28v382/Kconfig | 20 +++++++
src/superio/exar/xr28v382/Makefile.inc | 19 +++++++
src/superio/exar/xr28v382/early_init.c | 67 ++++++++++++++++++++++++
src/superio/exar/xr28v382/superio.c | 96 ++++++++++++++++++++++++++++++++++
src/superio/exar/xr28v382/xr28v382.h | 43 +++++++++++++++
6 files changed, 262 insertions(+)
diff --git a/src/superio/exar/Makefile.inc b/src/superio/exar/Makefile.inc
new file mode 100644
index 0000000..862617b
--- /dev/null
+++ b/src/superio/exar/Makefile.inc
@@ -0,0 +1,17 @@
+##
+## This file is part of the coreboot project.
+##
+## Copyright (C) 2009 Ronald G. Minnich
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; version 2 of the License.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+## GNU General Public License for more details.
+##
+
+subdirs-y += xr28v382
+
diff --git a/src/superio/exar/xr28v382/Kconfig b/src/superio/exar/xr28v382/Kconfig
new file mode 100644
index 0000000..22311b5
--- /dev/null
+++ b/src/superio/exar/xr28v382/Kconfig
@@ -0,0 +1,20 @@
+##
+## This file is part of the coreboot project.
+##
+## Copyright (C) 2009 Ronald G. Minnich
+## Copyright (C) 2014 Edward O'Callaghan <eocallaghan at alterapraxis.com>
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; version 2 of the License.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+## GNU General Public License for more details.
+##
+
+config SUPERIO_EXAR_XR28V382
+ bool
+ default y
+
diff --git a/src/superio/exar/xr28v382/Makefile.inc b/src/superio/exar/xr28v382/Makefile.inc
new file mode 100644
index 0000000..0c59263
--- /dev/null
+++ b/src/superio/exar/xr28v382/Makefile.inc
@@ -0,0 +1,19 @@
+##
+## This file is part of the coreboot project.
+##
+## Copyright (C) 2016 Patrick Agrain <patrick.agrain at al-enterprise.com>
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; either version 2 of the License, or
+## (at your option) any later version.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+## GNU General Public License for more details.
+##
+
+romstage-$(CONFIG_SUPERIO_EXAR_XR28V382) += early_init.c
+ramstage-$(CONFIG_SUPERIO_EXAR_XR28V382) += superio.c
+
diff --git a/src/superio/exar/xr28v382/early_init.c b/src/superio/exar/xr28v382/early_init.c
new file mode 100644
index 0000000..2c72647
--- /dev/null
+++ b/src/superio/exar/xr28v382/early_init.c
@@ -0,0 +1,67 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2008 Arastra, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <arch/io.h>
+#include <device/pnp.h>
+#include <stdint.h>
+#include "xr28v382.h"
+
+static void pnp_enter_ext_func_mode(pnp_devfn_t dev)
+{
+ u16 port = dev >> 8;
+
+ outb(0x67, port);
+ outb(0x67, port);
+}
+
+static void pnp_exit_ext_func_mode(pnp_devfn_t dev)
+{
+ u16 port = dev >> 8;
+
+ outb(0xAA, port);
+}
+
+void xr28v382_setup_chip(pnp_devfn_t dev)
+{
+ u8 reg8;
+
+ pnp_enter_ext_func_mode(dev);
+
+ /* Setup Input Clock - 24MHz */
+ reg8 = pnp_read_config(dev, XR28V382_CLKSEL_REG);
+ reg8 &= 0xFE;
+ pnp_write_config(dev, XR28V382_CLKSEL_REG, reg8);
+
+ /* Setup Entry key - 0x67 */
+ /* Setup Configuration Port - 0x2E/0x2F */
+ reg8 = pnp_read_config(dev, XR28V382_PORT_SEL_REG);
+ reg8 |= 0x03; /* [1-0] = '11' */
+ reg8 &= 0xEF; /* [4] = '0' */
+ pnp_write_config(dev, XR28V382_PORT_SEL_REG, reg8);
+
+ pnp_exit_ext_func_mode(dev);
+}
+
+void xr28v382_enable_serial(pnp_devfn_t dev, u16 iobase)
+{
+ pnp_enter_ext_func_mode(dev);
+ pnp_set_logical_device(dev);
+ pnp_set_enable(dev, 0);
+ pnp_set_iobase(dev, PNP_IDX_IO0, iobase);
+ pnp_set_enable(dev, 1);
+ pnp_exit_ext_func_mode(dev);
+}
+
diff --git a/src/superio/exar/xr28v382/superio.c b/src/superio/exar/xr28v382/superio.c
new file mode 100644
index 0000000..0e07cdd
--- /dev/null
+++ b/src/superio/exar/xr28v382/superio.c
@@ -0,0 +1,96 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2016 Patrick Agrain <patrick.agrain at al-enterprise.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <device/device.h>
+#include <device/pnp.h>
+#include <console/console.h>
+#include <pc80/keyboard.h>
+#include <arch/io.h>
+#include <stdlib.h>
+#include <superio/conf_mode.h>
+
+#include "xr28v382.h"
+
+static void pnp_enter_ext_func_mode(struct device *dev)
+{
+ outb(0x67, dev->path.pnp.port);
+ outb(0x67, dev->path.pnp.port);
+}
+
+static void pnp_exit_ext_func_mode(struct device *dev)
+{
+ outb(0xAA, dev->path.pnp.port);
+}
+
+static void xr28v382_init(struct device *dev)
+{
+ u16 did;
+
+ printk(BIOS_DEBUG, "EXAR: Enter init()\n");
+
+ if (!dev->enabled)
+ return;
+
+ switch (dev->path.pnp.device) {
+ case XR28V382_SP1:
+ pnp_enter_ext_func_mode(dev);
+ outb(0x20, dev->path.pnp.port);
+ did = (inb(dev->path.pnp.port+1) << 8);
+ outb(0x21, dev->path.pnp.port);
+ did |= inb(dev->path.pnp.port+1);
+ pnp_exit_ext_func_mode(dev);
+ printk(BIOS_DEBUG, "EXAR: Get Device ID 0x%04x\n", did);
+ break;
+ case XR28V382_SP2:
+ /* TODO */
+ break;
+ case XR28V382_WDT:
+ /* TODO */
+ break;
+ }
+}
+
+static const struct pnp_mode_ops pnp_conf_mode_xr28v382 = {
+ .enter_conf_mode = pnp_enter_ext_func_mode,
+ .exit_conf_mode = pnp_exit_ext_func_mode,
+};
+
+static struct device_operations ops = {
+ .read_resources = pnp_read_resources,
+ .set_resources = pnp_set_resources,
+ .enable_resources = pnp_enable_resources,
+ .enable = pnp_alt_enable,
+ .init = xr28v382_init,
+ .ops_pnp_mode = &pnp_conf_mode_xr28v382,
+};
+
+static struct pnp_info pnp_dev_info[] = {
+ { &ops, XR28V382_SP1, PNP_IO0 | PNP_IRQ0, {0x07f8, 0}, },
+ { &ops, XR28V382_SP2, PNP_IO0 | PNP_IRQ0, {0x07f8, 0}, },
+ { &ops, XR28V382_WDT, },
+};
+
+static void enable_dev(struct device *dev)
+{
+ pnp_enable_devices(dev, &ops, ARRAY_SIZE(pnp_dev_info), pnp_dev_info);
+}
+
+struct chip_operations superio_exar_xr28v382_ops = {
+ CHIP_NAME("EXAR XR28V382 Super I/O")
+ .enable_dev = enable_dev,
+};
+
+
diff --git a/src/superio/exar/xr28v382/xr28v382.h b/src/superio/exar/xr28v382/xr28v382.h
new file mode 100644
index 0000000..51664c8
--- /dev/null
+++ b/src/superio/exar/xr28v382/xr28v382.h
@@ -0,0 +1,43 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2016 Patrick Agrain <patrick.agrain at al-enterprise.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef SUPERIO_EXAR_XR28V382_H
+#define SUPERIO_EXAR_XR28V382_H
+
+#include <stdint.h>
+
+/* Datasheet: https://www.exar.com/content/document.ashx?id=21367 */
+
+#define XR28V382_SP1 0x00 /* Com1 */
+#define XR28V382_SP2 0x01 /* Com2 */
+#define XR28V382_WDT 0x08 /* Watchdog */
+
+/* Registers and bit definitions: */
+#define XR28V382_SW_RESET_REG 0x02
+#define XR28V382_LDN_REG 0x07
+#define XR28V382_DID_MSB_REG 0x20
+#define XR28V382_DID_LSB_REG 0x21
+#define XR28V382_VID_MSB 0x23
+#define XR28V382_VID_LSB 0x24
+#define XR28V382_CLKSEL_REG 0x25
+#define XR28V382_WDTCTRL_REG 0x26
+#define XR28V382_PORT_SEL_REG 0x27
+
+void xr28v382_enable_serial(pnp_devfn_t dev, u16 iobase);
+void xr28v382_setup_chip(pnp_devfn_t dev);
+
+#endif /* SUPERIO_EXAR_XR28V382_H */
+
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