[coreboot-gerrit] New patch to review for coreboot: mb/asus/p5gc-mx: Remove extra BSEL strap check

[Arthur Heymans (arthur@aheymans.xyz)]

Arthur Heymans (arthur at aheymans.xyz) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17997

-gerrit

commit a2e1fee1e98dee2d35754413b2b05fc8ac33fec3
Author: Arthur Heymans <arthur at aheymans.xyz>
Date:   Fri Dec 30 18:52:53 2016 +0100

    mb/asus/p5gc-mx: Remove extra BSEL strap check
    
    This extra check is based on comparing CPU BSEL pins and reports in
    MCH configuration. This gives false positives in the case of 1333MHz
    CPUs which automatically get downgraded to 1067MHz by the northbridge
    (max supported frequency by 945gc).
    
    TESTED with Intel Xeon 5460 (does not boot but completes raminit)
    
    Change-Id: I34cb37912906c803abdad0adbd9c589ca86a67c7
    Signed-off-by: Arthur Heymans <arthur at aheymans.xyz>
---
 src/mainboard/asus/p5gc-mx/romstage.c | 7 +------
 1 file changed, 1 insertion(+), 6 deletions(-)

diff --git a/src/mainboard/asus/p5gc-mx/romstage.c b/src/mainboard/asus/p5gc-mx/romstage.c
index 9be061f..8785595 100644
--- a/src/mainboard/asus/p5gc-mx/romstage.c
+++ b/src/mainboard/asus/p5gc-mx/romstage.c
@@ -242,12 +242,7 @@ void mainboard_romstage_entry(unsigned long bist)
 	i945_early_initialization();
 
 	m_bsel = MCHBAR32(CLKCFG) & 7;
-	printk(BIOS_DEBUG, "CPU BSEL: 0x%x\n MCH BSEL: 0x%x\n", c_bsel, m_bsel);
-	if (c_bsel != m_bsel) { /* Should not happen */
-		printk(BIOS_DEBUG, "Setting BSEL straps, resetting...\n");
-		outb(0xe, 0xcf9);
-		halt();
-	}
+	printk(BIOS_DEBUG, "CPU BSEL: 0x%x\nMCH BSEL: 0x%x\n", c_bsel, m_bsel);
 
 	s3resume = southbridge_detect_s3_resume();