[coreboot-gerrit] Patch set updated for coreboot: southbridge/amd/sb700: Enable extended APIC ID when Kconfig option set

[Timothy Pearson (tpearson@raptorengineeringinc.com)]

Timothy Pearson (tpearson at raptorengineeringinc.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13160

-gerrit

commit 066e48c7c9c0c216384f04ddd3662f7f69d77d7c
Author: Timothy Pearson <tpearson at raptorengineeringinc.com>
Date:   Tue Nov 24 14:11:58 2015 -0600

    southbridge/amd/sb700: Enable extended APIC ID when Kconfig option set
    
    Change-Id: I52fc2c2294edead3b5dacf397c0a1ab2e08b1e3f
    Signed-off-by: Timothy Pearson <tpearson at raptorengineeringinc.com>
---
 src/southbridge/amd/sb700/sm.c | 6 ++++--
 1 file changed, 4 insertions(+), 2 deletions(-)

diff --git a/src/southbridge/amd/sb700/sm.c b/src/southbridge/amd/sb700/sm.c
index 5f6d20e..6d93b17 100644
--- a/src/southbridge/amd/sb700/sm.c
+++ b/src/southbridge/amd/sb700/sm.c
@@ -308,9 +308,11 @@ static void sm_init(device_t dev)
 		dword |= 0x1;
 		pci_write_config32(dev, SB_MMIO_CFG_REG, dword);
 	}
-	//ACPI_DISABLE_TIMER_IRQ_ENHANCEMENT_FOR_8254_TIMER
  	byte = pci_read_config8(dev, 0xAE);
-	byte |= 1 << 5;
+ 	if (IS_ENABLED(CONFIG_ENABLE_APIC_EXT_ID))
+ 		byte |= 1 << 4;
+	byte |= 1 << 5;	/* ACPI_DISABLE_TIMER_IRQ_ENHANCEMENT_FOR_8254_TIMER */
+	byte |= 1 << 6;	/* Enable arbiter between APIC and PIC interrupts */
  	pci_write_config8(dev, 0xAE, byte);
 
 	/* 4.11:Programming Cycle Delay for AB and BIF Clock Gating */