[coreboot-gerrit] New patch to review for coreboot: soc/intel/broadwell: Fix UART compilation

[Stefan Reinauer (stefan.reinauer@coreboot.org)]

Stefan Reinauer (stefan.reinauer at coreboot.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13554

-gerrit

commit a444dea14fa0a5900aee3b876c9ee49a71a48e89
Author: Stefan Reinauer <stefan.reinauer at coreboot.org>
Date:   Mon Feb 1 16:36:07 2016 -0800

    soc/intel/broadwell: Fix UART compilation
    
    Change-Id: I7fe356041c6ac69a30e0e87d9a8649abef6996b7
    Signed-off-by: Stefan Reinauer <stefan.reinauer at coreboot.org>
---
 src/soc/intel/broadwell/Makefile.inc    |  3 +++
 src/soc/intel/broadwell/romstage/uart.c | 11 ++++++----
 src/soc/intel/broadwell/serialio.c      | 16 +-------------
 src/soc/intel/broadwell/uart_debug.c    | 37 +++++++++++++++++++++++++++++++++
 4 files changed, 48 insertions(+), 19 deletions(-)

diff --git a/src/soc/intel/broadwell/Makefile.inc b/src/soc/intel/broadwell/Makefile.inc
index 4da8c20..4159b96 100644
--- a/src/soc/intel/broadwell/Makefile.inc
+++ b/src/soc/intel/broadwell/Makefile.inc
@@ -65,6 +65,9 @@ ramstage-$(CONFIG_USBDEBUG) += usb_debug.c
 ramstage-y += ehci.c
 ramstage-y += xhci.c
 smm-y      += xhci.c
+romstage-y += uart_debug.c
+ramstage-y += uart_debug.c
+smm-y += uart_debug.c
 
 ramstage-srcs += src/mainboard/$(MAINBOARDDIR)/hda_verb.c
 
diff --git a/src/soc/intel/broadwell/romstage/uart.c b/src/soc/intel/broadwell/romstage/uart.c
index 1ea7cc2..732f7d7 100644
--- a/src/soc/intel/broadwell/romstage/uart.c
+++ b/src/soc/intel/broadwell/romstage/uart.c
@@ -19,11 +19,14 @@
 #include <device/pci_def.h>
 #include <reg_script.h>
 #include <stdint.h>
-#include <uart8250.h>
+#include <drivers/uart/uart8250reg.h>
+#include <drivers/uart/uart8250mem.h>
 #include <soc/iobp.h>
 #include <soc/serialio.h>
+#include <soc/pci_devs.h>
+#include <soc/romstage.h>
 
-const struct reg_script uart_init[] = {
+const struct reg_script uart_init_script[] = {
 	/* Set MMIO BAR */
 	REG_PCI_WRITE32(PCI_BASE_ADDRESS_0, CONFIG_TTYS0_BASE),
 	/* Enable Memory access and Bus Master */
@@ -71,11 +74,11 @@ void pch_uart_init(void)
 	pch_iobp_update(0xcb000180, ~0x0000003f, 0x0000003f);
 
 	/* Initialize chipset uart interface */
-	reg_script_run_on_dev(dev, uart_init);
+	reg_script_run_on_dev(dev, uart_init_script);
 
 	/*
 	 * Perform standard UART initialization
 	 * Divisor 1 is 115200 BAUD
 	 */
-	uart8250_mem_init(CONFIG_TTYS0_BASE, 1);
+	uart8250_mem_init((void *)CONFIG_TTYS0_BASE, 1);
 }
diff --git a/src/soc/intel/broadwell/serialio.c b/src/soc/intel/broadwell/serialio.c
index a73312c..83f6784 100644
--- a/src/soc/intel/broadwell/serialio.c
+++ b/src/soc/intel/broadwell/serialio.c
@@ -273,23 +273,9 @@ static void serialio_init(struct device *dev)
 	}
 }
 
-static void serialio_set_resources(struct device *dev)
-{
-	pci_dev_set_resources(dev);
-
-#if CONFIG_INTEL_PCH_UART_CONSOLE
-	/* Update UART base address if used for debug */
-	if (serialio_uart_is_debug(dev)) {
-		struct resource *res = find_resource(dev, PCI_BASE_ADDRESS_0);
-		if (res)
-			uartmem_setbaseaddr(res->base);
-	}
-#endif
-}
-
 static struct device_operations device_ops = {
 	.read_resources		= &pci_dev_read_resources,
-	.set_resources		= &serialio_set_resources,
+	.set_resources		= &pci_dev_set_resources,
 	.enable_resources	= &pci_dev_enable_resources,
 	.init			= &serialio_init,
 	.ops_pci		= &broadwell_pci_ops,
diff --git a/src/soc/intel/broadwell/uart_debug.c b/src/soc/intel/broadwell/uart_debug.c
new file mode 100644
index 0000000..50afc75
--- /dev/null
+++ b/src/soc/intel/broadwell/uart_debug.c
@@ -0,0 +1,37 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2015 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <stddef.h>
+#include <console/uart.h>
+#include <soc/iomap.h>
+#include <soc/serialio.h>
+
+unsigned int uart_platform_refclk(void)
+{
+	/*
+	 * Set M and N divisor inputs and enable clock.
+	 * Main reference frequency to UART is:
+	 *  120MHz * M / N = 120MHz * 48 / 3125 = 1843200Hz
+	 * The different order below is to handle integer math overflow.
+	 */
+	return 120 * MHz / SIO_REG_PPR_CLOCK_N_DIV * SIO_REG_PPR_CLOCK_M_DIV;
+}
+
+uintptr_t uart_platform_base(int idx)
+{
+	/* Same base address for all debug port usage. In reality UART2
+	 * is currently only supported. */
+	return CONFIG_TTYS0_BASE;
+}