[coreboot-gerrit] Patch set updated for coreboot: soc/apollolake: Add tsc_freq_mhz() functionality for udelay()

[Alexandru Gagniuc (mr.nuke.me@gmail.com)]

Alexandru Gagniuc (mr.nuke.me at gmail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13303

-gerrit

commit 62778a6106c09fc0b4a25e8cbf33432b3f213dd6
Author: Alexandru Gagniuc <alexandrux.gagniuc at intel.com>
Date:   Tue Oct 6 16:31:34 2015 -0700

    soc/apollolake: Add tsc_freq_mhz() functionality for udelay()
    
    Change-Id: I2f1147cefe2438992bff45fc0a1e91064217915d
    Signed-off-by: Alexandru Gagniuc <alexandrux.gagniuc at intel.com>
---
 src/soc/intel/apollolake/Kconfig           |  1 +
 src/soc/intel/apollolake/Makefile.inc      |  5 +++++
 src/soc/intel/apollolake/include/soc/cpu.h | 20 ++++++++++++++++++++
 src/soc/intel/apollolake/tsc_freq.c        | 21 +++++++++++++++++++++
 4 files changed, 47 insertions(+)

diff --git a/src/soc/intel/apollolake/Kconfig b/src/soc/intel/apollolake/Kconfig
index f7ae68e..825a40f 100644
--- a/src/soc/intel/apollolake/Kconfig
+++ b/src/soc/intel/apollolake/Kconfig
@@ -32,6 +32,7 @@ config CPU_SPECIFIC_OPTIONS
 	select RELOCATABLE_RAMSTAGE	# Build fails if this is not selected
 	select SOC_INTEL_COMMON
 	select UDELAY_TSC
+	select TSC_CONSTANT_RATE
 
 config MMCONF_BASE_ADDRESS
 	hex "PCI MMIO Base Address"
diff --git a/src/soc/intel/apollolake/Makefile.inc b/src/soc/intel/apollolake/Makefile.inc
index cc3e013..17b4ae4 100644
--- a/src/soc/intel/apollolake/Makefile.inc
+++ b/src/soc/intel/apollolake/Makefile.inc
@@ -10,6 +10,11 @@ subdirs-y += ../../../cpu/x86/tsc
 bootblock-y += bootblock/bootblock_car.c
 bootblock-y += bootblock/cache_as_ram.S
 bootblock-y += bootblock/early_chipset_config.S
+bootblock-y += tsc_freq.c
+
+romstage-y += tsc_freq.c
+
+ramstage-y += tsc_freq.c
 
 romstage-y += placeholders.c
 smm-y += placeholders.c
diff --git a/src/soc/intel/apollolake/include/soc/cpu.h b/src/soc/intel/apollolake/include/soc/cpu.h
new file mode 100644
index 0000000..d0d6afd
--- /dev/null
+++ b/src/soc/intel/apollolake/include/soc/cpu.h
@@ -0,0 +1,20 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2015 Intel Corp.
+ * (Written by Alexandru Gagniuc <alexandrux.gagniuc at intel.com> for Intel Corp.)
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+#ifndef _SOC_APOLLOLAKE_CPU_H_
+#define _SOC_APOLLOLAKE_CPU_H_
+
+#define MSR_PLATFORM_INFO	0xce
+
+#define BASE_CLOCK_MHZ		100
+
+#endif /* _SOC_APOLLOLAKE_CPU_H_ */
diff --git a/src/soc/intel/apollolake/tsc_freq.c b/src/soc/intel/apollolake/tsc_freq.c
new file mode 100644
index 0000000..2e90ef2
--- /dev/null
+++ b/src/soc/intel/apollolake/tsc_freq.c
@@ -0,0 +1,21 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2015 Intel Corp.
+ * (Written by Alexandru Gagniuc <alexandrux.gagniuc at intel.com> for Intel Corp.)
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+#include <cpu/x86/msr.h>
+#include <cpu/x86/tsc.h>
+#include <soc/cpu.h>
+
+unsigned long tsc_freq_mhz(void)
+{
+	msr_t msr = rdmsr(MSR_PLATFORM_INFO);
+	return (BASE_CLOCK_MHZ * ((msr.lo >> 8) & 0xff));
+}