[coreboot-gerrit] New patch to review for coreboot: intel/skylake: implement vboot_platform_is_resuming()

[Patrick Georgi (pgeorgi@google.com)]

Patrick Georgi (pgeorgi at google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13578

-gerrit

commit 7311a42011c15eaba4b466ac59cf4e94a08ccdbf
Author: Aaron Durbin <adurbin at chromium.org>
Date:   Fri Jan 22 15:43:43 2016 -0600

    intel/skylake: implement vboot_platform_is_resuming()
    
    To allow skylake platforms to run with verified memory init
    code the chipset needs to implement vboot_platform_is_resuming()
    so that the vboot code can make proper decisions.
    
    BUG=chrome-os-partner:46049
    BRANCH=glados
    TEST=Suspended and resumed on chell. Also, tested with an EC build
         which returns a bad hash to ensure that is properly caught.
    
    Change-Id: I508a339c07dcc9e7c56a0df4201660827b3ae07a
    Signed-off-by: Patrick Georgi <pgeorgi at chromium.org>
    Original-Commit-Id: a3e11789339bcd8fc8fc99b704c6a1110acf5302
    Original-Change-Id: I40264019eb28e85795258112c720056a6a3fc523
    Original-Signed-off-by: Aaron Durbin <adurbin at chromium.org>
    Original-Reviewed-on: https://chromium-review.googlesource.com/323503
    Original-Reviewed-by: Duncan Laurie <dlaurie at chromium.org>
---
 src/soc/intel/skylake/romstage/Makefile.inc  | 1 +
 src/soc/intel/skylake/romstage/power_state.c | 7 +++++++
 2 files changed, 8 insertions(+)

diff --git a/src/soc/intel/skylake/romstage/Makefile.inc b/src/soc/intel/skylake/romstage/Makefile.inc
index 00943ba..194091f 100644
--- a/src/soc/intel/skylake/romstage/Makefile.inc
+++ b/src/soc/intel/skylake/romstage/Makefile.inc
@@ -1,5 +1,6 @@
 verstage-y += cpu.c
 verstage-y += pch.c
+verstage-y += power_state.c
 verstage-y += report_platform.c
 verstage-y += romstage.c
 verstage-y += smbus.c
diff --git a/src/soc/intel/skylake/romstage/power_state.c b/src/soc/intel/skylake/romstage/power_state.c
index d91e197..cbef09a 100644
--- a/src/soc/intel/skylake/romstage/power_state.c
+++ b/src/soc/intel/skylake/romstage/power_state.c
@@ -30,6 +30,7 @@
 #include <soc/pci_devs.h>
 #include <soc/pm.h>
 #include <soc/romstage.h>
+#include <vendorcode/google/chromeos/vboot_common.h>
 
 static struct chipset_power_state power_state CAR_GLOBAL;
 
@@ -151,3 +152,9 @@ struct chipset_power_state *fill_power_state(void)
 
 	return ps;
 }
+
+int vboot_platform_is_resuming(void)
+{
+	int typ = (inl(ACPI_BASE_ADDRESS + PM1_CNT) & SLP_TYP) >> SLP_TYP_SHIFT;
+	return typ == SLP_TYP_S3;
+}