[coreboot-gerrit] New patch to review for coreboot: intel/skylake: unconditionally set SPI controller BAR

[Patrick Georgi (pgeorgi@google.com)]

Patrick Georgi (pgeorgi at google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13587

-gerrit

commit 1b74e0de8f081d0b7733c38ef608e5b5a48df0eb
Author: Aaron Durbin <adurbin at chromium.org>
Date:   Wed Dec 16 17:11:27 2015 -0600

    intel/skylake: unconditionally set SPI controller BAR
    
    The setting of the SPI controller BAR was conditional
    on the nominal frequency being set. Therefore, that doesn't
    mean the SPI BAR is set on all boots. Move the setting of
    the BAR in the southbridge_bootblock_init() which is called
    prioer to cpu_bootblock_init().
    
    BUG=chrome-os-partner:44827
    BRANCH=None
    TEST=Confirmed spibar is always set on glados.
    
    Change-Id: Ia58447d70f5e39a4336d4d08593f143332de833a
    Signed-off-by: Patrick Georgi <pgeorgi at chromium.org>
    Original-Commit-Id: 56fff7c25c2eb0ccd90e08f71c064b83c66640f8
    Original-Change-Id: I1e0cff783f4b072b80589a3a84703a262b86be3a
    Original-Signed-off-by: Aaron Durbin <adurbin at chromium.org>
    Original-Reviewed-on: https://chromium-review.googlesource.com/319461
    Original-Reviewed-by: Duncan Laurie <dlaurie at chromium.org>
---
 src/soc/intel/skylake/bootblock/cpu.c | 18 +-----------------
 src/soc/intel/skylake/bootblock/pch.c | 22 ++++++++++++++++++++++
 2 files changed, 23 insertions(+), 17 deletions(-)

diff --git a/src/soc/intel/skylake/bootblock/cpu.c b/src/soc/intel/skylake/bootblock/cpu.c
index 6fc4d92..d713974 100644
--- a/src/soc/intel/skylake/bootblock/cpu.c
+++ b/src/soc/intel/skylake/bootblock/cpu.c
@@ -74,25 +74,9 @@ static void bootblock_mdelay(int ms)
 
 static void set_pch_cpu_strap(u8 flex_ratio)
 {
-	device_t dev = PCH_DEV_SPI;
 	uint8_t *spibar = (void *)SPI_BASE_ADDRESS;
 	u32 ssl, ssms, soft_reset_data;
-	u8 pcireg;
-
-	/* Assign Resources to SPI Controller */
-	/* Clear BIT 1-2 SPI Command Register */
-	pcireg = pci_read_config8(dev, PCI_COMMAND);
-	pcireg &= ~(PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY);
-	pci_write_config8(dev, PCI_COMMAND, pcireg);
-
-	/* Program Temporary BAR for SPI */
-	pci_write_config32(dev, PCI_BASE_ADDRESS_0,
-		SPI_BASE_ADDRESS | PCI_BASE_ADDRESS_SPACE_MEMORY);
-
-	/* Enable Bus Master and MMIO Space */
-	pcireg = pci_read_config8(dev, PCI_COMMAND);
-	pcireg |= PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY;
-	pci_write_config8(dev, PCI_COMMAND, pcireg);
+
 
 	/* Set Strap Lock Disable */
 	ssl = read32(spibar + SPIBAR_RESET_LOCK);
diff --git a/src/soc/intel/skylake/bootblock/pch.c b/src/soc/intel/skylake/bootblock/pch.c
index 1bde802..94ed844 100644
--- a/src/soc/intel/skylake/bootblock/pch.c
+++ b/src/soc/intel/skylake/bootblock/pch.c
@@ -30,7 +30,29 @@ static void enable_spi_prefetch(void)
 	pci_write_config8(PCH_DEV_SPI, 0xdc, reg8);
 }
 
+static void enable_spibar(void)
+{
+	device_t dev = PCH_DEV_SPI;
+	u8 pcireg;
+
+	/* Assign Resources to SPI Controller */
+	/* Clear BIT 1-2 SPI Command Register */
+	pcireg = pci_read_config8(dev, PCI_COMMAND);
+	pcireg &= ~(PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY);
+	pci_write_config8(dev, PCI_COMMAND, pcireg);
+
+	/* Program Temporary BAR for SPI */
+	pci_write_config32(dev, PCI_BASE_ADDRESS_0,
+		SPI_BASE_ADDRESS | PCI_BASE_ADDRESS_SPACE_MEMORY);
+
+	/* Enable Bus Master and MMIO Space */
+	pcireg = pci_read_config8(dev, PCI_COMMAND);
+	pcireg |= PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY;
+	pci_write_config8(dev, PCI_COMMAND, pcireg);
+}
+
 static void bootblock_southbridge_init(void)
 {
+	enable_spibar();
 	enable_spi_prefetch();
 }