[coreboot-gerrit] Patch set updated for coreboot: google/lars: perform early init for CAR *stage

[Patrick Georgi (pgeorgi@google.com)]

Patrick Georgi (pgeorgi at google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13585

-gerrit

commit b4c33b3424fc2f9ab3dc3fbdf67072a3bd631d59
Author: Aaron Durbin <adurbin at chromium.org>
Date:   Mon Jan 25 17:56:43 2016 -0600

    google/lars: perform early init for CAR *stage
    
    In order to support both separate verstage and a verified boot after
    romstage one needs to ensure the proper GPIO and EC configuration
    been complete. Therefore, move that logic to
    car_mainboard_post_console_init() in car.c file which gets called
    in the early flow of a CAR stage (either verstage or romstage).
    
    BUG=chrome-os-partner:44827
    BRANCH=glados
    TEST=None
    
    Change-Id: I331f25ad4764cab972af7198f6154f604d2dbeae
    Signed-off-by: Patrick Georgi <pgeorgi at chromium.org>
    Original-Commit-Id: 2c1cb04645cbf34696e6adf48acec9d396e87ca9
    Original-Change-Id: I8d14ea16b2d07bbf04c5c33e4205a85d9f21847b
    Original-Signed-off-by: Aaron Durbin <adurbin at chromium.org>
    Original-Reviewed-on: https://chromium-review.googlesource.com/324075
    Original-Reviewed-by: Duncan Laurie <dlaurie at chromium.org>
---
 src/mainboard/google/lars/Makefile.inc |  3 +++
 src/mainboard/google/lars/car.c        | 35 ++++++++++++++++++++++++++++++++++
 src/mainboard/google/lars/romstage.c   | 16 ----------------
 3 files changed, 38 insertions(+), 16 deletions(-)

diff --git a/src/mainboard/google/lars/Makefile.inc b/src/mainboard/google/lars/Makefile.inc
index 79a2605..4bf6e0a 100644
--- a/src/mainboard/google/lars/Makefile.inc
+++ b/src/mainboard/google/lars/Makefile.inc
@@ -17,6 +17,7 @@
 subdirs-y += spd
 
 romstage-y += boardid.c
+romstage-y += car.c
 romstage-y += pei_data.c
 
 verstage-$(CONFIG_CHROMEOS) += chromeos.c
@@ -31,3 +32,5 @@ ramstage-y += pei_data.c
 ramstage-y += ramstage.c
 
 smm-$(CONFIG_HAVE_SMI_HANDLER) += smihandler.c
+
+verstage-y += car.c
diff --git a/src/mainboard/google/lars/car.c b/src/mainboard/google/lars/car.c
new file mode 100644
index 0000000..7791b92
--- /dev/null
+++ b/src/mainboard/google/lars/car.c
@@ -0,0 +1,35 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2016 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <ec/google/chromeec/ec.h>
+#include <fsp/car.h>
+#include <soc/gpio.h>
+#include "gpio.h"
+
+static void early_config_gpio(void)
+{
+	/* This is a hack for FSP because it does things in MemoryInit()
+	 * which it shouldn't be. We have to prepare certain gpios here
+	 * because of the brokenness in FSP. */
+	gpio_configure_pads(early_gpio_table, ARRAY_SIZE(early_gpio_table));
+}
+
+void car_mainboard_post_console_init(void)
+{
+	/* Ensure the EC and PD are in the right mode for recovery */
+	google_chromeec_early_init();
+
+	early_config_gpio();
+}
diff --git a/src/mainboard/google/lars/romstage.c b/src/mainboard/google/lars/romstage.c
index 1d25c7f..84c2b6f 100644
--- a/src/mainboard/google/lars/romstage.c
+++ b/src/mainboard/google/lars/romstage.c
@@ -15,10 +15,7 @@
  * GNU General Public License for more details.
  */
 
-#include <cbfs.h>
-#include <console/console.h>
 #include <string.h>
-#include <ec/google/chromeec/ec.h>
 #include <gpio.h>
 #include <soc/pei_data.h>
 #include <soc/pei_wrapper.h>
@@ -26,14 +23,6 @@
 #include "gpio.h"
 #include "spd/spd.h"
 
-static void early_config_gpio(void)
-{
-	/* This is a hack for FSP because it does things in MemoryInit()
-	 * which it shouldn't be. We have to prepare certain gpios here
-	 * because of the brokenness in FSP. */
-	gpio_configure_pads(early_gpio_table, ARRAY_SIZE(early_gpio_table));
-}
-
 void mainboard_romstage_entry(struct romstage_params *params)
 {
 	/* PCH_MEM_CFG[3:0] */
@@ -44,11 +33,6 @@ void mainboard_romstage_entry(struct romstage_params *params)
 		GPIO_MEM_CONFIG_3,
 	};
 
-	/* Ensure the EC and PD are in the right mode for recovery */
-	google_chromeec_early_init();
-
-	early_config_gpio();
-
 	params->pei_data->mem_cfg_id = gpio_base2_value(spd_gpios,
 							ARRAY_SIZE(spd_gpios));
 	/* Fill out PEI DATA */