[coreboot-gerrit] New patch to review for coreboot: chromeos: Remove CONFIG_VBNV_SIZE variable

[Patrick Georgi (pgeorgi@google.com)]

Patrick Georgi (pgeorgi at google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13598

-gerrit

commit c2d9192a2fed8227abb414829fc7e8a6a24e5151
Author: Duncan Laurie <dlaurie at chromium.org>
Date:   Thu Jan 28 10:26:31 2016 -0800

    chromeos: Remove CONFIG_VBNV_SIZE variable
    
    The VBNV region size is determined by vboot and is not really
    configurable.  Only the CMOS implementation defined this config
    variable so switch it to use VBNV_BLOCK_SIZE defined by vboot
    in vbnv_layout.h instead.
    
    This requires updating the broadwell/skylake cmos reset functions
    to use the right constant.
    
    BUG=chrome-os-partner:47915
    BRANCH=glados
    TEST=manually tested on chell
    
    Change-Id: I45e3efc2a22efcb1470bbbefbdae4eda33fc6c96
    Signed-off-by: Patrick Georgi <pgeorgi at chromium.org>
    Original-Commit-Id: e2b803ff3ac30ab22d65d1e62aca623730999a1d
    Original-Change-Id: I4896a1a5b7889d77ad00c4c8f285d184c4218e17
    Original-Signed-off-by: Duncan Laurie <dlaurie at chromium.org>
    Original-Reviewed-on: https://chromium-review.googlesource.com/324520
    Original-Reviewed-by: Aaron Durbin <adurbin at chromium.org>
---
 src/lib/coreboot_table.c                         | 3 ++-
 src/soc/intel/broadwell/lpc.c                    | 3 ++-
 src/soc/intel/skylake/pmc.c                      | 3 ++-
 src/vendorcode/google/chromeos/Kconfig           | 8 --------
 src/vendorcode/google/chromeos/acpi/chromeos.asl | 4 +++-
 src/vendorcode/google/chromeos/vbnv_cmos.c       | 4 ++--
 6 files changed, 11 insertions(+), 14 deletions(-)

diff --git a/src/lib/coreboot_table.c b/src/lib/coreboot_table.c
index 2226f5e..86f22c9 100644
--- a/src/lib/coreboot_table.c
+++ b/src/lib/coreboot_table.c
@@ -39,6 +39,7 @@
 #endif
 #include <vendorcode/google/chromeos/chromeos.h>
 #include <vendorcode/google/chromeos/gnvs.h>
+#include <vendorcode/google/chromeos/vbnv_layout.h>
 #endif
 #if CONFIG_ARCH_X86
 #include <cpu/x86/mtrr.h>
@@ -191,7 +192,7 @@ static void lb_vbnv(struct lb_header *header)
 	vbnv->tag = LB_TAG_VBNV;
 	vbnv->size = sizeof(*vbnv);
 	vbnv->range_start = CONFIG_VBNV_OFFSET + 14;
-	vbnv->range_size = CONFIG_VBNV_SIZE;
+	vbnv->range_size = VBNV_BLOCK_SIZE;
 #endif
 }
 
diff --git a/src/soc/intel/broadwell/lpc.c b/src/soc/intel/broadwell/lpc.c
index c77995d..7e57b23 100644
--- a/src/soc/intel/broadwell/lpc.c
+++ b/src/soc/intel/broadwell/lpc.c
@@ -47,6 +47,7 @@
 
 #if IS_ENABLED(CONFIG_CHROMEOS)
 #include <vendorcode/google/chromeos/chromeos.h>
+#include <vendorcode/google/chromeos/vbnv_layout.h>
 #endif
 
 static void pch_enable_ioapic(struct device *dev)
@@ -181,7 +182,7 @@ static void pch_power_options(device_t dev)
  */
 static void pch_cmos_init_preserve(int reset)
 {
-	uint8_t vbnv[CONFIG_VBNV_SIZE];
+	uint8_t vbnv[VBNV_BLOCK_SIZE];
 
 	if (reset)
 		read_vbnv(vbnv);
diff --git a/src/soc/intel/skylake/pmc.c b/src/soc/intel/skylake/pmc.c
index a2d88aa..eb7a160 100644
--- a/src/soc/intel/skylake/pmc.c
+++ b/src/soc/intel/skylake/pmc.c
@@ -37,6 +37,7 @@
 #include <soc/ramstage.h>
 #if IS_ENABLED(CONFIG_CHROMEOS)
 #include <vendorcode/google/chromeos/chromeos.h>
+#include <vendorcode/google/chromeos/vbnv_layout.h>
 #endif
 
 static const struct reg_script pch_pmc_misc_init_script[] = {
@@ -114,7 +115,7 @@ static void pch_set_acpi_mode(void)
  */
 static void pch_cmos_init_preserve(int reset)
 {
-	uint8_t vbnv[CONFIG_VBNV_SIZE];
+	uint8_t vbnv[VBNV_BLOCK_SIZE];
 	if (reset)
 		read_vbnv(vbnv);
 
diff --git a/src/vendorcode/google/chromeos/Kconfig b/src/vendorcode/google/chromeos/Kconfig
index d2a42a1..04a2fad 100644
--- a/src/vendorcode/google/chromeos/Kconfig
+++ b/src/vendorcode/google/chromeos/Kconfig
@@ -44,14 +44,6 @@ config VBNV_OFFSET
 	  CMOS offset for VbNv data. This value must match cmos.layout
 	  in the mainboard directory, minus 14 bytes for the RTC.
 
-config VBNV_SIZE
-	hex
-	default 0x10
-	depends on PC80_SYSTEM
-	help
-	  CMOS storage size for VbNv data. This value must match cmos.layout
-	  in the mainboard directory.
-
 config CHROMEOS_VBNV_CMOS
 	bool "Vboot non-volatile storage in CMOS."
 	default n
diff --git a/src/vendorcode/google/chromeos/acpi/chromeos.asl b/src/vendorcode/google/chromeos/acpi/chromeos.asl
index 5b2a26e..66ebbc1 100644
--- a/src/vendorcode/google/chromeos/acpi/chromeos.asl
+++ b/src/vendorcode/google/chromeos/acpi/chromeos.asl
@@ -13,6 +13,8 @@
  * GNU General Public License for more details.
  */
 
+#include <vendorcode/google/chromeos/vbnv_layout.h>
+
 Device (CRHW)
 {
 	Name(_HID, EISAID("GGL0001"))
@@ -70,7 +72,7 @@ Device (CRHW)
 			// See src/vendorcode/google/chromeos/Kconfig
 			// for the definition of these:
 			CONFIG_VBNV_OFFSET,
-			CONFIG_VBNV_SIZE
+			VBNV_BLOCK_SIZE
 		})
 		Return(VNBV)
 	}
diff --git a/src/vendorcode/google/chromeos/vbnv_cmos.c b/src/vendorcode/google/chromeos/vbnv_cmos.c
index ddcb765..e0d7ba1 100644
--- a/src/vendorcode/google/chromeos/vbnv_cmos.c
+++ b/src/vendorcode/google/chromeos/vbnv_cmos.c
@@ -22,7 +22,7 @@ void read_vbnv_cmos(uint8_t *vbnv_copy)
 {
 	int i;
 
-	for (i = 0; i < CONFIG_VBNV_SIZE; i++)
+	for (i = 0; i < VBNV_BLOCK_SIZE; i++)
 		vbnv_copy[i] = cmos_read(CONFIG_VBNV_OFFSET + 14 + i);
 }
 
@@ -30,6 +30,6 @@ void save_vbnv_cmos(const uint8_t *vbnv_copy)
 {
 	int i;
 
-	for (i = 0; i < CONFIG_VBNV_SIZE; i++)
+	for (i = 0; i < VBNV_BLOCK_SIZE; i++)
 		cmos_write(vbnv_copy[i], CONFIG_VBNV_OFFSET + 14 + i);
 }