[coreboot-gerrit] New patch to review for coreboot: soc/intel/quark: Report CPU info
Leroy P Leahy (leroy.p.leahy@intel.com)
gerrit at coreboot.org
Thu Feb 4 17:37:20 CET 2016
Leroy P Leahy (leroy.p.leahy at intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13605
-gerrit
commit 985916722fcc09add9bf5a1e1a8264cbe467e598
Author: Lee Leahy <leroy.p.leahy at intel.com>
Date: Tue Feb 2 19:14:12 2016 -0800
soc/intel/quark: Report CPU info
Decode the CPU variants and display the CPU info.
Testing:
* Successful if Quark X1000 is displayed
TEST=Build and run on Galileo
Change-Id: I7234a6d81a48cdd02708b80663147e2b09ba979e
Signed-off-by: Lee Leahy <leroy.p.leahy at intel.com>
---
src/soc/intel/quark/include/soc/cpu.h | 25 +++++
src/soc/intel/quark/include/soc/romstage.h | 1 +
src/soc/intel/quark/romstage/Makefile.inc | 1 +
src/soc/intel/quark/romstage/report_platform.c | 129 +++++++++++++++++++++++++
src/soc/intel/quark/romstage/romstage.c | 5 +
5 files changed, 161 insertions(+)
diff --git a/src/soc/intel/quark/include/soc/cpu.h b/src/soc/intel/quark/include/soc/cpu.h
new file mode 100644
index 0000000..25ba599
--- /dev/null
+++ b/src/soc/intel/quark/include/soc/cpu.h
@@ -0,0 +1,25 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2015-2016 Intel Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef _QUARK_CPU_H_
+#define _BROADWELL_CPU_H_
+
+#include <arch/cpu.h>
+#include <device/device.h>
+
+/* Supported CPUIDs */
+#define CPUID_QUARK_X1000 0X590
+
+#endif /* _QUARK_CPU_H_ */
diff --git a/src/soc/intel/quark/include/soc/romstage.h b/src/soc/intel/quark/include/soc/romstage.h
index 3a1320c..23c6270 100644
--- a/src/soc/intel/quark/include/soc/romstage.h
+++ b/src/soc/intel/quark/include/soc/romstage.h
@@ -30,6 +30,7 @@ void mcr_write(uint8_t opcode, uint8_t port, uint32_t reg_address);
uint32_t mdr_read(void);
void mdr_write(uint32_t value);
void mea_write(uint32_t reg_address);
+void report_platform_info(void);
int set_base_address_and_enable_uart(u8 bus, u8 dev, u8 func, u32 mmio_base);
#endif /* _QUARK_ROMSTAGE_H_ */
diff --git a/src/soc/intel/quark/romstage/Makefile.inc b/src/soc/intel/quark/romstage/Makefile.inc
index 46f4c72..d14cc84 100644
--- a/src/soc/intel/quark/romstage/Makefile.inc
+++ b/src/soc/intel/quark/romstage/Makefile.inc
@@ -16,6 +16,7 @@
cpu_incs-y += $(src)/soc/intel/quark/romstage/esram_init.inc
cpu_incs-y += $(src)/soc/intel/quark/romstage/cache_as_ram.inc
+romstage-y += report_platform.c
romstage-y += romstage.c
romstage-$(CONFIG_ENABLE_BUILTIN_HSUART1) += uart.c
diff --git a/src/soc/intel/quark/romstage/report_platform.c b/src/soc/intel/quark/romstage/report_platform.c
new file mode 100644
index 0000000..c93ac4b
--- /dev/null
+++ b/src/soc/intel/quark/romstage/report_platform.c
@@ -0,0 +1,129 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2014 Google Inc.
+ * Copyright (C) 2015-2016 Intel Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <arch/cpu.h>
+#include <console/console.h>
+#include <device/pci.h>
+#include <device/pci_def.h>
+#include <soc/cpu.h>
+#include <soc/pci_devs.h>
+#include <soc/romstage.h>
+
+static const struct {
+ u32 cpuid;
+ u32 extended_temp;
+ u32 ecc;
+ u32 secure_boot;
+ u32 d_variant;
+ u32 mm_number;
+ const char *name;
+} cpu_table[] = {
+ { CPUID_QUARK_X1000, 0, 0, 0, 0, 930237, "Quark X1000" },
+ { CPUID_QUARK_X1000, 0, 1, 0, 0, 930239, "Quark X1010" },
+ { CPUID_QUARK_X1000, 0, 1, 1, 0, 934775, "Quark X1020" },
+ { CPUID_QUARK_X1000, 0, 1, 1, 1, 930236, "Quark X1020D" },
+ { CPUID_QUARK_X1000, 1, 0, 0, 0, 934413, "Quark X1001" },
+ { CPUID_QUARK_X1000, 1, 1, 0, 0, 934415, "Quark X1011" },
+ { CPUID_QUARK_X1000, 1, 1, 1, 0, 934943, "Quark X1021" },
+ { CPUID_QUARK_X1000, 1, 1, 1, 1, 934411, "Quark X1021D" },
+};
+
+static struct {
+ u8 revision_id;
+ const char *stepping;
+} stepping_table[] = {
+ { 0, "A0" },
+};
+
+static uint32_t memory_cntrl_read(uint32_t offset)
+{
+ /* Read the memory controller register */
+ mea_write(offset);
+ mcr_write(QUARK_OPCODE_READ, QUARK_NC_MEMORY_CONTROLLER_SB_PORT_ID,
+ offset);
+ return mdr_read();
+}
+
+static uint32_t fuse_port_read(uint32_t offset)
+{
+ /* Read the SoC unit register */
+ mea_write(offset);
+ mcr_write(QUARK_ALT_OPCODE_READ, QUARK_SCSS_FUSE_SB_PORT_ID, offset);
+ return mdr_read();
+}
+
+static void report_cpu_info(void)
+{
+ struct cpuid_result cpuidr;
+ const char *cpu_type = "Unknown";
+ u32 d_variant;
+ u32 ecc_enabled;
+ u32 extended_temp;
+ u32 i;
+ u8 revision;
+ u32 secure_boot;
+ const char *stepping = "Unknown";
+
+ /* Determine if ECC is enabled */
+printk(BIOS_DEBUG, "Calling memory_cntrl_read\n");
+ ecc_enabled = (0 == (B_DFUSESTAT_ECC_DIS
+ & memory_cntrl_read(QUARK_NC_MEMORY_CONTROLLER_REG_DFUSESTAT)));
+
+printk(BIOS_DEBUG, "Calling soc_read\n");
+ /* Determine if secure boot is enabled */
+ secure_boot = (0 != (fuse_port_read(QUARK_SCSS_SOC_UNIT_SPI_ROM_FUSE)
+ & B_ROM_FUSE_IN_SECURE_SKU));
+
+ /* TODO: Determine if this is a D variant */
+ if (ecc_enabled && secure_boot)
+ d_variant = 0; /* or 1 */
+
+ /* TODO: Determine the temperature variant */
+ extended_temp = 0;
+
+ /* Look for string to match the CPU ID value */
+ cpuidr = cpuid(1);
+ for (i = 0; i < ARRAY_SIZE(cpu_table); i++) {
+ if ((cpu_table[i].cpuid == cpuidr.eax)
+ && (cpu_table[i].extended_temp == extended_temp)
+ && (cpu_table[i].ecc == ecc_enabled)
+ && (cpu_table[i].secure_boot == secure_boot)
+ && (cpu_table[i].d_variant == d_variant)) {
+ cpu_type = cpu_table[i].name;
+ break;
+ }
+ }
+
+ /*
+ * Translate the host bridge revision ID into the stepping
+ * Developer's Manual Section C.2
+ */
+ revision = pci_read_config8(MC_BDF, PCI_REVISION_ID);
+ for (i = 0; i < ARRAY_SIZE(stepping_table); i++) {
+ if (stepping_table[i].revision_id == revision) {
+ stepping = stepping_table[i].stepping;
+ break;
+ }
+ }
+
+ printk(BIOS_DEBUG, "CPU: ID %x:%x, %s %s Stepping\n", cpuidr.eax,
+ revision, cpu_type, stepping);
+}
+
+void report_platform_info(void)
+{
+ report_cpu_info();
+}
diff --git a/src/soc/intel/quark/romstage/romstage.c b/src/soc/intel/quark/romstage/romstage.c
index 0aafcd9..8b513d6 100644
--- a/src/soc/intel/quark/romstage/romstage.c
+++ b/src/soc/intel/quark/romstage/romstage.c
@@ -27,6 +27,11 @@
static struct chipset_power_state power_state CAR_GLOBAL;
+void car_soc_post_console_init(void)
+{
+ report_platform_info();
+};
+
struct chipset_power_state *fill_power_state(void)
{
struct chipset_power_state *ps = car_get_var_ptr(&power_state);
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