[coreboot-gerrit] Patch set updated for coreboot: southbridge/intel/lynxpoint: Use common gpio.c
Patrick Rudolph (siro@das-labor.org)
gerrit at coreboot.org
Sun Feb 7 11:34:36 CET 2016
Patrick Rudolph (siro at das-labor.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13615
-gerrit
commit 83141f058306e491e62c5a1397c8ad70e1489859
Author: Patrick Rudolph <siro at das-labor.org>
Date: Sat Feb 6 18:07:59 2016 +0100
southbridge/intel/lynxpoint: Use common gpio.c
Use shared gpio code from common folder.
I haven't found any good solution for
CONFIG_INTEL_LYNXPOINT_LP check in Makefile.in.
Needs test on real hardware !
Change-Id: Iccc6d254bafb927b6470704cec7c9dd7528e2c68
Signed-off-by: Patrick Rudolph <siro at das-labor.org>
---
src/mainboard/google/bolt/chromeos.c | 1 +
src/mainboard/google/falco/chromeos.c | 1 +
src/mainboard/google/falco/smihandler.c | 1 +
src/mainboard/google/panther/chromeos.c | 1 +
src/mainboard/google/peppy/chromeos.c | 1 +
src/mainboard/google/peppy/smihandler.c | 1 +
src/mainboard/google/slippy/chromeos.c | 1 +
src/mainboard/intel/baskingridge/chromeos.c | 24 +---
src/mainboard/intel/baskingridge/gpio.h | 2 +-
src/southbridge/intel/common/Makefile.inc | 2 +
src/southbridge/intel/lynxpoint/Kconfig | 1 +
src/southbridge/intel/lynxpoint/Makefile.inc | 4 -
src/southbridge/intel/lynxpoint/early_pch.c | 2 +-
src/southbridge/intel/lynxpoint/gpio.c | 145 -----------------------
src/southbridge/intel/lynxpoint/gpio.h | 165 ---------------------------
src/southbridge/intel/lynxpoint/lp_gpio.h | 11 ++
src/southbridge/intel/lynxpoint/pch.h | 15 ---
src/southbridge/intel/lynxpoint/pcie.c | 1 +
18 files changed, 27 insertions(+), 352 deletions(-)
diff --git a/src/mainboard/google/bolt/chromeos.c b/src/mainboard/google/bolt/chromeos.c
index 2f393e0..ff0a1f7 100644
--- a/src/mainboard/google/bolt/chromeos.c
+++ b/src/mainboard/google/bolt/chromeos.c
@@ -19,6 +19,7 @@
#include <device/device.h>
#include <device/pci.h>
#include <southbridge/intel/lynxpoint/pch.h>
+#include <southbridge/intel/common/gpio.h>
#if CONFIG_EC_GOOGLE_CHROMEEC
#include "ec.h"
diff --git a/src/mainboard/google/falco/chromeos.c b/src/mainboard/google/falco/chromeos.c
index a7d96a8..f0e6a5a 100644
--- a/src/mainboard/google/falco/chromeos.c
+++ b/src/mainboard/google/falco/chromeos.c
@@ -19,6 +19,7 @@
#include <device/device.h>
#include <device/pci.h>
#include <southbridge/intel/lynxpoint/pch.h>
+#include <southbridge/intel/common/gpio.h>
#if CONFIG_EC_GOOGLE_CHROMEEC
#include "ec.h"
diff --git a/src/mainboard/google/falco/smihandler.c b/src/mainboard/google/falco/smihandler.c
index c1b3fcf..6f17e40 100644
--- a/src/mainboard/google/falco/smihandler.c
+++ b/src/mainboard/google/falco/smihandler.c
@@ -19,6 +19,7 @@
#include <cpu/x86/smm.h>
#include <southbridge/intel/lynxpoint/nvs.h>
#include <southbridge/intel/lynxpoint/pch.h>
+#include <southbridge/intel/common/gpio.h>
#include <southbridge/intel/lynxpoint/me.h>
#include <northbridge/intel/haswell/haswell.h>
#include <cpu/intel/haswell/haswell.h>
diff --git a/src/mainboard/google/panther/chromeos.c b/src/mainboard/google/panther/chromeos.c
index 2c5c234..17917b1 100644
--- a/src/mainboard/google/panther/chromeos.c
+++ b/src/mainboard/google/panther/chromeos.c
@@ -19,6 +19,7 @@
#include <device/device.h>
#include <device/pci.h>
#include <southbridge/intel/lynxpoint/pch.h>
+#include <southbridge/intel/common/gpio.h>
#include <vendorcode/google/chromeos/chromeos.h>
#define GPIO_SPI_WP 58
diff --git a/src/mainboard/google/peppy/chromeos.c b/src/mainboard/google/peppy/chromeos.c
index a7d96a8..f0e6a5a 100644
--- a/src/mainboard/google/peppy/chromeos.c
+++ b/src/mainboard/google/peppy/chromeos.c
@@ -19,6 +19,7 @@
#include <device/device.h>
#include <device/pci.h>
#include <southbridge/intel/lynxpoint/pch.h>
+#include <southbridge/intel/common/gpio.h>
#if CONFIG_EC_GOOGLE_CHROMEEC
#include "ec.h"
diff --git a/src/mainboard/google/peppy/smihandler.c b/src/mainboard/google/peppy/smihandler.c
index 9e7657a..8f265a0 100644
--- a/src/mainboard/google/peppy/smihandler.c
+++ b/src/mainboard/google/peppy/smihandler.c
@@ -19,6 +19,7 @@
#include <cpu/x86/smm.h>
#include <southbridge/intel/lynxpoint/nvs.h>
#include <southbridge/intel/lynxpoint/pch.h>
+#include <southbridge/intel/common/gpio.h>
#include <southbridge/intel/lynxpoint/me.h>
#include <northbridge/intel/haswell/haswell.h>
#include <cpu/intel/haswell/haswell.h>
diff --git a/src/mainboard/google/slippy/chromeos.c b/src/mainboard/google/slippy/chromeos.c
index a7d96a8..f0e6a5a 100644
--- a/src/mainboard/google/slippy/chromeos.c
+++ b/src/mainboard/google/slippy/chromeos.c
@@ -19,6 +19,7 @@
#include <device/device.h>
#include <device/pci.h>
#include <southbridge/intel/lynxpoint/pch.h>
+#include <southbridge/intel/common/gpio.h>
#if CONFIG_EC_GOOGLE_CHROMEEC
#include "ec.h"
diff --git a/src/mainboard/intel/baskingridge/chromeos.c b/src/mainboard/intel/baskingridge/chromeos.c
index 3885257..94e8d89 100644
--- a/src/mainboard/intel/baskingridge/chromeos.c
+++ b/src/mainboard/intel/baskingridge/chromeos.c
@@ -19,7 +19,7 @@
#include <device/device.h>
#include <device/pci.h>
#include <southbridge/intel/lynxpoint/pch.h>
-#include <southbridge/intel/lynxpoint/gpio.h>
+#include <southbridge/intel/common/gpio.h>
#ifndef __PRE_RAM__
#include <boot/coreboot_tables.h>
@@ -82,38 +82,20 @@ void fill_lb_gpios(struct lb_gpios *gpios)
int get_developer_mode_switch(void)
{
- device_t dev;
-#ifdef __PRE_RAM__
- dev = PCI_DEV(0, 0x1f, 0);
-#else
- dev = dev_find_slot(0, PCI_DEVFN(0x1f,0));
-#endif
- u16 gpio_base = pci_read_config32(dev, GPIOBASE) & 0xfffe;
- u32 gp_lvl2 = inl(gpio_base + GP_LVL2);
-
/*
* Developer: GPIO48, Connected to J8E4, however the silkscreen says
* J8E3. The jumper is active low.
*/
- return !((gp_lvl2 >> (48-32)) & 1);
+ return !get_gpio(48);
}
int get_recovery_mode_switch(void)
{
- device_t dev;
-#ifdef __PRE_RAM__
- dev = PCI_DEV(0, 0x1f, 0);
-#else
- dev = dev_find_slot(0, PCI_DEVFN(0x1f,0));
-#endif
- u16 gpio_base = pci_read_config32(dev, GPIOBASE) & 0xfffe;
- u32 gp_lvl3 = inl(gpio_base + GP_LVL3);
-
/*
* Recovery: GPIO69, Connected to J8E3, however the silkscreen says
* J8E2. The jump is active high.
*/
- return (gp_lvl3 >> (69-64)) & 1;
+ return get_gpio(69);
}
int get_write_protect_state(void)
diff --git a/src/mainboard/intel/baskingridge/gpio.h b/src/mainboard/intel/baskingridge/gpio.h
index 99bec38..f2be9e3 100644
--- a/src/mainboard/intel/baskingridge/gpio.h
+++ b/src/mainboard/intel/baskingridge/gpio.h
@@ -16,7 +16,7 @@
#ifndef BASKING_RIDGE_GPIO_H
#define BASKING_RIDGE_GPIO_H
-#include "southbridge/intel/lynxpoint/gpio.h"
+#include <southbridge/intel/common/gpio.h>
const struct pch_gpio_set1 pch_gpio_set1_mode = {
.gpio0 = GPIO_MODE_GPIO, /* PCH_GPIO0_R -> S_GPIO -> J9F4 */
diff --git a/src/southbridge/intel/common/Makefile.inc b/src/southbridge/intel/common/Makefile.inc
index 123e96e..94c291b 100644
--- a/src/southbridge/intel/common/Makefile.inc
+++ b/src/southbridge/intel/common/Makefile.inc
@@ -21,9 +21,11 @@ ifeq ($(CONFIG_SOUTHBRIDGE_INTEL_COMMON),y)
romstage-$(CONFIG_USBDEBUG_IN_ROMSTAGE) += usb_debug.c
ramstage-$(CONFIG_USBDEBUG) += usb_debug.c
+ifeq ($(CONFIG_INTEL_LYNXPOINT_LP),n)
ifeq ($(CONFIG_SOUTHBRIDGE_INTEL_COMMON_GPIO),y)
romstage-y += gpio.c
ramstage-y += gpio.c
smm-$(CONFIG_HAVE_SMI_HANDLER) += gpio.c
endif
endif
+endif
diff --git a/src/southbridge/intel/lynxpoint/Kconfig b/src/southbridge/intel/lynxpoint/Kconfig
index 01556a4..5de537c 100644
--- a/src/southbridge/intel/lynxpoint/Kconfig
+++ b/src/southbridge/intel/lynxpoint/Kconfig
@@ -30,6 +30,7 @@ config SOUTH_BRIDGE_OPTIONS # dummy
select SPI_FLASH
select HAVE_INTEL_FIRMWARE
select HAVE_SPI_CONSOLE_SUPPORT
+ select SOUTHBRIDGE_INTEL_COMMON_GPIO
config INTEL_LYNXPOINT_LP
bool
diff --git a/src/southbridge/intel/lynxpoint/Makefile.inc b/src/southbridge/intel/lynxpoint/Makefile.inc
index 203aeb5..e36b1b2 100644
--- a/src/southbridge/intel/lynxpoint/Makefile.inc
+++ b/src/southbridge/intel/lynxpoint/Makefile.inc
@@ -51,10 +51,6 @@ ifeq ($(CONFIG_INTEL_LYNXPOINT_LP),y)
romstage-y += lp_gpio.c
ramstage-y += lp_gpio.c
smm-$(CONFIG_HAVE_SMI_HANDLER) += lp_gpio.c
-else
-romstage-y += gpio.c
-ramstage-y += gpio.c
-smm-$(CONFIG_HAVE_SMI_HANDLER) += gpio.c
endif
endif
diff --git a/src/southbridge/intel/lynxpoint/early_pch.c b/src/southbridge/intel/lynxpoint/early_pch.c
index 9802284..0e4fa3d 100644
--- a/src/southbridge/intel/lynxpoint/early_pch.c
+++ b/src/southbridge/intel/lynxpoint/early_pch.c
@@ -27,7 +27,7 @@
#if CONFIG_INTEL_LYNXPOINT_LP
#include "lp_gpio.h"
#else
-#include "gpio.h"
+#include "southbridge/intel/common/gpio.h"
#endif
const struct rcba_config_instruction pch_early_config[] = {
diff --git a/src/southbridge/intel/lynxpoint/gpio.c b/src/southbridge/intel/lynxpoint/gpio.c
deleted file mode 100644
index bcf3b76..0000000
--- a/src/southbridge/intel/lynxpoint/gpio.c
+++ /dev/null
@@ -1,145 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2011 The Chromium OS Authors. All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <stdint.h>
-#include <string.h>
-#include <arch/io.h>
-#include <device/device.h>
-#include <device/pci.h>
-#include "pch.h"
-#include "gpio.h"
-
-#define MAX_GPIO_NUMBER 75 /* zero based */
-
-static u16 get_gpio_base(void)
-{
-#if defined(__PRE_RAM__) || defined(__SMM__)
- return pci_read_config16(PCH_LPC_DEV, GPIO_BASE) & 0xfffc;
-#else
- return pci_read_config16(dev_find_slot(0, PCI_DEVFN(0x1f, 0)),
- GPIO_BASE) & 0xfffc;
-#endif
-}
-
-void setup_pch_gpios(const struct pch_gpio_map *gpio)
-{
- u16 gpiobase = get_gpio_base();
-
- /* GPIO Set 1 */
- if (gpio->set1.level)
- outl(*((u32*)gpio->set1.level), gpiobase + GP_LVL);
- if (gpio->set1.mode)
- outl(*((u32*)gpio->set1.mode), gpiobase + GPIO_USE_SEL);
- if (gpio->set1.direction)
- outl(*((u32*)gpio->set1.direction), gpiobase + GP_IO_SEL);
- if (gpio->set1.reset)
- outl(*((u32*)gpio->set1.reset), gpiobase + GP_RST_SEL1);
- if (gpio->set1.invert)
- outl(*((u32*)gpio->set1.invert), gpiobase + GPI_INV);
- if (gpio->set1.blink)
- outl(*((u32*)gpio->set1.blink), gpiobase + GPO_BLINK);
-
- /* GPIO Set 2 */
- if (gpio->set2.level)
- outl(*((u32*)gpio->set2.level), gpiobase + GP_LVL2);
- if (gpio->set2.mode)
- outl(*((u32*)gpio->set2.mode), gpiobase + GPIO_USE_SEL2);
- if (gpio->set2.direction)
- outl(*((u32*)gpio->set2.direction), gpiobase + GP_IO_SEL2);
- if (gpio->set2.reset)
- outl(*((u32*)gpio->set2.reset), gpiobase + GP_RST_SEL2);
-
- /* GPIO Set 3 */
- if (gpio->set3.level)
- outl(*((u32*)gpio->set3.level), gpiobase + GP_LVL3);
- if (gpio->set3.mode)
- outl(*((u32*)gpio->set3.mode), gpiobase + GPIO_USE_SEL3);
- if (gpio->set3.direction)
- outl(*((u32*)gpio->set3.direction), gpiobase + GP_IO_SEL3);
- if (gpio->set3.reset)
- outl(*((u32*)gpio->set3.reset), gpiobase + GP_RST_SEL3);
-}
-
-int get_gpio(int gpio_num)
-{
- static const int gpio_reg_offsets[] = {0xc, 0x38, 0x48};
- u16 gpio_base = get_gpio_base();
- int index, bit;
-
- if (gpio_num > MAX_GPIO_NUMBER)
- return 0; /* Just ignore wrong gpio numbers. */
-
- index = gpio_num / 32;
- bit = gpio_num % 32;
-
- return (inl(gpio_base + gpio_reg_offsets[index]) >> bit) & 1;
-}
-
-/*
- * get a number comprised of multiple GPIO values. gpio_num_array points to
- * the array of gpio pin numbers to scan, terminated by -1.
- */
-unsigned get_gpios(const int *gpio_num_array)
-{
- int gpio;
- unsigned bitmask = 1;
- unsigned vector = 0;
-
- while (bitmask &&
- ((gpio = *gpio_num_array++) != -1)) {
- if (get_gpio(gpio))
- vector |= bitmask;
- bitmask <<= 1;
- }
- return vector;
-}
-
-void set_gpio(int gpio_num, int value)
-{
- static const int gpio_reg_offsets[] = {0xc, 0x38, 0x48};
- u16 gpio_base = get_gpio_base();
- int index, bit;
- u32 config;
-
- if (gpio_num > MAX_GPIO_NUMBER)
- return; /* Just ignore wrong gpio numbers. */
-
- index = gpio_num / 32;
- bit = gpio_num % 32;
-
- config = inl(gpio_base + gpio_reg_offsets[index]);
- config &= ~(1 << bit);
- config |= value << bit;
- outl(config, gpio_base + gpio_reg_offsets[index]);
-}
-
-int gpio_is_native(int gpio_num)
-{
- static const int gpio_reg_offsets[] = {
- GPIO_USE_SEL, GPIO_USE_SEL2, GPIO_USE_SEL3
- };
- u16 gpio_base = get_gpio_base();
- int index, bit;
- u32 config;
-
- if (gpio_num > MAX_GPIO_NUMBER)
- return 0; /* Just ignore wrong gpio numbers. */
-
- index = gpio_num / 32;
- bit = gpio_num % 32;
-
- config = inl(gpio_base + gpio_reg_offsets[index]);
- return !(config & (1 << bit));
-}
diff --git a/src/southbridge/intel/lynxpoint/gpio.h b/src/southbridge/intel/lynxpoint/gpio.h
deleted file mode 100644
index 5f62a65..0000000
--- a/src/southbridge/intel/lynxpoint/gpio.h
+++ /dev/null
@@ -1,165 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2011 The Chromium OS Authors. All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#ifndef INTEL_LYNXPOINT_GPIO_H
-#define INTEL_LYNXPOINT_GPIO_H
-
-/* ICH7 GPIOBASE */
-#define GPIO_USE_SEL 0x00
-#define GP_IO_SEL 0x04
-#define GP_LVL 0x0c
-#define GPO_BLINK 0x18
-#define GPI_INV 0x2c
-#define GPIO_USE_SEL2 0x30
-#define GP_IO_SEL2 0x34
-#define GP_LVL2 0x38
-#define GPIO_USE_SEL3 0x40
-#define GP_IO_SEL3 0x44
-#define GP_LVL3 0x48
-#define GP_RST_SEL1 0x60
-#define GP_RST_SEL2 0x64
-#define GP_RST_SEL3 0x68
-
-#define GPIO_MODE_NATIVE 0
-#define GPIO_MODE_GPIO 1
-#define GPIO_MODE_NONE 1
-
-#define GPIO_DIR_OUTPUT 0
-#define GPIO_DIR_INPUT 1
-
-#define GPIO_NO_INVERT 0
-#define GPIO_INVERT 1
-
-#define GPIO_LEVEL_LOW 0
-#define GPIO_LEVEL_HIGH 1
-
-#define GPIO_NO_BLINK 0
-#define GPIO_BLINK 1
-
-#define GPIO_RESET_PWROK 0
-#define GPIO_RESET_RSMRST 1
-
-struct pch_gpio_set1 {
- u32 gpio0 : 1;
- u32 gpio1 : 1;
- u32 gpio2 : 1;
- u32 gpio3 : 1;
- u32 gpio4 : 1;
- u32 gpio5 : 1;
- u32 gpio6 : 1;
- u32 gpio7 : 1;
- u32 gpio8 : 1;
- u32 gpio9 : 1;
- u32 gpio10 : 1;
- u32 gpio11 : 1;
- u32 gpio12 : 1;
- u32 gpio13 : 1;
- u32 gpio14 : 1;
- u32 gpio15 : 1;
- u32 gpio16 : 1;
- u32 gpio17 : 1;
- u32 gpio18 : 1;
- u32 gpio19 : 1;
- u32 gpio20 : 1;
- u32 gpio21 : 1;
- u32 gpio22 : 1;
- u32 gpio23 : 1;
- u32 gpio24 : 1;
- u32 gpio25 : 1;
- u32 gpio26 : 1;
- u32 gpio27 : 1;
- u32 gpio28 : 1;
- u32 gpio29 : 1;
- u32 gpio30 : 1;
- u32 gpio31 : 1;
-} __attribute__ ((packed));
-
-struct pch_gpio_set2 {
- u32 gpio32 : 1;
- u32 gpio33 : 1;
- u32 gpio34 : 1;
- u32 gpio35 : 1;
- u32 gpio36 : 1;
- u32 gpio37 : 1;
- u32 gpio38 : 1;
- u32 gpio39 : 1;
- u32 gpio40 : 1;
- u32 gpio41 : 1;
- u32 gpio42 : 1;
- u32 gpio43 : 1;
- u32 gpio44 : 1;
- u32 gpio45 : 1;
- u32 gpio46 : 1;
- u32 gpio47 : 1;
- u32 gpio48 : 1;
- u32 gpio49 : 1;
- u32 gpio50 : 1;
- u32 gpio51 : 1;
- u32 gpio52 : 1;
- u32 gpio53 : 1;
- u32 gpio54 : 1;
- u32 gpio55 : 1;
- u32 gpio56 : 1;
- u32 gpio57 : 1;
- u32 gpio58 : 1;
- u32 gpio59 : 1;
- u32 gpio60 : 1;
- u32 gpio61 : 1;
- u32 gpio62 : 1;
- u32 gpio63 : 1;
-} __attribute__ ((packed));
-
-struct pch_gpio_set3 {
- u32 gpio64 : 1;
- u32 gpio65 : 1;
- u32 gpio66 : 1;
- u32 gpio67 : 1;
- u32 gpio68 : 1;
- u32 gpio69 : 1;
- u32 gpio70 : 1;
- u32 gpio71 : 1;
- u32 gpio72 : 1;
- u32 gpio73 : 1;
- u32 gpio74 : 1;
- u32 gpio75 : 1;
-} __attribute__ ((packed));
-
-struct pch_gpio_map {
- struct {
- const struct pch_gpio_set1 *mode;
- const struct pch_gpio_set1 *direction;
- const struct pch_gpio_set1 *level;
- const struct pch_gpio_set1 *reset;
- const struct pch_gpio_set1 *invert;
- const struct pch_gpio_set1 *blink;
- } set1;
- struct {
- const struct pch_gpio_set2 *mode;
- const struct pch_gpio_set2 *direction;
- const struct pch_gpio_set2 *level;
- const struct pch_gpio_set2 *reset;
- } set2;
- struct {
- const struct pch_gpio_set3 *mode;
- const struct pch_gpio_set3 *direction;
- const struct pch_gpio_set3 *level;
- const struct pch_gpio_set3 *reset;
- } set3;
-};
-
-/* Configure GPIOs with mainboard provided settings */
-void setup_pch_gpios(const struct pch_gpio_map *gpio);
-
-#endif
diff --git a/src/southbridge/intel/lynxpoint/lp_gpio.h b/src/southbridge/intel/lynxpoint/lp_gpio.h
index 4db6113..c35e770 100644
--- a/src/southbridge/intel/lynxpoint/lp_gpio.h
+++ b/src/southbridge/intel/lynxpoint/lp_gpio.h
@@ -163,4 +163,15 @@ struct pch_lp_gpio_map {
/* Configure GPIOs with mainboard provided settings */
void setup_pch_lp_gpios(const struct pch_lp_gpio_map map[]);
+/* get GPIO pin value */
+int get_gpio(int gpio_num);
+/*
+ * get a number comprised of multiple GPIO values. gpio_num_array points to
+ * the array of gpio pin numbers to scan, terminated by -1.
+ */
+unsigned get_gpios(const int *gpio_num_array);
+
+void set_gpio(int gpio_num, int value);
+
+int gpio_is_native(int gpio_num);
#endif
diff --git a/src/southbridge/intel/lynxpoint/pch.h b/src/southbridge/intel/lynxpoint/pch.h
index 46c3f63..2b834ff 100644
--- a/src/southbridge/intel/lynxpoint/pch.h
+++ b/src/southbridge/intel/lynxpoint/pch.h
@@ -167,21 +167,6 @@ void enable_all_gpe(u32 set1, u32 set2, u32 set3, u32 set4);
void disable_all_gpe(void);
void enable_gpe(u32 mask);
void disable_gpe(u32 mask);
-/*
- * get GPIO pin value
- */
-int get_gpio(int gpio_num);
-/*
- * Get a number comprised of multiple GPIO values. gpio_num_array points to
- * the array of gpio pin numbers to scan, terminated by -1.
- */
-unsigned get_gpios(const int *gpio_num_array);
-/*
- * Set GPIO pin value.
- */
-void set_gpio(int gpio_num, int value);
-/* Return non-zero if gpio is set to native function. 0 otherwise. */
-int gpio_is_native(int gpio_num);
#if !defined(__PRE_RAM__) && !defined(__SMM__)
#include <device/device.h>
diff --git a/src/southbridge/intel/lynxpoint/pcie.c b/src/southbridge/intel/lynxpoint/pcie.c
index 41e8890..17858af 100644
--- a/src/southbridge/intel/lynxpoint/pcie.c
+++ b/src/southbridge/intel/lynxpoint/pcie.c
@@ -20,6 +20,7 @@
#include <device/pciexp.h>
#include <device/pci_ids.h>
#include "pch.h"
+#include <southbridge/intel/common/gpio.h>
static void pcie_update_cfg8(device_t dev, int reg, u8 mask, u8 or);
static void pcie_update_cfg(device_t dev, int reg, u32 mask, u32 or);
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