[coreboot-gerrit] Patch set updated for coreboot: lumpy: Support native raminit
Vladimir Serbinenko (phcoder@gmail.com)
gerrit at coreboot.org
Wed Feb 10 04:09:38 CET 2016
Vladimir Serbinenko (phcoder at gmail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13663
-gerrit
commit 875f0d09f363eb09cadda87099b241701abe52d4
Author: Vladimir Serbinenko <phcoder at gmail.com>
Date: Wed Feb 10 03:01:37 2016 +0100
lumpy: Support native raminit
Change-Id: Id695fb6e759b90cd91bb9760bb4fe2a459480b21
Signed-off-by: Vladimir Serbinenko <phcoder at gmail.com>
---
src/mainboard/samsung/lumpy/Kconfig | 9 ++-
src/mainboard/samsung/lumpy/devicetree.cb | 2 +
src/mainboard/samsung/lumpy/romstage.c | 128 +++++++++++++++++++-----------
3 files changed, 88 insertions(+), 51 deletions(-)
diff --git a/src/mainboard/samsung/lumpy/Kconfig b/src/mainboard/samsung/lumpy/Kconfig
index d0f3844..592207e 100644
--- a/src/mainboard/samsung/lumpy/Kconfig
+++ b/src/mainboard/samsung/lumpy/Kconfig
@@ -19,11 +19,12 @@ config BOARD_SPECIFIC_OPTIONS # dummy
select SUPERIO_SMSC_LPC47N207
select DRIVERS_GENERIC_IOAPIC
select INTEL_INT15
- select HAVE_MRC
-config USE_NATIVE_RAMINIT
- bool
- default n
+if !USE_NATIVE_RAMINIT
+config BOARD_SPECIFIC_OPTIONS_MRC # dummy
+ def_bool y
+ select HAVE_MRC
+endif
config CHROMEOS
select CHROMEOS_VBNV_CMOS
diff --git a/src/mainboard/samsung/lumpy/devicetree.cb b/src/mainboard/samsung/lumpy/devicetree.cb
index 6bf571a..f73e603 100644
--- a/src/mainboard/samsung/lumpy/devicetree.cb
+++ b/src/mainboard/samsung/lumpy/devicetree.cb
@@ -14,6 +14,8 @@ chip northbridge/intel/sandybridge
register "gpu_panel_power_backlight_on_delay" = "2100" # T5: 210ms
register "gpu_panel_power_backlight_off_delay" = "2100" # TD: 210ms
+ register "max_mem_clock_mhz" = "666"
+
device cpu_cluster 0 on
chip cpu/intel/socket_rPGA989
device lapic 0 on end
diff --git a/src/mainboard/samsung/lumpy/romstage.c b/src/mainboard/samsung/lumpy/romstage.c
index 791afe9..3e3bd9a 100644
--- a/src/mainboard/samsung/lumpy/romstage.c
+++ b/src/mainboard/samsung/lumpy/romstage.c
@@ -31,6 +31,7 @@
#include <tpm.h>
#include <northbridge/intel/sandybridge/sandybridge.h>
#include <northbridge/intel/sandybridge/raminit.h>
+#include <northbridge/intel/sandybridge/raminit_native.h>
#include <southbridge/intel/bd82x6x/pch.h>
#include <arch/cpu.h>
#include <cpu/x86/msr.h>
@@ -112,53 +113,9 @@ void rcba_config(void)
RCBA32(FD) = reg32;
}
-void mainboard_fill_pei_data(struct pei_data *pei_data)
+uint8_t *locate_spd(void)
{
- struct pei_data pei_data_template = {
- .pei_version = PEI_VERSION,
- .mchbar = (uintptr_t)DEFAULT_MCHBAR,
- .dmibar = (uintptr_t)DEFAULT_DMIBAR,
- .epbar = DEFAULT_EPBAR,
- .pciexbar = CONFIG_MMCONF_BASE_ADDRESS,
- .smbusbar = SMBUS_IO_BASE,
- .wdbbar = 0x4000000,
- .wdbsize = 0x1000,
- .hpet_address = CONFIG_HPET_ADDRESS,
- .rcba = (uintptr_t)DEFAULT_RCBABASE,
- .pmbase = DEFAULT_PMBASE,
- .gpiobase = DEFAULT_GPIOBASE,
- .thermalbase = 0xfed08000,
- .system_type = 0, // 0 Mobile, 1 Desktop/Server
- .tseg_size = CONFIG_SMM_TSEG_SIZE,
- .spd_addresses = { 0xa0, 0x00,0x00,0x00 },
- .ts_addresses = { 0x30, 0x00, 0x00, 0x00 },
- .ec_present = 1,
- // 0 = leave channel enabled
- // 1 = disable dimm 0 on channel
- // 2 = disable dimm 1 on channel
- // 3 = disable dimm 0+1 on channel
- .dimm_channel0_disabled = 2,
- .dimm_channel1_disabled = 2,
- .max_ddr3_freq = 1333,
- .usb_port_config = {
- { 1, 0, 0x0080 }, /* P0: Port 0 (OC0) */
- { 1, 1, 0x0080 }, /* P1: Port 1 (OC1) */
- { 1, 0, 0x0040 }, /* P2: MINIPCIE1 (no OC) */
- { 1, 0, 0x0040 }, /* P3: MMC (no OC) */
- { 0, 0, 0x0000 }, /* P4: Empty */
- { 0, 0, 0x0000 }, /* P5: Empty */
- { 0, 0, 0x0000 }, /* P6: Empty */
- { 0, 0, 0x0000 }, /* P7: Empty */
- { 1, 4, 0x0040 }, /* P8: MINIPCIE2 (no OC) */
- { 0, 4, 0x0000 }, /* P9: Empty */
- { 0, 4, 0x0000 }, /* P10: Empty */
- { 1, 4, 0x0040 }, /* P11: Camera (no OC) */
- { 0, 4, 0x0000 }, /* P12: Empty */
- { 0, 4, 0x0000 }, /* P13: Empty */
- },
- };
- *pei_data = pei_data_template;
- typedef const uint8_t spd_blob[256];
+ typedef const uint8_t spd_blob[256];
spd_blob *spd_data;
size_t spd_file_len;
@@ -207,9 +164,86 @@ void mainboard_fill_pei_data(struct pei_data *pei_data)
if (spd_file_len < (spd_index + 1) * 256)
die("Missing SPD data.");
// leave onboard dimm address at f0, and copy spd data there.
- memcpy(pei_data->spd_data[0], spd_data[spd_index], 256);
+ return spd_data[spd_index];
}
+void mainboard_fill_pei_data(struct pei_data *pei_data)
+{
+ struct pei_data pei_data_template = {
+ .pei_version = PEI_VERSION,
+ .mchbar = (uintptr_t)DEFAULT_MCHBAR,
+ .dmibar = (uintptr_t)DEFAULT_DMIBAR,
+ .epbar = DEFAULT_EPBAR,
+ .pciexbar = CONFIG_MMCONF_BASE_ADDRESS,
+ .smbusbar = SMBUS_IO_BASE,
+ .wdbbar = 0x4000000,
+ .wdbsize = 0x1000,
+ .hpet_address = CONFIG_HPET_ADDRESS,
+ .rcba = (uintptr_t)DEFAULT_RCBABASE,
+ .pmbase = DEFAULT_PMBASE,
+ .gpiobase = DEFAULT_GPIOBASE,
+ .thermalbase = 0xfed08000,
+ .system_type = 0, // 0 Mobile, 1 Desktop/Server
+ .tseg_size = CONFIG_SMM_TSEG_SIZE,
+ .spd_addresses = { 0xa0, 0x00,0x00,0x00 },
+ .ts_addresses = { 0x30, 0x00, 0x00, 0x00 },
+ .ec_present = 1,
+ // 0 = leave channel enabled
+ // 1 = disable dimm 0 on channel
+ // 2 = disable dimm 1 on channel
+ // 3 = disable dimm 0+1 on channel
+ .dimm_channel0_disabled = 2,
+ .dimm_channel1_disabled = 2,
+ .max_ddr3_freq = 1333,
+ .usb_port_config = {
+ { 1, 0, 0x0080 }, /* P0: Port 0 (OC0) */
+ { 1, 1, 0x0080 }, /* P1: Port 1 (OC1) */
+ { 1, 0, 0x0040 }, /* P2: MINIPCIE1 (no OC) */
+ { 1, 0, 0x0040 }, /* P3: MMC (no OC) */
+ { 0, 0, 0x0000 }, /* P4: Empty */
+ { 0, 0, 0x0000 }, /* P5: Empty */
+ { 0, 0, 0x0000 }, /* P6: Empty */
+ { 0, 0, 0x0000 }, /* P7: Empty */
+ { 1, 4, 0x0040 }, /* P8: MINIPCIE2 (no OC) */
+ { 0, 4, 0x0000 }, /* P9: Empty */
+ { 0, 4, 0x0000 }, /* P10: Empty */
+ { 1, 4, 0x0040 }, /* P11: Camera (no OC) */
+ { 0, 4, 0x0000 }, /* P12: Empty */
+ { 0, 4, 0x0000 }, /* P13: Empty */
+ },
+ };
+ *pei_data = pei_data_template;
+ // leave onboard dimm address at f0, and copy spd data there.
+ memcpy(pei_data->spd_data[0], locate_spd(), 256);
+}
+
+const struct southbridge_usb_port mainboard_usb_ports[] = {
+ /* enabled power usb oc pin */
+ { 1, 1, 0 }, /* P0: Port 0 (OC0) */
+ { 1, 1, 1 }, /* P1: Port 1 (OC1) */
+ { 1, 0, -1 }, /* P2: MINIPCIE1 (no OC) */
+ { 1, 0, -1 }, /* P3: MMC (no OC) */
+ { 0, 0, -1 }, /* P4: Empty */
+ { 0, 0, -1 }, /* P5: Empty */
+ { 0, 0, -1 }, /* P6: Empty */
+ { 0, 0, -1 }, /* P7: Empty */
+ { 1, 0, -1 }, /* P8: MINIPCIE2 (no OC) */
+ { 0, 0, -1 }, /* P9: Empty */
+ { 0, 0, -1 }, /* P10: Empty */
+ { 1, 0, -1 }, /* P11: Camera (no OC) */
+ { 0, 0, -1 }, /* P12: Empty */
+ { 0, 0, -1 }, /* P13: Empty */
+};
+
+void mainboard_get_spd(spd_raw_data *spd)
+{
+ memcpy(&spd[0], locate_spd(), 128);
+}
+
+const struct southbridge_usb_port mainboard_usb_ports[] = {
+ /* enabled power usb oc pin */
+};
+
void mainboard_early_init(int s3resume)
{
init_bootmode_straps();
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