[coreboot-gerrit] New patch to review for coreboot: tegra132/210: Remove memlayout_vboot2.ld
Julius Werner (jwerner@chromium.org)
gerrit at coreboot.org
Wed Feb 10 08:18:07 CET 2016
Julius Werner (jwerner at chromium.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13667
-gerrit
commit 3ae02da979be1b7f2dc81084567f6bffb4b29ccf
Author: Julius Werner <jwerner at chromium.org>
Date: Tue Feb 9 22:47:11 2016 -0800
tegra132/210: Remove memlayout_vboot2.ld
Having two separate memlayouts is as unnecessary complication.
Contributors need to make sure that their code fits into the vboot one
(with smaller stage sizes) either way, and the Tegras have plenty of
SRAM anyway. Let's just make the vboot layout the default (as it was
done on other SoCs) to keep things easier to maintain. The empty SRAM
holes on non-vboot systems where the verstage and work buffer would've
been won't hurt them.
BRANCH=None
BUG=None
TEST=Ran abuild with and without --chromeos on Foster, Rush, Ryu and
Smaug.
Change-Id: If37228facb4de1459cc720dca10bf03e04eb9930
Signed-off-by: Julius Werner <jwerner at chromium.org>
---
src/mainboard/google/foster/memlayout.ld | 5 ---
src/mainboard/google/rush/memlayout.ld | 4 --
src/mainboard/google/rush_ryu/memlayout.ld | 4 --
src/mainboard/google/smaug/memlayout.ld | 5 ---
src/soc/nvidia/tegra132/include/soc/memlayout.ld | 14 ++++---
.../tegra132/include/soc/memlayout_vboot2.ld | 49 ----------------------
src/soc/nvidia/tegra210/include/soc/memlayout.ld | 14 ++++---
.../tegra210/include/soc/memlayout_vboot2.ld | 49 ----------------------
8 files changed, 16 insertions(+), 128 deletions(-)
diff --git a/src/mainboard/google/foster/memlayout.ld b/src/mainboard/google/foster/memlayout.ld
index c53f744..ead7f47 100644
--- a/src/mainboard/google/foster/memlayout.ld
+++ b/src/mainboard/google/foster/memlayout.ld
@@ -1,6 +1 @@
-#if IS_ENABLED(CONFIG_VBOOT_VERIFY_FIRMWARE)
-#include <soc/memlayout_vboot2.ld>
-#else
#include <soc/memlayout.ld>
-#endif
-
diff --git a/src/mainboard/google/rush/memlayout.ld b/src/mainboard/google/rush/memlayout.ld
index 367a88e..ead7f47 100644
--- a/src/mainboard/google/rush/memlayout.ld
+++ b/src/mainboard/google/rush/memlayout.ld
@@ -1,5 +1 @@
-#if IS_ENABLED(CONFIG_VBOOT_VERIFY_FIRMWARE)
-#include <soc/memlayout_vboot2.ld>
-#else
#include <soc/memlayout.ld>
-#endif
diff --git a/src/mainboard/google/rush_ryu/memlayout.ld b/src/mainboard/google/rush_ryu/memlayout.ld
index 367a88e..ead7f47 100644
--- a/src/mainboard/google/rush_ryu/memlayout.ld
+++ b/src/mainboard/google/rush_ryu/memlayout.ld
@@ -1,5 +1 @@
-#if IS_ENABLED(CONFIG_VBOOT_VERIFY_FIRMWARE)
-#include <soc/memlayout_vboot2.ld>
-#else
#include <soc/memlayout.ld>
-#endif
diff --git a/src/mainboard/google/smaug/memlayout.ld b/src/mainboard/google/smaug/memlayout.ld
index c53f744..ead7f47 100644
--- a/src/mainboard/google/smaug/memlayout.ld
+++ b/src/mainboard/google/smaug/memlayout.ld
@@ -1,6 +1 @@
-#if IS_ENABLED(CONFIG_VBOOT_VERIFY_FIRMWARE)
-#include <soc/memlayout_vboot2.ld>
-#else
#include <soc/memlayout.ld>
-#endif
-
diff --git a/src/soc/nvidia/tegra132/include/soc/memlayout.ld b/src/soc/nvidia/tegra132/include/soc/memlayout.ld
index aad3083..e3d221e 100644
--- a/src/soc/nvidia/tegra132/include/soc/memlayout.ld
+++ b/src/soc/nvidia/tegra132/include/soc/memlayout.ld
@@ -29,15 +29,17 @@ SECTIONS
{
SRAM_START(0x40000000)
PRERAM_CBMEM_CONSOLE(0x40000000, 8K)
- PRERAM_CBFS_CACHE(0x40002000, 84K)
+ PRERAM_CBFS_CACHE(0x40002000, 72K)
+ VBOOT2_WORK(0x40014000, 12K)
#if ENV_ARM64
- STACK(0x40017000, 8K)
+ STACK(0x40017000, 3K)
#else /* AVP gets a separate stack to avoid any chance of handoff races. */
- STACK(0x40019000, 6K)
+ STACK(0x40017C00, 3K)
#endif
- TIMESTAMP(0x4001A800, 2K)
- BOOTBLOCK(0x4001B800, 22K)
- ROMSTAGE(0x40021000, 124K)
+ TIMESTAMP(0x40018800, 2K)
+ BOOTBLOCK(0x40019000, 22K)
+ VERSTAGE(0x4001e800, 55K)
+ ROMSTAGE(0x4002c400, 77K)
SRAM_END(0x40040000)
DRAM_START(0x80000000)
diff --git a/src/soc/nvidia/tegra132/include/soc/memlayout_vboot2.ld b/src/soc/nvidia/tegra132/include/soc/memlayout_vboot2.ld
deleted file mode 100644
index e3d221e..0000000
--- a/src/soc/nvidia/tegra132/include/soc/memlayout_vboot2.ld
+++ /dev/null
@@ -1,49 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright 2014 Google Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <memlayout.h>
-#include <rules.h>
-
-#include <arch/header.ld>
-
-/*
- * Note: The BootROM uses the address range [0x4000_0000:0x4000_E000) itself,
- * so the bootblock loading address must be placed after that. After the
- * handoff that area may be reclaimed for other uses, e.g. CBFS cache.
- * TODO: Did this change on Tegra132? What's the new valid range?
- */
-
-SECTIONS
-{
- SRAM_START(0x40000000)
- PRERAM_CBMEM_CONSOLE(0x40000000, 8K)
- PRERAM_CBFS_CACHE(0x40002000, 72K)
- VBOOT2_WORK(0x40014000, 12K)
-#if ENV_ARM64
- STACK(0x40017000, 3K)
-#else /* AVP gets a separate stack to avoid any chance of handoff races. */
- STACK(0x40017C00, 3K)
-#endif
- TIMESTAMP(0x40018800, 2K)
- BOOTBLOCK(0x40019000, 22K)
- VERSTAGE(0x4001e800, 55K)
- ROMSTAGE(0x4002c400, 77K)
- SRAM_END(0x40040000)
-
- DRAM_START(0x80000000)
- POSTRAM_CBFS_CACHE(0x80100000, 1M)
- RAMSTAGE(0x80200000, 256K)
- TTB(0x100000000 - CONFIG_TRUSTZONE_CARVEOUT_SIZE_MB * 1M, 1M)
-}
diff --git a/src/soc/nvidia/tegra210/include/soc/memlayout.ld b/src/soc/nvidia/tegra210/include/soc/memlayout.ld
index 00ecd28..c1c581b 100644
--- a/src/soc/nvidia/tegra210/include/soc/memlayout.ld
+++ b/src/soc/nvidia/tegra210/include/soc/memlayout.ld
@@ -29,15 +29,17 @@ SECTIONS
{
SRAM_START(0x40000000)
PRERAM_CBMEM_CONSOLE(0x40000000, 8K)
- PRERAM_CBFS_CACHE(0x40002000, 84K)
+ PRERAM_CBFS_CACHE(0x40002000, 36K)
+ VBOOT2_WORK(0x4000B000, 12K)
#if ENV_ARM64
- STACK(0x40017000, 8K)
+ STACK(0x4000E000, 3K)
#else /* AVP gets a separate stack to avoid any chance of handoff races. */
- STACK(0x40019000, 8K)
+ STACK(0x4000EC00, 3K)
#endif
- TIMESTAMP(0x4001B000, 2K)
- BOOTBLOCK(0x4001B800, 24K)
- ROMSTAGE(0x40022000, 120K)
+ TIMESTAMP(0x4000F800, 2K)
+ BOOTBLOCK(0x40010000, 28K)
+ VERSTAGE(0x40017000, 64K)
+ ROMSTAGE(0x40027000, 100K)
SRAM_END(0x40040000)
DRAM_START(0x80000000)
diff --git a/src/soc/nvidia/tegra210/include/soc/memlayout_vboot2.ld b/src/soc/nvidia/tegra210/include/soc/memlayout_vboot2.ld
deleted file mode 100644
index c1c581b..0000000
--- a/src/soc/nvidia/tegra210/include/soc/memlayout_vboot2.ld
+++ /dev/null
@@ -1,49 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright 2014 Google Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <memlayout.h>
-#include <rules.h>
-
-#include <arch/header.ld>
-
-/*
- * Note: The BootROM uses the address range [0x4000_0000:0x4000_E000) itself,
- * so the bootblock loading address must be placed after that. After the
- * handoff that area may be reclaimed for other uses, e.g. CBFS cache.
- * TODO: Did this change on Tegra210? What's the new valid range?
- */
-
-SECTIONS
-{
- SRAM_START(0x40000000)
- PRERAM_CBMEM_CONSOLE(0x40000000, 8K)
- PRERAM_CBFS_CACHE(0x40002000, 36K)
- VBOOT2_WORK(0x4000B000, 12K)
-#if ENV_ARM64
- STACK(0x4000E000, 3K)
-#else /* AVP gets a separate stack to avoid any chance of handoff races. */
- STACK(0x4000EC00, 3K)
-#endif
- TIMESTAMP(0x4000F800, 2K)
- BOOTBLOCK(0x40010000, 28K)
- VERSTAGE(0x40017000, 64K)
- ROMSTAGE(0x40027000, 100K)
- SRAM_END(0x40040000)
-
- DRAM_START(0x80000000)
- POSTRAM_CBFS_CACHE(0x80100000, 1M)
- RAMSTAGE(0x80200000, 256K)
- TTB(0x100000000 - CONFIG_TTB_SIZE_MB * 1M, CONFIG_TTB_SIZE_MB * 1M)
-}
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