[coreboot-gerrit] New patch to review for coreboot: nb/amd/amdmct: Add socket specific configuration for FM2
Damien Zammit (damien@zamaudio.com)
gerrit at coreboot.org
Sun Feb 14 03:44:41 CET 2016
Damien Zammit (damien at zamaudio.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13709
-gerrit
commit 22e925285f75663f4560b948dad156aea65927eb
Author: Damien Zammit <damien at zamaudio.com>
Date: Sat Feb 13 16:53:34 2016 +1100
nb/amd/amdmct: Add socket specific configuration for FM2
Change-Id: I1088064e5f84fcabcd51e0eaaedfb5074f7fb2b5
Signed-off-by: Damien Zammit <damien at zamaudio.com>
---
src/northbridge/amd/amdmct/mct_ddr3/mct_d.c | 209 ++++++++++++++++++++++++++-
src/northbridge/amd/amdmct/mct_ddr3/mct_d.h | 1 +
src/northbridge/amd/amdmct/mct_ddr3/mctsdi.c | 44 ++++++
src/northbridge/amd/amdmct/wrappers/mcti_d.c | 2 +
4 files changed, 249 insertions(+), 7 deletions(-)
diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c b/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c
index e1c0d4f..322318d 100644
--- a/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c
+++ b/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c
@@ -686,6 +686,19 @@ static uint32_t fam15h_phy_predriver_calibration_code(struct DCTStatStruc *pDCTs
calibration_code = 0xb6d;
}
}
+ } else if (package_type == PT_FM2) {
+ /* Socket FM2 */
+ if (ddr_voltage_index & 0x1) {
+ /* 1.5V */
+ /* Fam15h BKDG Rev. 3.12 section 2.9.5.4.4 Table 22 */
+ if ((MemClkFreq == 0x4) || (MemClkFreq == 0x6)) {
+ /* DDR3-667 - DDR3-800 */
+ calibration_code = 0xb24;
+ } else if (MemClkFreq >= 0xa) {
+ /* DDR3-1066 or higher */
+ calibration_code = 0xff6;
+ }
+ }
}
} else {
/* LRDIMM */
@@ -1242,6 +1255,66 @@ static uint32_t fam15h_output_driver_compensation_code(struct DCTStatStruc *pDCT
*/
}
}
+ } else if (package_type == PT_FM2) {
+ /* Socket FM2 */
+ /* Assume UDIMM */
+ /* Fam15h Model10h BKDG Rev. 3.12 section 2.9.5.6.6 Table 32 */
+ if (MaxDimmsInstallable == 1) {
+ rank_count_dimm0 = pDCTstat->DimmRanks[(1 * 2) + dct];
+
+ if (MemClkFreq == 0x4) {
+ /* DDR3-667 */
+ calibration_code = 0x00112222;
+ } else if (MemClkFreq == 0x6) {
+ /* DDR3-800 */
+ calibration_code = 0x10112222;
+ } else if (MemClkFreq == 0xa) {
+ /* DDR3-1066 */
+ calibration_code = 0x20112222;
+ } else if (MemClkFreq >= 0xe) {
+ /* DDR3-1333 or higher */
+ calibration_code = 0x30112222;
+ }
+ } else if (MaxDimmsInstallable == 2) {
+ rank_count_dimm0 = pDCTstat->DimmRanks[(0 * 2) + dct];
+ rank_count_dimm1 = pDCTstat->DimmRanks[(1 * 2) + dct];
+
+ if (dimm_count == 1) {
+ /* 1 DIMM detected */
+ if ((MemClkFreq == 0x4) || (MemClkFreq == 0x6)) {
+ /* DDR3-667 or DDR3-800 */
+ calibration_code = 0x00112222;
+ } else if (MemClkFreq == 0xa) {
+ /* DDR3-1066 */
+ calibration_code = 0x10112222;
+ } else if (MemClkFreq == 0xe) {
+ /* DDR3-1333 */
+ calibration_code = 0x20112222;
+ } else if (MemClkFreq >= 0x12) {
+ /* DDR3-1600 or higher */
+ calibration_code = 0x30112222;
+ }
+ } else if (dimm_count == 2) {
+ /* 2 DIMMs detected */
+ rank_count_dimm0 = pDCTstat->DimmRanks[(0 * 2) + dct];
+ rank_count_dimm1 = pDCTstat->DimmRanks[(1 * 2) + dct];
+
+ if (MemClkFreq == 0x4) {
+ /* DDR3-667 */
+ calibration_code = 0x10222322;
+ } else if (MemClkFreq == 0x6) {
+ /* DDR3-800 */
+ calibration_code = 0x20222322;
+ } else if (MemClkFreq >= 0xa) {
+ /* DDR3-1066 or higher */
+ calibration_code = 0x30222322;
+ }
+ }
+ } else if (MaxDimmsInstallable == 3) {
+ /* TODO
+ * 3 DIMM/channel support unimplemented
+ */
+ }
} else {
/* TODO
* Other socket support unimplemented
@@ -1574,6 +1647,63 @@ static uint32_t fam15h_address_timing_compensation_code(struct DCTStatStruc *pDC
*/
}
}
+ } else if (package_type == PT_FM2) {
+ /* Socket FM2 */
+ /* Assume UDIMM */
+ /* Fam15h Model10h BKDG Rev. 3.12 section 2.9.5.6.6 Table 32 */
+ if (dimm_count == 1) {
+ /* 1 DIMM detected */
+ rank_count_dimm0 = pDCTstat->DimmRanks[(1 * 2) + dct];
+
+ if ((MemClkFreq == 0x4) || (MemClkFreq == 0x6)) {
+ /* DDR3-667 or DDR3-800 */
+ if (rank_count_dimm0 == 1)
+ calibration_code = 0x00000000;
+ else
+ calibration_code = 0x003b0000;
+ } else if (MemClkFreq == 0xa) {
+ /* DDR3-1066 */
+ if (rank_count_dimm0 == 1)
+ calibration_code = 0x00000000;
+ else
+ calibration_code = 0x00380000;
+ } else if (MemClkFreq == 0xe) {
+ /* DDR3-1333 */
+ if (rank_count_dimm0 == 1)
+ calibration_code = 0x00000000;
+ else
+ calibration_code = 0x00360000;
+ } else if (MemClkFreq >= 0x12) {
+ /* DDR3-1600 or higher */
+ calibration_code = 0x00000000;
+ }
+
+ } else if (dimm_count == 2) {
+ /* 2 DIMMs detected */
+ rank_count_dimm0 = pDCTstat->DimmRanks[(0 * 2) + dct];
+ rank_count_dimm1 = pDCTstat->DimmRanks[(1 * 2) + dct];
+
+ if ((MemClkFreq == 0x4) || (MemClkFreq == 0x6)) {
+ /* DDR3-667 or DDR3-800 */
+ calibration_code = 0x00390039;
+ } else if (MemClkFreq == 0xa) {
+ /* DDR3-1066 */
+ calibration_code = 0x00350037;
+ } else if (MemClkFreq == 0xe) {
+ /* DDR3-1333 */
+ calibration_code = 0x00000035;
+ } else if (MemClkFreq == 0x12) {
+ /* DDR3-1600 */
+ calibration_code = 0x0000002b;
+ } else if (MemClkFreq > 0x12) {
+ /* DDR3-1866 or greater */
+ calibration_code = 0x00000031;
+ }
+ } else if (MaxDimmsInstallable == 3) {
+ /* TODO
+ * 3 DIMM/channel support unimplemented
+ */
+ }
} else {
/* TODO
* Other socket support unimplemented
@@ -1724,6 +1854,59 @@ static uint8_t fam15h_slow_access_mode(struct DCTStatStruc *pDCTstat, uint8_t dc
*/
}
}
+ } else if (package_type == PT_FM2) {
+ /* Socket FM2 */
+ /* UDIMM */
+ /* Fam15h Model10 BKDG Rev. 3.12 section 2.9.5.6.6 Table 32 */
+ if (MaxDimmsInstallable == 1) {
+ rank_count_dimm0 = pDCTstat->DimmRanks[(1 * 2) + dct];
+
+ if ((MemClkFreq == 0x4) || (MemClkFreq == 0x6)
+ || (MemClkFreq == 0xa) | (MemClkFreq == 0xe)) {
+ /* DDR3-667 - DDR3-1333 */
+ slow_access = 0;
+ } else if (MemClkFreq >= 0x12) {
+ /* DDR3-1600 or higher */
+ if (rank_count_dimm0 == 1)
+ slow_access = 0;
+ else
+ slow_access = 1;
+ }
+ } else if (MaxDimmsInstallable == 2) {
+ if (dimm_count == 1) {
+ /* 1 DIMM detected */
+ rank_count_dimm0 = pDCTstat->DimmRanks[(1 * 2) + dct];
+
+ if ((MemClkFreq == 0x4) || (MemClkFreq == 0x6)
+ || (MemClkFreq == 0xa) | (MemClkFreq == 0xe)) {
+ /* DDR3-667 - DDR3-1333 */
+ slow_access = 0;
+ } else if (MemClkFreq >= 0x12) {
+ /* DDR3-1600 or higher */
+ if (rank_count_dimm0 == 1)
+ slow_access = 0;
+ else
+ slow_access = 1;
+ }
+ } else if (dimm_count == 2) {
+ /* 2 DIMMs detected */
+ rank_count_dimm0 = pDCTstat->DimmRanks[(0 * 2) + dct];
+ rank_count_dimm1 = pDCTstat->DimmRanks[(1 * 2) + dct];
+
+ if ((MemClkFreq == 0x4) || (MemClkFreq == 0x6)
+ || (MemClkFreq == 0xa)) {
+ /* DDR3-667 - DDR3-1066 */
+ slow_access = 0;
+ } else if (MemClkFreq >= 0xe) {
+ /* DDR3-1333 or higher */
+ slow_access = 1;
+ }
+ }
+ } else if (MaxDimmsInstallable == 3) {
+ /* TODO
+ * 3 DIMM/channel support unimplemented
+ */
+ }
} else {
/* TODO
* Other socket support unimplemented
@@ -1919,6 +2102,11 @@ static uint8_t fam15h_odt_tristate_enable_code(struct DCTStatStruc *pDCTstat, ui
*/
}
}
+ } else if (package_type == PT_FM2) {
+ /* Socket FM2 */
+ /* UDIMM */
+ /* Fam15h Model10h BKDG Rev. 3.12 section 2.9.2 Table 19 */
+ odt_tristate_code = 0xf;
} else {
/* TODO
* Other socket support unimplemented
@@ -2114,6 +2302,11 @@ static uint8_t fam15h_cs_tristate_enable_code(struct DCTStatStruc *pDCTstat, uin
*/
}
}
+ } else if (package_type == PT_FM2) {
+ /* Socket FM2 */
+ /* UDIMM */
+ /* Fam15h Model10 BKDG Rev. 3.12 section 2.9.2 Table 19 */
+ cs_tristate_code = 0x0f;
} else {
/* TODO
* Other socket support unimplemented
@@ -6445,7 +6638,7 @@ void mct_ForceNBPState0_En_Fam15(struct MCTStatStruc *pMCTstat,
{
/* Force the NB P-state to P0 */
uint32_t dword;
- uint32_t dword2;
+ //uint32_t dword2;
dword = Get_NB32(pDCTstat->dev_nbctl, 0x174);
if (!(dword & 0x1)) {
@@ -6462,9 +6655,9 @@ void mct_ForceNBPState0_En_Fam15(struct MCTStatStruc *pMCTstat,
Set_NB32(pDCTstat->dev_nbctl, 0x170, dword);
/* Wait until CurNbPState == NbPstateLo */
- do {
- dword2 = Get_NB32(pDCTstat->dev_nbctl, 0x174);
- } while (((dword2 << 19) & 0x7) != (dword & 0x3));
+// do {
+// dword2 = Get_NB32(pDCTstat->dev_nbctl, 0x174);
+// } while (((dword2 << 19) & 0x7) != (dword & 0x3));
dword = Get_NB32(pDCTstat->dev_nbctl, 0x170);
dword &= ~(0x3 << 6); /* NbPstateHi = 0 */
@@ -6472,9 +6665,9 @@ void mct_ForceNBPState0_En_Fam15(struct MCTStatStruc *pMCTstat,
Set_NB32(pDCTstat->dev_nbctl, 0x170, dword);
/* Wait until CurNbPState == 0 */
- do {
- dword2 = Get_NB32(pDCTstat->dev_nbctl, 0x174);
- } while (((dword2 << 19) & 0x7) != 0);
+// do {
+// dword2 = Get_NB32(pDCTstat->dev_nbctl, 0x174);
+// } while (((dword2 << 19) & 0x7) != 0);
}
}
@@ -6960,6 +7153,7 @@ static void InitPhyCompensation(struct MCTStatStruc *pMCTstat,
* to the hardware. The BKDG does not require this, but it does take
* some time for the data to propagate, so it's probably a good idea.
*/
+ /*
uint8_t predriver_cal_pending = 1;
printk(BIOS_DEBUG, "Waiting for predriver calibration to be applied...");
while (predriver_cal_pending) {
@@ -6970,6 +7164,7 @@ static void InitPhyCompensation(struct MCTStatStruc *pMCTstat,
}
}
printk(BIOS_DEBUG, "done!\n");
+ */
} else {
dword = Get_NB32_index_wait_DCT(dev, dct, index_reg, 0x00);
dword = 0;
diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mct_d.h b/src/northbridge/amd/amdmct/mct_ddr3/mct_d.h
index e7361ac..6faa975 100644
--- a/src/northbridge/amd/amdmct/mct_ddr3/mct_d.h
+++ b/src/northbridge/amd/amdmct/mct_ddr3/mct_d.h
@@ -31,6 +31,7 @@
#define PT_GR 3
#define PT_AS 4
#define PT_C3 5
+#define PT_FM2 6
#define J_MIN 0 /* j loop constraint. 1=CL 2.0 T*/
#define J_MAX 5 /* j loop constraint. 5=CL 7.0 T*/
diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mctsdi.c b/src/northbridge/amd/amdmct/mct_ddr3/mctsdi.c
index bcf6031..1947061 100644
--- a/src/northbridge/amd/amdmct/mct_ddr3/mctsdi.c
+++ b/src/northbridge/amd/amdmct/mct_ddr3/mctsdi.c
@@ -239,6 +239,19 @@ static uint8_t fam15_rttwr(struct DCTStatStruc *pDCTstat, uint8_t dct, uint8_t d
term = 0x2;
}
}
+ } else if (package_type == PT_FM2) {
+ /* Socket FM2: Fam15h Model10 BKDG 3.12 Table 32 */
+ if (MaxDimmsInstallable == 1) {
+ term = 0x0;
+ } else if (MaxDimmsInstallable == 2) {
+ if ((number_of_dimms == 2) && (frequency_index >= 0x12)) {
+ term = 0x1;
+ } else if (number_of_dimms == 1) {
+ term = 0x0;
+ } else {
+ term = 0x2;
+ }
+ }
} else {
/* TODO
* Other sockets unimplemented
@@ -606,6 +619,37 @@ static uint8_t fam15_rttnom(struct DCTStatStruc *pDCTstat, uint8_t dct, uint8_t
}
}
}
+ } else if (package_type == PT_FM2) {
+ /* Socket FM2: Fam15h Model10 BKDG 3.12 Table 32 */
+ if (MaxDimmsInstallable == 1) {
+ if ((frequency_index == 0x4)
+ || (frequency_index == 0x6)
+ || (frequency_index == 0xa))
+ term = 0x4;
+ else if (frequency_index == 0xe)
+ term = 0x3;
+ else if (frequency_index >= 0x12)
+ term = 0x2;
+ }
+ if (MaxDimmsInstallable == 2) {
+ if (number_of_dimms == 1) {
+ if (frequency_index <= 0xa) {
+ term = 0x4;
+ } else if (frequency_index <= 0xe) {
+ term = 0x3;
+ } else {
+ term = 0x2;
+ }
+ } else {
+ if (frequency_index <= 0xa) {
+ term = 0x2;
+ } else if (frequency_index <= 0xe) {
+ term = 0x1;
+ } else {
+ term = 0x0;
+ }
+ }
+ }
} else {
/* TODO
* Other sockets unimplemented
diff --git a/src/northbridge/amd/amdmct/wrappers/mcti_d.c b/src/northbridge/amd/amdmct/wrappers/mcti_d.c
index dc4186e..12115c5 100644
--- a/src/northbridge/amd/amdmct/wrappers/mcti_d.c
+++ b/src/northbridge/amd/amdmct/wrappers/mcti_d.c
@@ -59,6 +59,8 @@ static u16 mctGet_NVbits(u8 index)
val = 5;
#elif CONFIG_CPU_SOCKET_TYPE == 0x15 /* G34 */
val = 3;
+#elif CONFIG_CPU_SOCKET_TYPE == 0x16 /* FM2 */
+ val = 6;
//#elif SYSTEM_TYPE == MOBILE
// val = 2;
#endif
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