[coreboot-gerrit] Patch set updated for coreboot: mb/asus/f2a85-m_fam10: Add ASUS F2A85-M (using non-AGESA)
Damien Zammit (damien@zamaudio.com)
gerrit at coreboot.org
Wed Feb 17 04:59:34 CET 2016
Damien Zammit (damien at zamaudio.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13712
-gerrit
commit 500a1100b51c9bc3b77c9dc18b4bbd3727c2681f
Author: Damien Zammit <damien at zamaudio.com>
Date: Wed Feb 10 14:06:30 2016 +1100
mb/asus/f2a85-m_fam10: Add ASUS F2A85-M (using non-AGESA)
Change-Id: I28717d9e78336e6097fd91f270cac2bfed9534d8
Signed-off-by: Damien Zammit <damien at zamaudio.com>
---
src/mainboard/asus/f2a85-m_fam10/Kconfig | 99 ++++++
src/mainboard/asus/f2a85-m_fam10/Kconfig.name | 2 +
src/mainboard/asus/f2a85-m_fam10/acpi/cpstate.asl | 111 +++++++
src/mainboard/asus/f2a85-m_fam10/acpi/gpe.asl | 72 +++++
.../asus/f2a85-m_fam10/acpi/mainboard.asl | 32 ++
src/mainboard/asus/f2a85-m_fam10/acpi/routing.asl | 258 +++++++++++++++
src/mainboard/asus/f2a85-m_fam10/acpi/sata.asl | 16 +
src/mainboard/asus/f2a85-m_fam10/acpi/si.asl | 22 ++
src/mainboard/asus/f2a85-m_fam10/acpi/sleep.asl | 96 ++++++
src/mainboard/asus/f2a85-m_fam10/acpi/superio.asl | 16 +
src/mainboard/asus/f2a85-m_fam10/acpi/thermal.asl | 16 +
src/mainboard/asus/f2a85-m_fam10/acpi/usb_oc.asl | 27 ++
src/mainboard/asus/f2a85-m_fam10/acpi_tables.c | 48 +++
src/mainboard/asus/f2a85-m_fam10/board_info.txt | 7 +
src/mainboard/asus/f2a85-m_fam10/bootblock.c | 23 ++
src/mainboard/asus/f2a85-m_fam10/cmos.layout | 74 +++++
src/mainboard/asus/f2a85-m_fam10/devicetree.cb | 125 ++++++++
src/mainboard/asus/f2a85-m_fam10/dsdt.asl | 48 +++
src/mainboard/asus/f2a85-m_fam10/get_bus_conf.c | 5 +
src/mainboard/asus/f2a85-m_fam10/hdaverb | 24 ++
src/mainboard/asus/f2a85-m_fam10/irq_tables.c | 103 ++++++
src/mainboard/asus/f2a85-m_fam10/mainboard.c | 47 +++
src/mainboard/asus/f2a85-m_fam10/mptable.c | 182 +++++++++++
src/mainboard/asus/f2a85-m_fam10/romstage.c | 353 +++++++++++++++++++++
24 files changed, 1806 insertions(+)
diff --git a/src/mainboard/asus/f2a85-m_fam10/Kconfig b/src/mainboard/asus/f2a85-m_fam10/Kconfig
new file mode 100644
index 0000000..ee0a997
--- /dev/null
+++ b/src/mainboard/asus/f2a85-m_fam10/Kconfig
@@ -0,0 +1,99 @@
+#
+# This file is part of the coreboot project.
+#
+# Copyright (C) 2012 Advanced Micro Devices, Inc.
+# Copyright (C) 2012 Rudolf Marek <r.marek at assembler.cz>
+# Copyright (C) 2016 Damien Zammit <damien at zamaudio.com>
+#
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; version 2 of the License.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+
+if BOARD_ASUS_F2A85_M_FAM10
+
+config BOARD_SPECIFIC_OPTIONS # dummy
+ def_bool y
+ select CPU_AMD_SOCKET_FM2_NON_AGESA
+ select DIMM_DDR3
+ select DIMM_REGISTERED
+ select DIMM_VOLTAGE_SET_SUPPORT
+ select NORTHBRIDGE_AMD_AMDFAM10
+ select SOUTHBRIDGE_AMD_SB900
+ select SUPERIO_ITE_IT8728F
+ select HAVE_OPTION_TABLE
+ select HAVE_PIRQ_TABLE
+ select HAVE_MP_TABLE
+ select HAVE_ACPI_TABLES
+ select BOARD_ROMSIZE_KB_8192
+ select ENABLE_APIC_EXT_ID
+ select PCI
+ select PCIEXP_PLUGIN_SUPPORT
+ select SB_HT_CHAIN_UNITID_OFFSET_ONLY
+
+config HT_CHAIN_END_UNITID_BASE
+ hex
+ default 0x1
+
+config HT_CHAIN_UNITID_BASE
+ hex
+ default 0x0
+
+config MAINBOARD_DIR
+ string
+ default "asus/f2a85-m_fam10"
+
+config MAINBOARD_PART_NUMBER
+ string
+ default "F2A85-M"
+
+config BOOTBLOCK_MAINBOARD_INIT
+ string
+ default "mainboard/asus/f2a85-m_fam10/bootblock.c"
+
+config DCACHE_RAM_BASE
+ hex
+ default 0xc2000
+
+config DCACHE_RAM_SIZE
+ hex
+ default 0x1e000
+
+config APIC_ID_OFFSET
+ hex
+ default 0
+
+config HW_MEM_HOLE_SIZEK
+ hex
+ default 0x200000
+
+config MAX_CPUS
+ int
+ default 32
+
+config MAX_PHYSICAL_CPUS
+ int
+ default 1
+
+config MAINBOARD_POWER_ON_AFTER_POWER_FAIL
+ bool
+ default y
+
+config IRQ_SLOT_COUNT
+ int
+ default 13
+
+config ONBOARD_VGA_IS_PRIMARY
+ bool
+ default y
+
+config VGA_BIOS_ID
+ string
+ default "1002,9993"
+
+endif # BOARD_ASUS_F2A85_M_FAM10
diff --git a/src/mainboard/asus/f2a85-m_fam10/Kconfig.name b/src/mainboard/asus/f2a85-m_fam10/Kconfig.name
new file mode 100644
index 0000000..c3cfb1d
--- /dev/null
+++ b/src/mainboard/asus/f2a85-m_fam10/Kconfig.name
@@ -0,0 +1,2 @@
+config BOARD_ASUS_F2A85_M_FAM10
+ bool "F2A85-M(NONAGESA)"
diff --git a/src/mainboard/asus/f2a85-m_fam10/acpi/cpstate.asl b/src/mainboard/asus/f2a85-m_fam10/acpi/cpstate.asl
new file mode 100644
index 0000000..0951006
--- /dev/null
+++ b/src/mainboard/asus/f2a85-m_fam10/acpi/cpstate.asl
@@ -0,0 +1,111 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2012 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+/* This file defines the processor and performance state capability
+ * for each core in the system. It is included into the DSDT for each
+ * core. It assumes that each core of the system has the same performance
+ * characteristics.
+*/
+/*
+DefinitionBlock ("DSDT.AML","DSDT",0x01,"XXXXXX","XXXXXXXX",0x00010001)
+ {
+ Scope (\_PR) {
+ Processor(CPU0,0,0x808,0x06) {
+ #include "cpstate.asl"
+ }
+ Processor(CPU1,1,0x0,0x0) {
+ #include "cpstate.asl"
+ }
+ Processor(CPU2,2,0x0,0x0) {
+ #include "cpstate.asl"
+ }
+ Processor(CPU3,3,0x0,0x0) {
+ #include "cpstate.asl"
+ }
+ }
+*/
+ /* P-state support: The maximum number of P-states supported by the */
+ /* CPUs we'll use is 6. */
+ /* Get from AMI BIOS. */
+ Name(_PSS, Package(){
+ Package()
+ {
+ 0x00000D48,
+ 0x00011170,
+ 0x00000004,
+ 0x00000004,
+ 0x00000000,
+ 0x00000000
+ },
+
+ Package()
+ {
+ 0x00000AF0,
+ 0x0000C544,
+ 0x00000004,
+ 0x00000004,
+ 0x00000001,
+ 0x00000001
+ },
+
+ Package()
+ {
+ 0x000009C4,
+ 0x0000B3B0,
+ 0x00000004,
+ 0x00000004,
+ 0x00000002,
+ 0x00000002
+ },
+
+ Package()
+ {
+ 0x00000898,
+ 0x0000ABE0,
+ 0x00000004,
+ 0x00000004,
+ 0x00000003,
+ 0x00000003
+ },
+
+ Package()
+ {
+ 0x00000708,
+ 0x0000A410,
+ 0x00000004,
+ 0x00000004,
+ 0x00000004,
+ 0x00000004
+ },
+
+ Package()
+ {
+ 0x00000578,
+ 0x00006F54,
+ 0x00000004,
+ 0x00000004,
+ 0x00000005,
+ 0x00000005
+ }
+ })
+
+ Name(_PCT, Package(){
+ ResourceTemplate(){Register(FFixedHW, 0, 0, 0)},
+ ResourceTemplate(){Register(FFixedHW, 0, 0, 0)}
+ })
+
+ Method(_PPC, 0){
+ Return(0)
+ }
diff --git a/src/mainboard/asus/f2a85-m_fam10/acpi/gpe.asl b/src/mainboard/asus/f2a85-m_fam10/acpi/gpe.asl
new file mode 100644
index 0000000..c34faaf
--- /dev/null
+++ b/src/mainboard/asus/f2a85-m_fam10/acpi/gpe.asl
@@ -0,0 +1,72 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2013 Sage Electronic Engineering, LLC
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+Scope(\_GPE) { /* Start Scope GPE */
+
+ /* General event 3 */
+ Method(_L03) {
+ /* DBGO("\\_GPE\\_L00\n") */
+ Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */
+ }
+
+ /* Legacy PM event */
+ Method(_L08) {
+ /* DBGO("\\_GPE\\_L08\n") */
+ }
+
+ /* Temp warning (TWarn) event */
+ Method(_L09) {
+ /* DBGO("\\_GPE\\_L09\n") */
+ /* Notify (\_TZ.TZ00, 0x80) */
+ }
+
+ /* USB controller PME# */
+ Method(_L0B) {
+ /* DBGO("\\_GPE\\_L0B\n") */
+ Notify(\_SB.PCI0.UOH1, 0x02) /* NOTIFY_DEVICE_WAKE */
+ Notify(\_SB.PCI0.UOH2, 0x02) /* NOTIFY_DEVICE_WAKE */
+ Notify(\_SB.PCI0.UOH3, 0x02) /* NOTIFY_DEVICE_WAKE */
+ Notify(\_SB.PCI0.UOH4, 0x02) /* NOTIFY_DEVICE_WAKE */
+ Notify(\_SB.PCI0.UOH5, 0x02) /* NOTIFY_DEVICE_WAKE */
+ Notify(\_SB.PCI0.UOH6, 0x02) /* NOTIFY_DEVICE_WAKE */
+ Notify(\_SB.PCI0.UEH1, 0x02) /* NOTIFY_DEVICE_WAKE */
+ Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */
+ }
+
+ /* ExtEvent0 SCI event */
+ Method(_L10) {
+ /* DBGO("\\_GPE\\_L10\n") */
+ }
+
+
+ /* ExtEvent1 SCI event */
+ Method(_L11) {
+ /* DBGO("\\_GPE\\_L11\n") */
+ }
+
+ /* GPIO0 or GEvent8 event */
+ Method(_L18) {
+ /* DBGO("\\_GPE\\_L18\n") */
+ Notify(\_SB.PCI0.PBR4, 0x02) /* NOTIFY_DEVICE_WAKE */
+ Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */
+ }
+
+ /* Azalia SCI event */
+ Method(_L1B) {
+ /* DBGO("\\_GPE\\_L1B\n") */
+ Notify(\_SB.PCI0.AZHD, 0x02) /* NOTIFY_DEVICE_WAKE */
+ Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */
+ }
+} /* End Scope GPE */
diff --git a/src/mainboard/asus/f2a85-m_fam10/acpi/mainboard.asl b/src/mainboard/asus/f2a85-m_fam10/acpi/mainboard.asl
new file mode 100644
index 0000000..f88ad68
--- /dev/null
+++ b/src/mainboard/asus/f2a85-m_fam10/acpi/mainboard.asl
@@ -0,0 +1,32 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2013 Sage Electronic Engineering, LLC
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+ /* Data to be patched by the BIOS during POST */
+ /* FIXME the patching is not done yet! */
+ /* Memory related values */
+ Name(LOMH, 0x0) /* Start of unused memory in C0000-E0000 range */
+ Name(PBAD, 0x0) /* Address of BIOS area (If TOM2 != 0, Addr >> 16) */
+ Name(PBLN, 0x0) /* Length of BIOS area */
+
+ Name(PCBA, CONFIG_MMCONF_BASE_ADDRESS) /* Base address of PCIe config space */
+ Name(PCLN, Multiply(0x100000, CONFIG_MMCONF_BUS_NUMBER)) /* Length of PCIe config space, 1MB each bus */
+ Name(HPBA, 0xFED00000) /* Base address of HPET table */
+
+ Name(SSFG, 0x0D) /* S1 support: bit 0, S2 Support: bit 1, etc. S0 & S5 assumed */
+
+ /* Some global data */
+ Name(OSVR, 3) /* Assume nothing. WinXp = 1, Vista = 2, Linux = 3, WinCE = 4 */
+ Name(OSV, Ones) /* Assume nothing */
+ Name(PMOD, One) /* Assume APIC */
diff --git a/src/mainboard/asus/f2a85-m_fam10/acpi/routing.asl b/src/mainboard/asus/f2a85-m_fam10/acpi/routing.asl
new file mode 100644
index 0000000..0af6b42
--- /dev/null
+++ b/src/mainboard/asus/f2a85-m_fam10/acpi/routing.asl
@@ -0,0 +1,258 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2012 Advanced Micro Devices, Inc.
+ * Copyright (C) 2013 Sage Electronic Engineering, LLC
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+ /* Routing is in System Bus scope */
+ Name(PR0, Package(){
+ /* NB devices */
+ /* Bus 0, Dev 0 - F15 Host Controller */
+ Package(){0x0000FFFF, 0, INTA, 0 },
+ Package(){0x0000FFFF, 1, INTB, 0 },
+ Package(){0x0000FFFF, 2, INTC, 0 },
+ Package(){0x0000FFFF, 3, INTD, 0 },
+
+ /* Bus 0, Dev 1 - PCI Bridge for Internal Graphics(IGP) */
+ Package(){0x0001FFFF, 0, INTB, 0 },
+ Package(){0x0001FFFF, 1, INTC, 0 },
+
+ /* Bus 0, Dev 2 - PCIe Bridge for x16 slot */
+ Package(){0x0002FFFF, 0, INTC, 0 },
+ Package(){0x0002FFFF, 1, INTD, 0 },
+ Package(){0x0002FFFF, 2, INTA, 0 },
+ Package(){0x0002FFFF, 3, INTB, 0 },
+
+ /* Bus 0, Dev 3 - PCIe graphics port 1 bridge */
+
+ /* Bus 0, Dev 4 - PCIe Bridge for 4x slot */
+ Package(){0x0004FFFF, 0, INTA, 0 },
+ Package(){0x0004FFFF, 1, INTB, 0 },
+ Package(){0x0004FFFF, 2, INTC, 0 },
+ Package(){0x0004FFFF, 3, INTD, 0 },
+
+ /* Bus 0, Dev 5 - General purpose PCIe bridge 5 */
+ /* Bus 0, Dev 6 - PCIe Bridge for Ethernet Chip */
+ /* Bus 0, Dev 7 - PCIe Bridge for x1 PCIe Slot */
+ /* Bus 0, Dev 8 - Southbridge port (normally hidden) */
+
+ /* Bus 0, Dev 20 - F0:SMBus/ACPI,F1:IDE;F2:HDAudio;F3:LPC;F4:PCIBridge;F5:USB */
+ Package(){0x0014FFFF, 0, INTA, 0 },
+ Package(){0x0014FFFF, 1, INTB, 0 },
+ Package(){0x0014FFFF, 2, INTC, 0 },
+ Package(){0x0014FFFF, 3, INTD, 0 },
+
+ /* Bus 0, Dev 18,19,22 - USB: OHCI @ func 0
+ * EHCI @ func 2 */
+ Package(){0x0012FFFF, 0, INTC, 0 },
+ Package(){0x0012FFFF, 1, INTB, 0 },
+
+ Package(){0x0013FFFF, 0, INTC, 0 },
+ Package(){0x0013FFFF, 1, INTB, 0 },
+
+ Package(){0x0016FFFF, 0, INTC, 0 },
+ Package(){0x0016FFFF, 1, INTB, 0 },
+
+ /* SB devices */
+ /* Bus 0, Dev 16 - USB: XHCI func 0, 1 */
+ Package(){0x0010FFFF, 0, INTC, 0 },
+ Package(){0x0010FFFF, 1, INTB, 0 },
+
+ /* Bus 0, Dev 17 - SATA controller */
+ Package(){0x0011FFFF, 0, INTD, 0 },
+
+ /* Bus 0, Dev 21 Pcie Bridge */
+ Package(){0x0015FFFF, 0, INTA, 0 },
+ Package(){0x0015FFFF, 1, INTB, 0 },
+ Package(){0x0015FFFF, 2, INTC, 0 },
+ Package(){0x0015FFFF, 3, INTD, 0 },
+ })
+
+ Name(APR0, Package(){
+ /* NB devices in APIC mode */
+ /* Bus 0, Dev 0 - F15 Host Controller */
+ Package(){0x0000FFFF, 0, 0, 16 },
+ Package(){0x0000FFFF, 1, 0, 17 },
+ Package(){0x0000FFFF, 2, 0, 18 },
+ Package(){0x0000FFFF, 3, 0, 19 },
+
+ /* Bus 0, Dev 1 - PCI Bridge for Internal Graphics(IGP) */
+ Package(){0x0001FFFF, 0, 0, 17 },
+ Package(){0x0001FFFF, 1, 0, 18 },
+
+ /* Bus 0, Dev 2 - PCIe Bridge for x16 PCIe Slot */
+ Package(){0x0002FFFF, 0, 0, 18 },
+ Package(){0x0002FFFF, 1, 0, 19 },
+ Package(){0x0002FFFF, 2, 0, 16 },
+ Package(){0x0002FFFF, 3, 0, 17 },
+
+ /* Bus 0, Dev 3 - PCIe graphics port 1 bridge */
+
+ /* Bus 0, Dev 4 - PCIe Bridge for x4 PCIe Slot black */
+ Package(){0x0004FFFF, 0, 0, 16 },
+ Package(){0x0004FFFF, 1, 0, 17 },
+ Package(){0x0004FFFF, 2, 0, 18 },
+ Package(){0x0004FFFF, 3, 0, 19 },
+
+ /* Bus 0, Dev 5 - General purpose PCIe bridge 5 */
+ /* Bus 0, Dev 6 - General purpose PCIe bridge 6 */
+ /* Bus 0, Dev 7 - PCIe Bridge for network card */
+ /* Bus 0, Dev 8 - Southbridge port (normally hidden) */
+
+ /* Bus 0, Dev 20 - F0:SMBus/ACPI, F1:IDE; F2:HDAudio; F3:LPC; F4:PCIBridge; F5:USB */
+ Package(){0x0014FFFF, 0, 0, 16 },
+ Package(){0x0014FFFF, 1, 0, 17 },
+ Package(){0x0014FFFF, 2, 0, 18 },
+ Package(){0x0014FFFF, 3, 0, 19 },
+
+ /* SB devices in APIC mode */
+ /* Bus 0, Dev 18,19,22 - USB: OHCI @ func 0
+ * EHCI @ func 2 */
+ Package(){0x0012FFFF, 0, 0, 18 },
+ Package(){0x0012FFFF, 1, 0, 17 },
+
+ Package(){0x0013FFFF, 0, 0, 18 },
+ Package(){0x0013FFFF, 1, 0, 17 },
+
+ Package(){0x0016FFFF, 0, 0, 18 },
+ Package(){0x0016FFFF, 1, 0, 17 },
+
+ /* Bus 0, Dev 16 - USB: XHCI func 0, 1 */
+ Package(){0x0010FFFF, 0, 0, 0x12},
+ Package(){0x0010FFFF, 1, 0, 0x11},
+
+ /* Bus 0, Dev 17 - SATA controller */
+ Package(){0x0011FFFF, 0, 0, 19 },
+
+ /* Bus 0, Dev 21 PCIE Bridge */
+ Package(){0x0015FFFF, 0, 0, 17 },
+ Package(){0x0015FFFF, 1, 0, 18 },
+ Package(){0x0015FFFF, 2, 0, 19 },
+ Package(){0x0015FFFF, 3, 0, 16 },
+ })
+
+ Name(PS2, Package(){
+ /* The external GFX - Hooked to PCIe slot 2 */
+ Package(){0x0000FFFF, 0, INTD, 0 },
+ Package(){0x0000FFFF, 1, INTA, 0 },
+ Package(){0x0000FFFF, 2, INTB, 0 },
+ Package(){0x0000FFFF, 3, INTC, 0 },
+ })
+ Name(APS2, Package(){
+ /* The external GFX - Hooked to PCIe slot 2 */
+ Package(){0x0000FFFF, 0, 0, 18 },
+ Package(){0x0000FFFF, 1, 0, 19 },
+ Package(){0x0000FFFF, 2, 0, 16 },
+ Package(){0x0000FFFF, 3, 0, 17 },
+ })
+
+ /* black slot */
+ Name(PS4, Package(){
+ /* PCIe slot - Hooked to PCIe slot 4 */
+ Package(){0x0000FFFF, 0, INTA, 0 },
+ Package(){0x0000FFFF, 1, INTB, 0 },
+ Package(){0x0000FFFF, 2, INTC, 0 },
+ Package(){0x0000FFFF, 3, INTD, 0 },
+ })
+ Name(APS4, Package(){
+ /* PCIe slot - Hooked to PCIe slot 4 */
+ Package(){0x0000FFFF, 0, 0, 16 },
+ Package(){0x0000FFFF, 1, 0, 17 },
+ Package(){0x0000FFFF, 2, 0, 18 },
+ Package(){0x0000FFFF, 3, 0, 19 },
+ })
+
+ Name(PS5, Package(){
+ /* PCIe slot - Hooked to PCIe slot 5 */
+ Package(){0x0000FFFF, 0, INTB, 0 },
+ Package(){0x0000FFFF, 1, INTC, 0 },
+ Package(){0x0000FFFF, 2, INTD, 0 },
+ Package(){0x0000FFFF, 3, INTA, 0 },
+ })
+ Name(APS5, Package(){
+ /* PCIe slot - Hooked to PCIe slot 5 */
+ Package(){0x0000FFFF, 0, 0, 17 },
+ Package(){0x0000FFFF, 1, 0, 18 },
+ Package(){0x0000FFFF, 2, 0, 19 },
+ Package(){0x0000FFFF, 3, 0, 16 },
+ })
+
+ Name(PS6, Package(){
+ /* PCIe slot - Hooked to PCIe slot 6 */
+ Package(){0x0000FFFF, 0, INTC, 0 },
+ Package(){0x0000FFFF, 1, INTD, 0 },
+ Package(){0x0000FFFF, 2, INTA, 0 },
+ Package(){0x0000FFFF, 3, INTB, 0 },
+ })
+ Name(APS6, Package(){
+ /* PCIe slot - Hooked to PCIe slot 6 */
+ Package(){0x0000FFFF, 0, 0, 18 },
+ Package(){0x0000FFFF, 1, 0, 19 },
+ Package(){0x0000FFFF, 2, 0, 16 },
+ Package(){0x0000FFFF, 3, 0, 17 },
+ })
+
+ Name(PS7, Package(){
+ /* The onboard Ethernet chip - Hooked to PCIe slot 7 */
+ Package(){0x0000FFFF, 0, INTD, 0 },
+ Package(){0x0000FFFF, 1, INTA, 0 },
+ Package(){0x0000FFFF, 2, INTB, 0 },
+ Package(){0x0000FFFF, 3, INTC, 0 },
+ })
+
+ Name(APS7, Package(){
+ /* The onboard Ethernet chip - Hooked to PCIe slot 7 */
+ Package(){0x0000FFFF, 0, 0, 19 },
+ Package(){0x0000FFFF, 1, 0, 16 },
+ Package(){0x0000FFFF, 2, 0, 17 },
+ Package(){0x0000FFFF, 3, 0, 18 },
+ })
+
+ Name(PBR0, Package(){
+ /* PCIx1 on SB */
+ Package(){0x0000FFFF, 0, INTA, 0 },
+ Package(){0x0000FFFF, 1, INTB, 0 },
+ Package(){0x0000FFFF, 2, INTC, 0 },
+ Package(){0x0000FFFF, 3, INTD, 0 },
+ })
+ Name(ABR0, Package(){
+ /* PCIx1 on SB */
+ Package(){0x0000FFFF, 0, 0, 0x10 },
+ Package(){0x0000FFFF, 1, 0, 0x11 },
+ Package(){0x0000FFFF, 2, 0, 0x12 },
+ Package(){0x0000FFFF, 3, 0, 0x13 },
+ })
+
+ Name(PBR1, Package(){
+ /* Onboard network */
+ Package(){0x0000FFFF, 0, INTB, 0 },
+ Package(){0x0000FFFF, 1, INTC, 0 },
+ Package(){0x0000FFFF, 2, INTD, 0 },
+ Package(){0x0000FFFF, 3, INTA, 0 },
+ })
+ Name(ABR1, Package(){
+ /* Onboard network */
+ Package(){0x0000FFFF, 0, 0, 0x11 },
+ Package(){0x0000FFFF, 1, 0, 0x12 },
+ Package(){0x0000FFFF, 2, 0, 0x13 },
+ Package(){0x0000FFFF, 3, 0, 0x10 },
+ })
+
+ /* SB PCI Bridge */
+ Name(PCIB, Package(){
+ /* PCI slots: slot 0 behind Dev14, Fun4. */
+ Package(){0x0005FFFF, 0, 0, 0x14 },
+ Package(){0x0005FFFF, 1, 0, 0x15 },
+ Package(){0x0005FFFF, 2, 0, 0x16 },
+ Package(){0x0005FFFF, 3, 0, 0x17 },
+ })
diff --git a/src/mainboard/asus/f2a85-m_fam10/acpi/sata.asl b/src/mainboard/asus/f2a85-m_fam10/acpi/sata.asl
new file mode 100644
index 0000000..46daa0e
--- /dev/null
+++ b/src/mainboard/asus/f2a85-m_fam10/acpi/sata.asl
@@ -0,0 +1,16 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2013 Sage Electronic Engineering, LLC
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+/* No SATA functionality */
diff --git a/src/mainboard/asus/f2a85-m_fam10/acpi/si.asl b/src/mainboard/asus/f2a85-m_fam10/acpi/si.asl
new file mode 100644
index 0000000..ff0c3cf
--- /dev/null
+++ b/src/mainboard/asus/f2a85-m_fam10/acpi/si.asl
@@ -0,0 +1,22 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2013 Sage Electronic Engineering, LLC
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+ Scope(\_SI) {
+ Method(_SST, 1) {
+ /* DBGO("\\_SI\\_SST\n") */
+ /* DBGO(" New Indicator state: ") */
+ /* DBGO(Arg0) */
+ /* DBGO("\n") */
+ }
+ } /* End Scope SI */
diff --git a/src/mainboard/asus/f2a85-m_fam10/acpi/sleep.asl b/src/mainboard/asus/f2a85-m_fam10/acpi/sleep.asl
new file mode 100644
index 0000000..1d553bd
--- /dev/null
+++ b/src/mainboard/asus/f2a85-m_fam10/acpi/sleep.asl
@@ -0,0 +1,96 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2013 Sage Electronic Engineering, LLC
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+/* Wake status package */
+Name(WKST,Package(){Zero, Zero})
+
+/*
+* \_PTS - Prepare to Sleep method
+*
+* Entry:
+* Arg0=The value of the sleeping state S1=1, S2=2, etc
+*
+* Exit:
+* -none-
+*
+* The _PTS control method is executed at the beginning of the sleep process
+* for S1-S5. The sleeping value is passed to the _PTS control method. This
+* control method may be executed a relatively long time before entering the
+* sleep state and the OS may abort the operation without notification to
+* the ACPI driver. This method cannot modify the configuration or power
+* state of any device in the system.
+*/
+Method(\_PTS, 1) {
+ /* DBGO("\\_PTS\n") */
+ /* DBGO("From S0 to S") */
+ /* DBGO(Arg0) */
+ /* DBGO("\n") */
+
+ /* Clear sleep SMI status flag and enable sleep SMI trap. */
+ /*Store(One, CSSM)
+ Store(One, SSEN)*/
+
+ /* On older chips, clear PciExpWakeDisEn */
+ /*if (LLessEqual(\_SB.SBRI, 0x13)) {
+ * Store(0,\_SB.PWDE)
+ *}
+ */
+
+ /* Clear wake status structure. */
+ Store(0, Index(WKST,0))
+ Store(0, Index(WKST,1))
+
+ Store (0x07, UPWS)
+} /* End Method(\_PTS) */
+
+/*
+* \_BFS OEM Back From Sleep method
+*
+* Entry:
+* Arg0=The value of the sleeping state S1=1, S2=2
+*
+* Exit:
+* -none-
+*/
+Method(\_BFS, 1) {
+ /* DBGO("\\_BFS\n") */
+ /* DBGO("From S") */
+ /* DBGO(Arg0) */
+ /* DBGO(" to S0\n") */
+}
+
+/*
+* \_WAK System Wake method
+*
+* Entry:
+* Arg0=The value of the sleeping state S1=1, S2=2
+*
+* Exit:
+* Return package of 2 DWords
+* Dword 1 - Status
+* 0x00000000 wake succeeded
+* 0x00000001 Wake was signaled but failed due to lack of power
+* 0x00000002 Wake was signaled but failed due to thermal condition
+* Dword 2 - Power Supply state
+* if non-zero the effective S-state the power supply entered
+*/
+Method(\_WAK, 1) {
+ /* DBGO("\\_WAK\n") */
+ /* DBGO("From S") */
+ /* DBGO(Arg0) */
+ /* DBGO(" to S0\n") */
+
+ Return(WKST)
+} /* End Method(\_WAK) */
diff --git a/src/mainboard/asus/f2a85-m_fam10/acpi/superio.asl b/src/mainboard/asus/f2a85-m_fam10/acpi/superio.asl
new file mode 100644
index 0000000..6f95a8a
--- /dev/null
+++ b/src/mainboard/asus/f2a85-m_fam10/acpi/superio.asl
@@ -0,0 +1,16 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2013 Sage Electronic Engineering, LLC
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+/* No Super I/O device or functionality yet */
diff --git a/src/mainboard/asus/f2a85-m_fam10/acpi/thermal.asl b/src/mainboard/asus/f2a85-m_fam10/acpi/thermal.asl
new file mode 100644
index 0000000..d769f9a
--- /dev/null
+++ b/src/mainboard/asus/f2a85-m_fam10/acpi/thermal.asl
@@ -0,0 +1,16 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2013 Sage Electronic Engineering, LLC
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+/* No thermal zone functionality */
diff --git a/src/mainboard/asus/f2a85-m_fam10/acpi/usb_oc.asl b/src/mainboard/asus/f2a85-m_fam10/acpi/usb_oc.asl
new file mode 100644
index 0000000..f5d6980
--- /dev/null
+++ b/src/mainboard/asus/f2a85-m_fam10/acpi/usb_oc.asl
@@ -0,0 +1,27 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2012 Advanced Micro Devices, Inc.
+ * Copyright (C) 2013 Sage Electronic Engineering, LLC
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+/* USB overcurrent mapping pins. */
+Name(UOM0, 0)
+Name(UOM1, 2)
+Name(UOM2, 0)
+Name(UOM3, 7)
+Name(UOM4, 2)
+Name(UOM5, 2)
+Name(UOM6, 6)
+Name(UOM7, 2)
+Name(UOM8, 6)
+Name(UOM9, 6)
diff --git a/src/mainboard/asus/f2a85-m_fam10/acpi_tables.c b/src/mainboard/asus/f2a85-m_fam10/acpi_tables.c
new file mode 100644
index 0000000..3433bfc
--- /dev/null
+++ b/src/mainboard/asus/f2a85-m_fam10/acpi_tables.c
@@ -0,0 +1,48 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2012 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <arch/acpi.h>
+#include <arch/acpigen.h>
+#include <arch/ioapic.h>
+#include <console/console.h>
+#include <cpu/amd/amdfam15.h>
+#include <device/pci.h>
+#include <device/pci_ids.h>
+#include <string.h>
+
+unsigned long acpi_fill_madt(unsigned long current)
+{
+ /* create all subtables for processors */
+ current = acpi_create_madt_lapics(current);
+
+ /* Write Hudson IOAPIC, only one */
+ current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, CONFIG_MAX_CPUS,
+ IO_APIC_ADDR, 0);
+
+ current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *)
+ current, 0, 0, 2, 0);
+ current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *)
+ current, 0, 9, 9, 0xF);
+ /* 0: mean bus 0--->ISA */
+ /* 0: PIC 0 */
+ /* 2: APIC 2 */
+ /* 5 mean: 0101 --> Edge-triggered, Active high */
+
+ /* create all subtables for processors */
+ current += acpi_create_madt_lapic_nmi((acpi_madt_lapic_nmi_t *)current, 0xff, 5, 1);
+ /* 1: LINT1 connect to NMI */
+
+ return current;
+}
diff --git a/src/mainboard/asus/f2a85-m_fam10/board_info.txt b/src/mainboard/asus/f2a85-m_fam10/board_info.txt
new file mode 100644
index 0000000..091def6
--- /dev/null
+++ b/src/mainboard/asus/f2a85-m_fam10/board_info.txt
@@ -0,0 +1,7 @@
+Category: desktop
+Board URL: http://www.asus.com/Motherboards/AMD_Socket_FM2/F2A85M/
+ROM package: DIP8
+ROM protocol: [http://www.winbond-usa.com/hq/enu/ProductAndSales/ProductLines/FlashMemory/SerialFlash/W25Q64BV.htm SPI]
+ROM socketed: y
+Flashrom support: y
+Release year: 2013
diff --git a/src/mainboard/asus/f2a85-m_fam10/bootblock.c b/src/mainboard/asus/f2a85-m_fam10/bootblock.c
new file mode 100644
index 0000000..77a9e41
--- /dev/null
+++ b/src/mainboard/asus/f2a85-m_fam10/bootblock.c
@@ -0,0 +1,23 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2016 Damien Zammit <damien at zamaudio.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <arch/io.h>
+
+void bootblock_mainboard_init(void)
+{
+ bootblock_northbridge_init();
+ bootblock_southbridge_init();
+}
diff --git a/src/mainboard/asus/f2a85-m_fam10/cmos.layout b/src/mainboard/asus/f2a85-m_fam10/cmos.layout
new file mode 100644
index 0000000..d83bb14
--- /dev/null
+++ b/src/mainboard/asus/f2a85-m_fam10/cmos.layout
@@ -0,0 +1,74 @@
+#*****************************************************************************
+#
+# This file is part of the coreboot project.
+#
+# Copyright (C) 2012 Advanced Micro Devices, Inc.
+#
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; version 2 of the License.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#*****************************************************************************
+
+entries
+
+0 384 r 0 reserved_memory
+384 1 e 4 boot_option
+388 4 r 0 reboot_bits
+392 3 e 5 baud_rate
+395 1 e 1 hw_scrubber
+396 1 e 1 interleave_chip_selects
+397 2 e 8 max_mem_clock
+399 1 e 2 multi_core
+400 1 e 1 power_on_after_fail
+412 4 e 6 debug_level
+440 4 e 9 slow_cpu
+444 1 e 1 nmi
+445 1 e 1 iommu
+456 1 e 1 ECC_memory
+728 256 h 0 user_data
+984 16 h 0 check_sum
+# Reserve the extended AMD configuration registers
+1000 24 r 0 amd_reserved
+
+enumerations
+
+#ID value text
+1 0 Disable
+1 1 Enable
+2 0 Enable
+2 1 Disable
+4 0 Fallback
+4 1 Normal
+5 0 115200
+5 1 57600
+5 2 38400
+5 3 19200
+5 4 9600
+5 5 4800
+5 6 2400
+5 7 1200
+6 6 Notice
+6 7 Info
+6 8 Debug
+6 9 Spew
+8 0 400Mhz
+8 1 333Mhz
+8 2 266Mhz
+8 3 200Mhz
+9 0 off
+9 1 87.5%
+9 2 75.0%
+9 3 62.5%
+9 4 50.0%
+9 5 37.5%
+9 6 25.0%
+9 7 12.5%
+
+checksums
+
+checksum 392 983 984
diff --git a/src/mainboard/asus/f2a85-m_fam10/devicetree.cb b/src/mainboard/asus/f2a85-m_fam10/devicetree.cb
new file mode 100644
index 0000000..0d826cc
--- /dev/null
+++ b/src/mainboard/asus/f2a85-m_fam10/devicetree.cb
@@ -0,0 +1,125 @@
+#
+# This file is part of the coreboot project.
+#
+# Copyright (C) 2012 Advanced Micro Devices, Inc.
+# Copyright (C) 2016 Damien Zammit <damien at zamaudio.com>
+#
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; version 2 of the License.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+chip northbridge/amd/amdfam10/root_complex
+
+ device cpu_cluster 0 on
+ chip cpu/amd/socket_FM2
+ device lapic 10 on end
+ end
+ end
+
+ device domain 0 on
+ subsystemid 0x1022 0x1410 inherit
+ chip northbridge/amd/amdfam10 # NB RAM Controller
+
+ device pci 0.0 on end # Root Complex
+ device pci 0.2 on end # IOMMU
+ device pci 1.0 on end # Internal Graphics P2P bridge 0x99XX
+ device pci 1.1 on end # Internal Multimedia
+ device pci 2.0 on end # PCIE SLOT0 x16 blue
+ device pci 3.0 off end # unused?
+ device pci 4.0 on end # PCIE 4x black
+ device pci 5.0 off end # unused?
+ device pci 6.0 off end # unused?
+ device pci 7.0 off end # LAN
+ device pci 8.0 off end # NB/SB Link P2P bridge
+
+ device pci 18.0 on
+ chip southbridge/amd/sb900 # it is under NB/SB Link, but on the same pci bus
+ device pci 10.0 on end # XHCI HC0
+ device pci 10.1 on end # XHCI HC1
+ device pci 11.0 on end # SATA
+ device pci 12.0 on end # USB
+ device pci 12.2 on end # USB
+ device pci 13.0 on end # USB
+ device pci 13.2 on end # USB
+ device pci 14.0 on # SMBUS
+ chip drivers/generic/generic #dimm 0
+ device i2c 50 on end # 7-bit SPD address
+ end
+ chip drivers/generic/generic #dimm 1
+ device i2c 51 on end # 7-bit SPD address
+ end
+ end # SM
+ device pci 14.1 off end # IDE 0x439c
+ device pci 14.2 on end # HDA 0x4383
+ device pci 14.3 on # LPC 0x439d
+ chip superio/ite/it8728f
+ register hwm_ctl_register = "0xc0"
+ register hwm_main_ctl_register = "0x33"
+ register hwm_adc_temp_chan_en_reg = "0x38"
+ register hwm_fan1_ctl_pwm = "0x00"
+ register hwm_fan2_ctl_pwm = "0x00"
+ register hwm_fan3_ctl_pwm = "0x00"
+
+ device pnp 2e.0 off # Floppy
+ io 0x60 = 0x3f0
+ irq 0x70 = 6
+ drq 0x74 = 2
+ end
+ device pnp 2e.1 on # Com1
+ io 0x60 = 0x3f8
+ irq 0x70 = 4
+ end
+ device pnp 2e.2 off # Com2
+ io 0x60 = 0x2f8
+ irq 0x70 = 3
+ end
+ device pnp 2e.3 off # Parallel Port
+ io 0x60 = 0x378
+ irq 0x70 = 7
+ end
+ device pnp 2e.4 on # Env Controller
+ io 0x60 = 0x290
+ io 0x62 = 0x220
+ irq 0x70 = 0
+ end
+ device pnp 2e.5 on # Keyboard
+ io 0x60 = 0x60
+ io 0x62 = 0x64
+ irq 0x70 = 1
+ end
+ device pnp 2e.6 off # Mouse
+ irq 0x70 = 12
+ end
+ device pnp 2e.7 on # GPIO
+ io 0x60 = 0x228 #SMI
+ io 0x62 = 0x300 #Simple I/O
+ io 0x64 = 0x238 #Phony resource IT8603E does not have it
+ irq 0x70 = 0
+ end
+ device pnp 2e.a off end # CIR
+ end #superio/ite/it8728f
+ end #device pci 14.3 # LPC
+ device pci 14.4 on end # PCI 0x4384
+ device pci 14.5 on end # USB 2
+ device pci 14.6 off end # Gec
+ device pci 14.7 off end # SD
+ device pci 15.0 on end # PCIe 0 - onboard PCIe 1x
+ device pci 15.1 on end # PCIe 1 onboard gigabit
+ device pci 15.2 off end # unused
+ device pci 15.3 off end # unused
+
+ end #chip southbridge/amd/sb900
+ end #18.0
+ device pci 18.1 on end
+ device pci 18.2 on end
+ device pci 18.3 on end
+ device pci 18.4 on end
+ device pci 18.5 on end
+ end #chip northbridge/amd/amdfam10
+ end #domain
+end #chip northbridge/amd/amdfam10/root_complex
diff --git a/src/mainboard/asus/f2a85-m_fam10/dsdt.asl b/src/mainboard/asus/f2a85-m_fam10/dsdt.asl
new file mode 100644
index 0000000..a58ab7e
--- /dev/null
+++ b/src/mainboard/asus/f2a85-m_fam10/dsdt.asl
@@ -0,0 +1,48 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2012 Advanced Micro Devices, Inc.
+ * Copyright (C) 2013 Sage Electronic Engineering, LLC
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+/* DefinitionBlock Statement */
+DefinitionBlock (
+ "DSDT.AML", /* Output filename */
+ "DSDT", /* Signature */
+ 0x02, /* DSDT Revision, needs to be 2 for 64bit */
+ "ASUS ", /* OEMID */
+ "COREBOOT", /* TABLE ID */
+ 0x00010001 /* OEM Revision */
+ )
+{ /* Start of ASL file */
+ /* #include <arch/x86/acpi/debug.asl> */ /* Include global debug methods if needed */
+
+ //#include "acpi/usb_oc.asl"
+
+ //#include "northbridge/amd/amdfam10/amdfam10_util.asl"
+
+ /* Globals for the platform */
+ //#include "acpi/mainboard.asl"
+
+ /* Describe the Sleep Methods (WAK, PTS, GTS, etc.) for this platform */
+ //#include "acpi/sleep.asl"
+
+ Scope(\_SB) {
+ /* global utility methods expected within the \_SB scope */
+ //#include <arch/x86/acpi/globutil.asl>
+
+ /* Describe IRQ Routing mapping for this platform (within the \_SB scope) */
+ //#include "acpi/routing.asl"
+
+ } /* End Scope(_SB) */
+}
+/* End of ASL file */
diff --git a/src/mainboard/asus/f2a85-m_fam10/get_bus_conf.c b/src/mainboard/asus/f2a85-m_fam10/get_bus_conf.c
new file mode 100644
index 0000000..f627bd6
--- /dev/null
+++ b/src/mainboard/asus/f2a85-m_fam10/get_bus_conf.c
@@ -0,0 +1,5 @@
+#include <cpu/amd/amdfam10_sysconf.h>
+
+void get_bus_conf(void)
+{
+}
diff --git a/src/mainboard/asus/f2a85-m_fam10/hdaverb b/src/mainboard/asus/f2a85-m_fam10/hdaverb
new file mode 100644
index 0000000..a544e2a
--- /dev/null
+++ b/src/mainboard/asus/f2a85-m_fam10/hdaverb
@@ -0,0 +1,24 @@
+const CODEC_ENTRY f2a85_m_alc887_VerbTbl[] = {
+> {0x11, 0x99430140},
+> {0x12, 0x411111f0},
+> {0x14, 0x01014010},
+> {0x15, 0x01011012},
+> {0x16, 0x01016011},
+> {0x17, 0x01012014},
+> {0x18, 0x01a19850},
+> {0x19, 0x02a19c60},
+> {0x1a, 0x0181305f},
+> {0x1b, 0x02214c20},
+> {0x1c, 0x411111f0},
+> {0x1d, 0x4005e601},
+> {0x1e, 0x01456130},
+> {0x1f, 0x411111f0},
+> {0xff, 0xffffffff}
+};
+
+static const CODEC_TBL_LIST CodecTableList[] =
+{
+> {0x10ec0887, (CODEC_ENTRY*)&f2a85_m_alc887_VerbTbl[0]},
+> {(UINT32)0x0FFFFFFFF, (CODEC_ENTRY*)0x0FFFFFFFFUL}
+};
+
diff --git a/src/mainboard/asus/f2a85-m_fam10/irq_tables.c b/src/mainboard/asus/f2a85-m_fam10/irq_tables.c
new file mode 100644
index 0000000..eeaf8d3
--- /dev/null
+++ b/src/mainboard/asus/f2a85-m_fam10/irq_tables.c
@@ -0,0 +1,103 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2012 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <arch/pirq_routing.h>
+#include <console/console.h>
+#include <cpu/amd/amdfam15.h>
+#include <device/pci_def.h>
+#include <stdint.h>
+#include <string.h>
+
+static void write_pirq_info(struct irq_info *pirq_info, u8 bus, u8 devfn,
+ u8 link0, u16 bitmap0, u8 link1, u16 bitmap1,
+ u8 link2, u16 bitmap2, u8 link3, u16 bitmap3,
+ u8 slot, u8 rfu)
+{
+ pirq_info->bus = bus;
+ pirq_info->devfn = devfn;
+ pirq_info->irq[0].link = link0;
+ pirq_info->irq[0].bitmap = bitmap0;
+ pirq_info->irq[1].link = link1;
+ pirq_info->irq[1].bitmap = bitmap1;
+ pirq_info->irq[2].link = link2;
+ pirq_info->irq[2].bitmap = bitmap2;
+ pirq_info->irq[3].link = link3;
+ pirq_info->irq[3].bitmap = bitmap3;
+ pirq_info->slot = slot;
+ pirq_info->rfu = rfu;
+}
+
+
+unsigned long write_pirq_routing_table(unsigned long addr)
+{
+ struct irq_routing_table *pirq;
+ struct irq_info *pirq_info;
+ u32 slot_num;
+ u8 *v;
+
+ u8 sum = 0;
+ int i;
+
+ /* Align the table to be 16 byte aligned. */
+ addr += 15;
+ addr &= ~15;
+
+ /* This table must be between 0xf0000 & 0x100000 */
+ printk(BIOS_INFO, "Writing IRQ routing tables to 0x%lx...", addr);
+
+ pirq = (void *)(addr);
+ v = (u8 *) (addr);
+
+ pirq->signature = PIRQ_SIGNATURE;
+ pirq->version = PIRQ_VERSION;
+
+ pirq->rtr_bus = 0;
+ pirq->rtr_devfn = PCI_DEVFN(0x14, 4);
+
+ pirq->exclusive_irqs = 0;
+
+ pirq->rtr_vendor = 0x1002;
+ pirq->rtr_device = 0x4384;
+
+ pirq->miniport_data = 0;
+
+ memset(pirq->rfu, 0, sizeof(pirq->rfu));
+
+ pirq_info = (void *)(&pirq->checksum + 1);
+ slot_num = 0;
+
+ /* pci bridge */
+ write_pirq_info(pirq_info, 0, PCI_DEVFN(0x14, 4),
+ 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0,
+ 0);
+ pirq_info++;
+
+ slot_num++;
+
+ pirq->size = 32 + 16 * slot_num;
+
+ for (i = 0; i < pirq->size; i++)
+ sum += v[i];
+
+ sum = pirq->checksum - sum;
+
+ if (sum != pirq->checksum) {
+ pirq->checksum = sum;
+ }
+
+ printk(BIOS_INFO, "write_pirq_routing_table done.\n");
+
+ return (unsigned long)pirq_info;
+}
diff --git a/src/mainboard/asus/f2a85-m_fam10/mainboard.c b/src/mainboard/asus/f2a85-m_fam10/mainboard.c
new file mode 100644
index 0000000..e1a1712
--- /dev/null
+++ b/src/mainboard/asus/f2a85-m_fam10/mainboard.c
@@ -0,0 +1,47 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2012 Advanced Micro Devices, Inc.
+ * Copyright (C) 2016 Damien Zammit <damien at zamaudio.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <arch/acpi.h>
+#include <arch/io.h>
+#include <console/console.h>
+#include <cpu/x86/msr.h>
+#include <device/device.h>
+#include <device/pci.h>
+#include <device/pci_def.h>
+
+static void mainboard_enable(device_t dev)
+{
+ msr_t msr;
+
+ printk(BIOS_INFO, "Mainboard " CONFIG_MAINBOARD_PART_NUMBER " Enable.\n");
+
+ msr = rdmsr(0xC0011020);
+ msr.lo &= ~(1 << 28);
+ wrmsr(0xC0011020, msr);
+
+ msr = rdmsr(0xC0011022);
+ msr.lo &= ~(1 << 4);
+ msr.lo &= ~(1 << 13);
+ wrmsr(0xC0011022, msr);
+
+ msr = rdmsr(0xC0011023);
+ msr.lo &= ~(1 << 23);
+ wrmsr(0xC0011023, msr);
+}
+
+struct chip_operations mainboard_ops = {
+ .enable_dev = mainboard_enable,
+};
diff --git a/src/mainboard/asus/f2a85-m_fam10/mptable.c b/src/mainboard/asus/f2a85-m_fam10/mptable.c
new file mode 100644
index 0000000..267c824
--- /dev/null
+++ b/src/mainboard/asus/f2a85-m_fam10/mptable.c
@@ -0,0 +1,182 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2012 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <arch/cpu.h>
+#include <arch/io.h>
+#include <arch/ioapic.h>
+#include <arch/smp/mpspec.h>
+#include <cpu/amd/amdfam15.h>
+#include <cpu/x86/lapic.h>
+#include <device/pci.h>
+#include <stdint.h>
+#include <string.h>
+
+u8 picr_data[] = {
+ 0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x0A,0xF1,0x00,0x00,0x1F,0x1F,0x1F,0x1F,
+ 0x09,0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0x1F,0x1F,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0x1F,0x1F,0x1F,0x1F
+};
+u8 intr_data[0x54] = {
+ 0x10,0x11,0x12,0x13,0x14,0x15,0x16,0x17,0x00,0x00,0x00,0x00,0x1F,0x1F,0x1F,0x1F,
+ 0x09,0x1F,0x1F,0x10,0x1F,0x10,0x1F,0x10,0x1F,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0x05,0x1F,0x1F,0x1F,0x1F,0x1F,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0x12,0x11,0x12,0x11,0x12,0x11,0x12,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0x11,0x13,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0x10,0x11,0x12,0x13
+};
+
+static void smp_add_mpc_entry(struct mp_config_table *mc, unsigned length)
+{
+ mc->mpc_length += length;
+ mc->mpc_entry_count++;
+}
+
+static void my_smp_write_bus(struct mp_config_table *mc,
+ unsigned char id, const char *bustype)
+{
+ struct mpc_config_bus *mpc;
+ mpc = smp_next_mpc_entry(mc);
+ memset(mpc, '\0', sizeof(*mpc));
+ mpc->mpc_type = MP_BUS;
+ mpc->mpc_busid = id;
+ memcpy(mpc->mpc_bustype, bustype, sizeof(mpc->mpc_bustype));
+ smp_add_mpc_entry(mc, sizeof(*mpc));
+}
+
+static void *smp_write_config_table(void *v)
+{
+ struct mp_config_table *mc;
+ int bus_isa;
+ u8 byte;
+
+ /*
+ * By the time this function gets called, the IOAPIC registers
+ * have been written so they can be read to get the correct
+ * APIC ID and Version
+ */
+ u8 ioapic_id = (io_apic_read(VIO_APIC_VADDR, 0x00) >> 24);
+ u8 ioapic_ver = (io_apic_read(VIO_APIC_VADDR, 0x01) & 0xFF);
+
+ mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
+
+ mptable_init(mc, LOCAL_APIC_ADDR);
+ memcpy(mc->mpc_oem, "AMD ", 8);
+
+ smp_write_processors(mc);
+
+ //mptable_write_buses(mc, NULL, &bus_isa);
+ my_smp_write_bus(mc, 0, "PCI ");
+ my_smp_write_bus(mc, 1, "PCI ");
+ bus_isa = 0x02;
+ my_smp_write_bus(mc, bus_isa, "ISA ");
+
+ /* I/O APICs: APIC ID Version State Address */
+ smp_write_ioapic(mc, ioapic_id, ioapic_ver, VIO_APIC_VADDR);
+
+ /* PIC IRQ routine */
+ for (byte = 0x0; byte < sizeof(picr_data); byte ++) {
+ outb(byte, 0xC00);
+ outb(picr_data[byte], 0xC01);
+ }
+
+ /* APIC IRQ routine */
+ for (byte = 0x0; byte < sizeof(intr_data); byte ++) {
+ outb(byte | 0x80, 0xC00);
+ outb(intr_data[byte], 0xC01);
+ }
+
+ /* I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */
+#define IO_LOCAL_INT(type, intr, apicid, pin) \
+ smp_write_lintsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, (intr), (apicid), (pin));
+ mptable_add_isa_interrupts(mc, bus_isa, ioapic_id, 0);
+
+ /* PCI interrupts are level triggered, and are
+ * associated with a specific bus/device/function tuple.
+ */
+#define PCI_INT(bus, dev, int_sign, pin) \
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(int_sign)), ioapic_id, (pin))
+
+ /* IOMMU */
+ PCI_INT(0x0, 0x0, 0x0, 0x10);
+ PCI_INT(0x0, 0x0, 0x1, 0x11);
+ PCI_INT(0x0, 0x0, 0x2, 0x12);
+ PCI_INT(0x0, 0x0, 0x3, 0x13);
+
+ /* Internal VGA */
+ PCI_INT(0x0, 0x01, 0x0, intr_data[0x02]);
+ PCI_INT(0x0, 0x01, 0x1, intr_data[0x03]);
+
+ /* SMBUS */
+ PCI_INT(0x0, 0x14, 0x0, 0x10);
+
+ /* HD Audio */
+ PCI_INT(0x0, 0x14, 0x0, intr_data[0x13]);
+
+ /* USB */
+ PCI_INT(0x0, 0x12, 0x0, intr_data[0x30]);
+ PCI_INT(0x0, 0x12, 0x1, intr_data[0x31]);
+ PCI_INT(0x0, 0x13, 0x0, intr_data[0x32]);
+ PCI_INT(0x0, 0x13, 0x1, intr_data[0x33]);
+ PCI_INT(0x0, 0x16, 0x0, intr_data[0x34]);
+ PCI_INT(0x0, 0x16, 0x1, intr_data[0x35]);
+ PCI_INT(0x0, 0x14, 0x2, intr_data[0x36]);
+
+ /* sata */
+ PCI_INT(0x0, 0x11, 0x0, intr_data[0x40]);
+ PCI_INT(0x0, 0x11, 0x0, intr_data[0x41]);
+
+ /* on board NIC & Slot PCIE. */
+
+ /* PCI slots */
+ device_t dev = dev_find_slot(0, PCI_DEVFN(0x14, 4));
+ if (dev && dev->enabled) {
+ u8 bus_pci = dev->link_list->secondary;
+ /* PCI_SLOT 0. */
+ PCI_INT(bus_pci, 0x5, 0x0, 0x14);
+ PCI_INT(bus_pci, 0x5, 0x1, 0x15);
+ PCI_INT(bus_pci, 0x5, 0x2, 0x16);
+ PCI_INT(bus_pci, 0x5, 0x3, 0x17);
+ }
+
+ /* PCIe Lan*/
+ PCI_INT(0x0, 0x06, 0x0, 0x13);
+
+ /* FCH PCIe PortA */
+ PCI_INT(0x0, 0x15, 0x0, 0x10);
+ /* FCH PCIe PortB */
+ PCI_INT(0x0, 0x15, 0x1, 0x11);
+ /* FCH PCIe PortC */
+ PCI_INT(0x0, 0x15, 0x2, 0x12);
+ /* FCH PCIe PortD */
+ PCI_INT(0x0, 0x15, 0x3, 0x13);
+
+ /*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */
+ IO_LOCAL_INT(mp_ExtINT, 0, MP_APIC_ALL, 0x0);
+ IO_LOCAL_INT(mp_NMI, 0, MP_APIC_ALL, 0x1);
+ /* There is no extension information... */
+
+ /* Compute the checksums */
+ return mptable_finalize(mc);
+}
+
+unsigned long write_smp_table(unsigned long addr)
+{
+ void *v;
+ v = smp_write_floating_table(addr, 0);
+ return (unsigned long)smp_write_config_table(v);
+}
diff --git a/src/mainboard/asus/f2a85-m_fam10/romstage.c b/src/mainboard/asus/f2a85-m_fam10/romstage.c
new file mode 100644
index 0000000..b756b49
--- /dev/null
+++ b/src/mainboard/asus/f2a85-m_fam10/romstage.c
@@ -0,0 +1,353 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2012 Advanced Micro Devices, Inc.
+ * Copyright (C) 2012 Rudolf Marek <r.marek at assembler.cz>
+ * Copyright (C) 2016 Damien Zammit <damien at zamaudio.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+unsigned int get_sbdn(unsigned bus);
+
+#include <arch/acpi.h>
+#include <arch/cpu.h>
+#include <arch/io.h>
+#include <arch/stages.h>
+#include <cbmem.h>
+#include <console/console.h>
+#include <cpu/amd/car.h>
+#include <cpu/x86/bist.h>
+#include <cpu/x86/lapic.h>
+#include <device/pci_def.h>
+#include <device/pci_ids.h>
+#include <device/pnp_def.h>
+#include <spd.h>
+#include <cpu/amd/model_10xxx_rev.h>
+#include <northbridge/amd/amdfam10/raminit.h>
+#include <northbridge/amd/amdfam10/amdfam10.h>
+#include <delay.h>
+#include "northbridge/amd/amdfam10/reset_test.c"
+#include <stdint.h>
+#include <string.h>
+#include <superio/ite/common/ite.h>
+#include <superio/ite/it8728f/it8728f.h>
+#include <southbridge/amd/sb900/sb900.h>
+#include <southbridge/amd/sb900/smbus.h>
+#include "northbridge/amd/amdfam10/debug.c"
+//#include "northbridge/amd/amdfam10/setup_resource_map.c"
+
+#define MMIO_NON_POSTED_START 0xfed00000
+#define MMIO_NON_POSTED_END 0xfedfffff
+#define SB_MMIO 0xFED80000
+#define SB_MMIO_MISC32(x) *(volatile u32 *)(SB_MMIO + 0xE00 + (x))
+
+#define SMBUS_IO_BASE 0xb00
+#define SMBUS_AUX_IO_BASE 0xb20
+
+#define SERIAL_DEV PNP_DEV(0x2e, IT8728F_SP1)
+#define GPIO_DEV PNP_DEV(0x2e, IT8728F_GPIO)
+
+static void writepmreg (int reg, int data)
+{
+ outb(reg, 0xCD6);
+ outb(data, 0xCD7);
+}
+
+static void activate_spd_rom(const struct mem_controller *ctrl)
+{
+ u32 iobase = SMBUS_IO_BASE;
+
+ writepmreg (0x2D, iobase >> 8);
+ writepmreg (0x2C, iobase | 1);
+ /* Set SMBUS clock to 400KHz */
+ outb(66000000 / 400000 / 4, iobase + 0x0E);
+}
+
+inline int spd_read_byte(unsigned device, unsigned address)
+{
+ return do_smbus_read_byte(SMBUS_IO_BASE, device, address);
+}
+
+static const uint8_t spd_addr_fam15[] = {
+ // Socket 0 Node 0 ("Node 0")
+ RC00, DIMM0, DIMM1, 0, 0, DIMM2, DIMM3, 0, 0,
+};
+
+#include <northbridge/amd/amdfam10/amdfam10.h>
+#include "northbridge/amd/amdfam10/raminit_sysinfo_in_ram.c"
+#include "northbridge/amd/amdfam10/pci.c"
+//#include "resourcemap.c"
+#include "cpu/amd/quadcore/quadcore.c"
+
+#include <cpu/amd/microcode.h>
+
+#include "cpu/amd/family_10h-family_15h/init_cpus.c"
+//#include "northbridge/amd/amdfam10/early_ht.c"
+
+static void sbxxx_enable_48mhzout(void)
+{
+ /* most likely programming to 48MHz out signal */
+ u32 reg32;
+ reg32 = SB_MMIO_MISC32(0x28);
+ reg32 &= 0xffc7ffff;
+ reg32 |= 0x00100000;
+ SB_MMIO_MISC32(0x28) = reg32;
+
+ reg32 = SB_MMIO_MISC32(0x40);
+ reg32 &= ~0x80u;
+ SB_MMIO_MISC32(0x40) = reg32;
+}
+
+static void set_ddr3_voltage(uint8_t node, uint8_t index) {
+ uint8_t byte;
+ uint8_t value = 0;
+
+ if (index == 0)
+ value = 0x0;
+ else if (index == 1)
+ value = 0x1;
+ else if (index == 2)
+ value = 0x4;
+ else if (index == 3)
+ value = 0x5;
+ if (node == 1)
+ value <<= 1;
+
+ /* Set GPIOs */
+ byte = pci_read_config8(PCI_DEV(0, 0x14, 3), 0xd1);
+ if (node == 0)
+ byte &= ~0x5;
+ if (node == 1)
+ byte &= ~0xa;
+ byte |= value;
+ pci_write_config8(PCI_DEV(0, 0x14, 3), 0xd1, byte);
+
+ /* Enable GPIO output drivers */
+ byte = pci_read_config8(PCI_DEV(0, 0x14, 3), 0xd0);
+ byte &= 0x0f;
+ pci_write_config8(PCI_DEV(0, 0x14, 3), 0xd0, byte);
+}
+
+void DIMMSetVoltages(struct MCTStatStruc *pMCTstat,
+ struct DCTStatStruc *pDCTstatA) {
+ u8 dimm;
+ u8 socket = 0;
+ u8 set_voltage = 0x1;
+
+ set_ddr3_voltage(socket, set_voltage);
+
+ /* Save 1.5V DIMM voltages for MCT and SMBIOS use */
+ for (dimm = 0; dimm < MAX_DIMMS_SUPPORTED; dimm++) {
+ pDCTstatA->DimmConfiguredVoltage[dimm] = set_voltage;
+ }
+ /* Allow the DDR supply voltages to settle */
+ udelay(100000);
+ printk(BIOS_DEBUG, "DIMM voltage set to index %02x\n", set_voltage);
+}
+
+unsigned int get_sbdn(unsigned int bus)
+{
+ device_t dev;
+
+ dev = PCI_DEV(0, 0x14, 0);
+ return (dev >> 15) & 0x1f;
+}
+
+void soft_reset(void)
+{
+}
+
+static void execute_memory_test(void)
+{
+ /* Test DRAM functionality */
+ uint32_t i;
+ uint32_t* dataptr;
+ printk(BIOS_DEBUG, "Writing test patterns to memory...\n");
+ for (i=0; i < 0x1000000; i = i + 8) {
+ dataptr = (void *)(0x300000 + i);
+ *dataptr = 0x55555555;
+ dataptr = (void *)(0x300000 + i + 4);
+ *dataptr = 0xaaaaaaaa;
+ }
+ printk(BIOS_DEBUG, "Done!\n");
+ printk(BIOS_DEBUG, "Testing memory...\n");
+ uint32_t readback;
+ for (i=0; i < 0x1000000; i = i + 8) {
+ dataptr = (void *)(0x300000 + i);
+ readback = *dataptr;
+ if (readback != 0x55555555)
+ printk(BIOS_DEBUG, "%p: INCORRECT VALUE %08x (should have been %08x)\n", dataptr, readback, 0x55555555);
+ dataptr = (void *)(0x300000 + i + 4);
+ readback = *dataptr;
+ if (readback != 0xaaaaaaaa)
+ printk(BIOS_DEBUG, "%p: INCORRECT VALUE %08x (should have been %08x)\n", dataptr, readback, 0xaaaaaaaa);
+ }
+ printk(BIOS_DEBUG, "Done!\n");
+}
+
+void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
+{
+ u32 val;
+ u8 byte;
+ device_t dev;
+ uint32_t bsp_apicid = 0;
+ msr_t msr;
+
+ struct sys_info *sysinfo = &sysinfo_car;
+
+ /* Limit the maximum HT speed to 2.6GHz to prevent lockups
+ * due to HT CPU <--> CPU wiring not being validated to 3.2GHz
+ */
+ sysinfo->ht_link_cfg.ht_speed_limit = 2600;
+
+ if (!cpu_init_detectedx && boot_cpu()) {
+
+ //set_bsp_node_CHtExtNodeCfgEn();
+ //enumerate_ht_chain();
+
+ /* enable SIO LPC decode */
+ dev = PCI_DEV(0, 0x14, 3);
+ byte = pci_read_config8(dev, 0x48);
+ byte |= 3; /* 2e, 2f */
+ pci_write_config8(dev, 0x48, byte);
+
+ /* enable serial decode */
+ byte = pci_read_config8(dev, 0x44);
+ byte |= (1 << 6); /* 0x3f8 */
+ pci_write_config8(dev, 0x44, byte);
+
+ sb900_pci_port80();
+
+ post_code(0x30);
+
+ /* enable SB MMIO space */
+ outb(0x24, 0xcd6);
+ outb(0x1, 0xcd7);
+
+ /* enable SIO clock */
+ sbxxx_enable_48mhzout();
+ ite_kill_watchdog(GPIO_DEV);
+ ite_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
+ ite_enable_3vsbsw(GPIO_DEV);
+ console_init();
+
+ printk(BIOS_SPEW, "CONSOLE: Hello\n");
+
+ /* turn on secondary smbus at b20 */
+ outb(0x28, 0xcd6);
+ byte = inb(0xcd7);
+ byte |= 1;
+ outb(byte, 0xcd7);
+ }
+
+ if (bist == 0)
+ bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo);
+
+ post_code(0x34);
+
+ /* Halt if there was a built in self test failure */
+ report_bist_failure(bist);
+
+ /* Load MPB */
+ val = cpuid_eax(1);
+ printk(BIOS_DEBUG, "BSP Family_Model: %08x\n", val);
+ printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx\n", cpu_init_detectedx);
+
+ set_sysinfo_in_ram(0);
+
+ //update_microcode(val);
+
+ cpuSetAMDMSR(0);
+
+ /* Pass NULL to this function to skip */
+ amd_ht_init(NULL);
+ //amd_ht_fixup(sysinfo);
+
+ post_code(0x35);
+
+ finalize_node_setup(sysinfo);
+ //setup_mb_resource_map();
+ post_code(0x36);
+
+ /* Wait for all the APs core0 started by finalize_node_setup. */
+ wait_all_core0_started();
+
+ if (IS_ENABLED(CONFIG_LOGICAL_CPUS)) {
+ /* Core0 on each node is configured. Now setup any additional cores. */
+ printk(BIOS_DEBUG, "start_other_cores()\n");
+ start_other_cores(bsp_apicid);
+ post_code(0x37);
+ wait_all_other_cores_started(bsp_apicid);
+ }
+
+ if (IS_ENABLED(CONFIG_SET_FIDVID)) {
+ msr = rdmsr(0xc0010071);
+ printk(BIOS_DEBUG, "\nBegin FIDVID MSR 0xc0010071 0x%08x 0x%08x\n", msr.hi, msr.lo);
+
+ /* FIXME: The sb fid change may survive the warm reset and only need to be done once */
+ //enable_fid_change_on_sb(sysinfo->sbbusn, sysinfo->sbdn);
+
+ post_code(0x38);
+
+ if (!warm_reset_detect(0)) { // BSP is node 0
+ init_fidvid_bsp(bsp_apicid, sysinfo->nodes);
+ } else {
+ init_fidvid_stage2(bsp_apicid, 0); // BSP is node 0
+ }
+
+ post_code(0x39);
+
+ /* show final fid and vid */
+ msr=rdmsr(0xc0010071);
+ printk(BIOS_DEBUG, "End FIDVIDMSR 0xc0010071 0x%08x 0x%08x\n", msr.hi, msr.lo);
+ }
+
+ post_code(0x3a);
+
+ set_ddr3_voltage(0, 1);
+
+ post_code(0x3b);
+
+ ///* Set up peripheral control lines */
+ //set_peripheral_control_lines();
+ fill_mem_ctrl(sysinfo->nodes, sysinfo->ctrl, spd_addr_fam15);
+
+ post_code(0x40);
+ printk(BIOS_DEBUG, "do raminit...");
+ raminit_amdmct(sysinfo);
+ printk(BIOS_DEBUG, "done\n");
+ post_code(0x41);
+
+ execute_memory_test();
+
+ post_code(0x42);
+
+ cbmem_initialize_empty();
+
+ amdmct_cbmem_store_info(sysinfo);
+
+ post_cache_as_ram();
+
+ post_code(0xee); /* Should never see this post code. */
+}
+
+BOOL AMD_CB_ManualBUIDSwapList (u8 node, u8 link, const u8 **List)
+{
+ /* Force BUID to 0 */
+ static const u8 swaplist[] = { 0xFF, CONFIG_HT_CHAIN_UNITID_BASE,
+ CONFIG_HT_CHAIN_END_UNITID_BASE, 0xFF };
+ if ((node == 0) && (link == 0)) { /* BSP SB link */
+ *List = swaplist;
+ return 1;
+ }
+
+ return 0;
+}
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