[coreboot-gerrit] Patch merged into coreboot/master: nb/intel/sandybridge: Start PEG link training

[gerrit at coreboot.org]

the following patch was just integrated into master:
commit e4f9d5c70ae3396a0005de7ea10709e74f003980
Author: Patrick Rudolph <siro at das-labor.org>
Date:   Thu Oct 15 11:09:15 2015 +0200

    nb/intel/sandybridge: Start PEG link training
    
    Issue observed:
    The PCIe Root port shows up in GNU/Linux but no PCIe device
    is being detected.
    
    Test system:
    * Gigabyte GA-B75M-D3H (Intel Pentium CPU G2130)
    * Lenovo T530 (Intel Core i5-3320M CPU)
    
    Problem description:
    The PEG Root port link training on Ivy Bridge needs to be manually started.
    
    Problem solution:
    The bits are set in early_init to meet PCIe reset timeout of 100msec.
    The bits should be set in PCI device enable function, but this causes the
    PCI enumeration to not detect the card, as it's still booting. Adding
    a fixed delay of 100msec resolves this problem, but this would
    increase boot time.
    Read the PCI base revision mask to make sure it's any IvyBridge CPU.
    Don't run the code on MRC path as it has its own PEG initilization code.
    
    Tested with:
    * Nvidia NVS 5400M (PCIe2)
    * ATI Radeon HD4780 (PCIe2)
    * Nvidia GeForce 8600 GT (PCIe1)
    
    Untested:
    * PCIe3 devices
    
    Final test results:
    The PEG device shows up under GNU/Linux and can be used without issues.
    
    Change-Id: Id8cfc43e5c4630b0ac217d98bb857c3308e6015b
    Signed-off-by: Patrick Rudolph <siro at das-labor.org>
    Reviewed-on: https://review.coreboot.org/11917
    Tested-by: build bot (Jenkins)
    Reviewed-by: Martin Roth <martinroth at google.com>


See https://review.coreboot.org/11917 for details.

-gerrit