[coreboot-gerrit] Patch merged into coreboot/master: x86: add coreboot table entry for TSC info

[gerrit at coreboot.org]

the following patch was just integrated into master:
commit e0969aec2573872b9f528e33edd2cf3fb84c5948
Author: Aaron Durbin <adurbin at chromium.org>
Date:   Wed Feb 10 10:56:06 2016 -0600

    x86: add coreboot table entry for TSC info
    
    The 8254 (Programmable Interrupt Timer) is becoming optional
    on x86 platforms -- either from saving power or not including it
    at all. To allow a payload to still use a TSC without doing
    calibration provide the TSC frequency information in the coreboot
    tables. That data is provided by code/logic already employed
    by platform. If tsc_freq_mhz() returns 0 or
    CONFIG_TSC_CONSTANT_RATE is not selected the coreboot table
    record isn't created.
    
    BUG=chrome-os-partner:50214
    BRANCH=glados
    TEST=With all subsequent patches confirmed TSC is picked up in
         libpayload.
    
    Change-Id: Iaeadb85c2648587debcf55f4fa5351d0c287e971
    Signed-off-by: Aaron Durbin <adurbin at chromium.org>
    Reviewed-on: https://review.coreboot.org/13670
    Tested-by: build bot (Jenkins)
    Reviewed-by: Furquan Shaikh <furquan at google.com>
    Reviewed-by: Andrey Petrov <andrey.petrov at intel.com>


See https://review.coreboot.org/13670 for details.

-gerrit