[coreboot-gerrit] Patch set updated for coreboot: FSP2.0: Add coreboot<->FSP header files
Andrey Petrov (andrey.petrov@intel.com)
gerrit at coreboot.org
Fri Feb 26 03:44:27 CET 2016
Andrey Petrov (andrey.petrov at intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13796
-gerrit
commit 741d430138337eb5936d213dc0f13fad83f87d58
Author: Andrey Petrov <andrey.petrov at intel.com>
Date: Thu Feb 25 14:13:12 2016 -0800
FSP2.0: Add coreboot<->FSP header files
This adds important header files that specify calling interface between
coreboot and FSP.
Change-Id: I393601c91e3c3f630e0fc899f1140ecefed8ecba
Signed-off-by: Andrey Petrov <andrey.petrov at intel.com>
---
src/drivers/intel/Kconfig | 1 +
src/drivers/intel/Makefile.inc | 1 +
src/drivers/intel/fsp2_0/Kconfig | 42 +++++++++
src/drivers/intel/fsp2_0/Makefile.inc | 11 +++
src/drivers/intel/fsp2_0/include/fsp/api.h | 101 +++++++++++++++++++++
src/drivers/intel/fsp2_0/include/fsp/info_header.h | 45 +++++++++
src/drivers/intel/fsp2_0/include/fsp/util.h | 42 +++++++++
7 files changed, 243 insertions(+)
diff --git a/src/drivers/intel/Kconfig b/src/drivers/intel/Kconfig
index 19986f4..e5525d8 100644
--- a/src/drivers/intel/Kconfig
+++ b/src/drivers/intel/Kconfig
@@ -14,5 +14,6 @@
##
source src/drivers/intel/fsp1_1/Kconfig
+source src/drivers/intel/fsp2_0/Kconfig
source src/drivers/intel/gma/Kconfig
source src/drivers/intel/i210/Kconfig
diff --git a/src/drivers/intel/Makefile.inc b/src/drivers/intel/Makefile.inc
index e54f07b..67c1163 100644
--- a/src/drivers/intel/Makefile.inc
+++ b/src/drivers/intel/Makefile.inc
@@ -2,4 +2,5 @@ subdirs-y += gma
subdirs-$(CONFIG_GENERATE_SMBIOS_TABLES) += wifi
subdirs-$(CONFIG_PLATFORM_USES_FSP1_0) += fsp1_0
subdirs-$(CONFIG_PLATFORM_USES_FSP1_1) += fsp1_1
+subdirs-$(CONFIG_PLATFORM_USES_FSP2_0) += fsp2_0
subdirs-$(CONFIG_DRIVER_INTEL_I210) += i210
diff --git a/src/drivers/intel/fsp2_0/Kconfig b/src/drivers/intel/fsp2_0/Kconfig
new file mode 100644
index 0000000..a05d8de
--- /dev/null
+++ b/src/drivers/intel/fsp2_0/Kconfig
@@ -0,0 +1,42 @@
+config PLATFORM_USES_FSP2_0
+ bool
+ help
+ Include FSP 2.0 wrappers and functionality
+
+if PLATFORM_USES_FSP2_0
+
+comment "Intel FSP 2.0"
+
+config ADD_FSP_BINARIES
+ bool "Add Intel FSP 2.0 binaries to CBFS"
+ help
+ Add the FSP-M and FSP-S binaries to CBFS. Note that coreboot does not
+ use the FSP-T binary, so that will not be included.
+
+config FSP_M_FILE
+ string "Intel FSP-M (memory init) binary path and filename"
+ depends on ADD_FSP_BINARIES
+ help
+ The path and filename of the Intel FSP-M binary for this platform.
+
+config FSP_S_FILE
+ string "Intel FSP-S (silicon init) binary path and filename"
+ depends on ADD_FSP_BINARIES
+ help
+ The path and filename of the Intel FSP-S binary for this platform.
+
+
+config ADD_VBT_DATA_FILE
+ bool "Add a Video Bios Table (VBT) binary to CBFS"
+ help
+ Add a VBT file data file to CBFS. The VBT describes the integrated
+ GPU and connections, and is needed by FSP in order to initialize the
+ display.
+
+config VBT_FILE
+ string "VBT binary path and filename"
+ depends on ADD_VBT_DATA_FILE
+ help
+ The path and filename of the VBT binary for this platform.
+
+endif # PLATFORM_USES_FSP2_0
diff --git a/src/drivers/intel/fsp2_0/Makefile.inc b/src/drivers/intel/fsp2_0/Makefile.inc
new file mode 100644
index 0000000..61faefa
--- /dev/null
+++ b/src/drivers/intel/fsp2_0/Makefile.inc
@@ -0,0 +1,11 @@
+romstage-y += hand_off_block.c
+romstage-y += util.c
+romstage-y += memory_init.c
+
+ramstage-y += graphics.c
+ramstage-y += hand_off_block.c
+ramstage-y += notify.c
+ramstage-y += silicon_init.c
+ramstage-y += util.c
+
+CPPFLAGS_common += -I$(src)/drivers/intel/fsp2_0/include
diff --git a/src/drivers/intel/fsp2_0/include/fsp/api.h b/src/drivers/intel/fsp2_0/include/fsp/api.h
new file mode 100644
index 0000000..aae17e8
--- /dev/null
+++ b/src/drivers/intel/fsp2_0/include/fsp/api.h
@@ -0,0 +1,101 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2015 Intel Corp.
+ * (Written by Alexandru Gagniuc <alexandrux.gagniuc at intel.com> for Intel Corp.)
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+#ifndef _FSP2_0_API_H_
+#define _FSP2_0_API_H_
+
+#include <stddef.h>
+#include <memrange.h>
+
+enum fsp_status {
+ FSP_SUCCESS = 0x00000000,
+ FSP_INVALID_PARAMETER = 0x80000002,
+ FSP_UNSUPPORTED = 0x80000003,
+ FSP_NOT_READY = 0x80000006,
+ FSP_DEVICE_ERROR = 0x80000007,
+ FSP_OUT_OF_RESOURCES = 0x80000009,
+ FSP_VOLUME_CORRUPTED = 0x8000000a,
+ FSP_NOT_FOUND = 0x8000000a,
+ FSP_TIMEOUT = 0x80000012,
+ FSP_ABORTED = 0x80000015,
+ FSP_INCOMPATIBLE_VERSION = 0x80000010,
+ FSP_SECURITY_VIOLATION = 0x8000001a,
+ FSP_CRC_ERROR = 0x8000001b,
+};
+
+enum fsp_notify_phase {
+ AFTER_PCI_ENUM = 0x20,
+ READY_TO_BOOT = 0x40
+};
+
+
+/* Opaque structures. These are platform-specific. */
+struct FSPM_UPD;
+struct FSPS_UPD;
+
+/* Main FSP stages */
+enum fsp_status fsp_memory_init(void **hob_list, struct range_entry *r);
+enum fsp_status fsp_silicon_init(struct range_entry *r);
+enum fsp_status fsp_notify(enum fsp_notify_phase phase);
+
+/* Callbacks for updating stage-specific parameters */
+void platform_fsp_memory_init_params_cb(struct FSPM_UPD *memupd);
+void platform_fsp_silicon_init_params_cb(struct FSPS_UPD *silupd);
+
+/*
+ * # DOCUMENTATION:
+ *
+ * This file defines the interface between coreboot and the FSP 2.0 wrapper
+ * fsp_memory_init(), fsp_silicon_init(), and fsp_notify() are the main entry
+ * points and map 1:1 to the FSP entry points of the same name.
+ *
+ * ### fsp_memory_init():
+ * - hob_list: retuns a pointer to the HOB storage area created by FSP
+ * - r: memory range that the binary is allowed to be loaded into
+ *
+ * This function is responsible for loading and executing the memory
+ * initialization code from the FSP-M binary. It expects this binary to reside
+ * in cbfs as FSP_M_FILE.
+ *
+ * The function takes one parameter, which is described below, but does not
+ * take in memory parameters as an argument. The memory parameters can be filled
+ * in with platform_fsp_memory_init_params_cb(). This is a callback symbol
+ * that fsp_memory_init() will call. The platform must provide this symbol.
+ *
+ * FSP returns information about the memory layout in a series of structures
+ * called hand-off-blocks (HOB). The "hob_list" output parameter will point to
+ * the start of the HOB list. The fsp reserved region will also be described by
+ * one of the HOBs. For more information on parsing these structures, see
+ * fsp/util.h
+ *
+ *
+ * ### fsp_silicon_init():
+ * - r: memory range that the binary is allowed to be loaded into
+ *
+ * This function is responsible for loading and executing the silicon
+ * initialization code from the FSP-S binary. It expects this binary to reside
+ * in cbfs as FSP_S_FILE.
+ *
+ * Like fsp_memory_init(), it provides a callback to fill in FSP-specific
+ * parameters, via platform_fsp_silicon_init_params_cb(). The platform must
+ * also provide this symbol.
+ *
+ *
+ * ### fsp_notify():
+ * - phase: Which FSP notification phase
+ *
+ * This function is responsible for loading and executing the notify code from
+ * the FSP-S binary. It expects that fsp_silicon_init() has already been called
+ * succesfully, and that the FSP-S binary is still loaded into memory.
+ */
+
+#endif /* _FSP2_0_API_H_ */
diff --git a/src/drivers/intel/fsp2_0/include/fsp/info_header.h b/src/drivers/intel/fsp2_0/include/fsp/info_header.h
new file mode 100644
index 0000000..a6cc49f
--- /dev/null
+++ b/src/drivers/intel/fsp2_0/include/fsp/info_header.h
@@ -0,0 +1,45 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2015 Intel Corp.
+ * (Written by Alexandru Gagniuc <alexandrux.gagniuc at intel.com> for Intel Corp.)
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+#ifndef _FSP2_0_INFO_HEADER_H_
+#define _FSP2_0_INFO_HEADER_H_
+
+#include <stdint.h>
+#include <stdlib.h>
+#include <types.h>
+
+#define FSP_HDR_OFFSET 0x94
+#define FSP_HDR_LEN 0x48
+#define FSP_HDR_SIGNATURE "FSPH"
+#define FSP_HDR_ATTRIB_FSPT (0b0001 << 28)
+#define FSP_HDR_ATTRIB_FSPM (0b0010 << 28)
+#define FSP_HDR_ATTRIB_FSPS (0b0011 << 28)
+
+struct fsp_header {
+ uint32_t fsp_revision;
+ size_t image_size;
+ uintptr_t image_base;
+ uint32_t image_attribute;
+ size_t cfg_region_offset;
+ size_t cfg_region_size;
+ size_t notify_phase_entry_offset;
+ size_t memory_init_entry_offset;
+ size_t silicon_init_entry_offset;
+ char image_id[sizeof(uint64_t) + 1];
+ uint8_t revision;
+};
+
+enum cb_err fsp_identify(struct fsp_header *hdr, const void *fsp_blob);
+void fsp_print_header_info(const struct fsp_header *hdr);
+void fsp_print_upd_info(const struct fsp_header *hdr, void *cfg_blob);
+
+#endif /* _FSP2_0_INFO_HEADER_H_ */
diff --git a/src/drivers/intel/fsp2_0/include/fsp/util.h b/src/drivers/intel/fsp2_0/include/fsp/util.h
new file mode 100644
index 0000000..69e545e
--- /dev/null
+++ b/src/drivers/intel/fsp2_0/include/fsp/util.h
@@ -0,0 +1,42 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2015 Intel Corp.
+ * (Written by Alexandru Gagniuc <alexandrux.gagniuc at intel.com> for Intel Corp.)
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+#ifndef _FSP2_0_UTIL_H_
+#define _FSP2_0_UTIL_H_
+
+#include <boot/coreboot_tables.h>
+#include <fsp/info_header.h>
+#include <device/resource.h>
+#include <memrange.h>
+
+/*
+ * Hand-off-block handling functions that depend on CBMEM, and thus can only
+ * be used after cbmem_initialize().
+ */
+void fsp_save_hob_list(void *hob_list_ptr);
+const void *fsp_get_hob_list(void);
+const void *fsp_find_extension_hob_by_uuid(const uint8_t *uuid, size_t *size);
+enum cb_err fsp_fill_lb_framebuffer(struct lb_framebuffer *framebuffer);
+/*
+ * Hand-off-block utilities which do not depend on CBMEM, but need to be passed
+ * the HOB list explicitly.
+ */
+void fsp_find_reserved_memory(struct resource *res, const void *hob_list);
+void fsp_print_memory_resource_hobs(const void *hob_list);
+
+/* Load an FSP binary into CBFS, and fill the associated fsp_header struct */
+enum cb_err fsp_load_binary(struct fsp_header *hdr, const char *name,
+ struct range_entry *r);
+/* Load a vbt.bin file for graphics. Returns 0 if a valid VBT is not found. */
+uintptr_t fsp_load_vbt(void);
+
+#endif /* _FSP2_0_UTIL_H_ */
More information about the coreboot-gerrit
mailing list